LPC2148 Quicksheet v1.

0
Documented by Kaushik Shrestha (kaushik.shrestha@gmail.com) P0.24, P0.26, P0.27 are not available P1.0 to P1.15 are not available

PINSEL
Registers
PINSEL0 0xE002C000 PINSEL1 0xE002C004 PINSEL2 0xE002C014

PINSEL0 0xE002C000 Bit Symbol 00

0-1 2-3 3-4 6-7 8-9 10-11 12-13 14-15 16-17 18-19 20-21 22-23 24-25 26-27 28-29 30-31 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15

01
TXD RXD SCL0 SDA0 SCK0 (UART0) (UART0) (I C0) (I C0) (SPI0)
2 2

10
PWM1 PWM3 CAP0.0 (Timer0) MAT0.0 (Timer0) CAP0.1 (Timer0) MAT0.1 (Timer0) CAP 0.2 (Timer0) PWM2 PWM4 PWM6 CAP1.0 (Timer1) CAP1.1 (Timer1) MAT1.0 (Timer1) MAT1.1 (Timer1) EINT1 EINT2

11
EINT0 EINT1 AD0.6 AD0.7 AD1.0 EINT2 AD1.1 EINT3 AD1.2 SCL1 (I C1) AD1.3 AD1.4 SDA1 (I C1) AD1.5
2 2

MISO0 (SPI0) MOSI0 (SPI0) SSEL0 TXD RXD RTS CTS DSR DTR DCD RI (SPI0) (UART1) (UART1) (UART1) (UART1) (UART1) (UART1) (UART1) (UART1)

PINSEL1 0xE002C004 Bit Symbol 00

0-1 2-3 3-4 6-7 8-9 10-11 12-13 14-15 16-17 18-19 20-21 22-23 24-25 26-27 28-29 30-31 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.24 P0.25 P0.26 P0.27 P0.28 P0.29 P0.30 P0.31 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.25 P0.28 P0.29 P0.30 P0.31

01
EINT0 CAP1.2 (Timer1) CAP1.3 (Timer1) MAT1.2 (Timer1) MAT1.3 (Timer1) PWM5 AD1.7 VBUS AD0.4 AD0.1 AD0.2 AD0.3 UP_LED

10
MAT0.2 SCK1 (SSP) MISO1 (SSP) MOSI1 (SSP) SSEL1 AD1.6 CAP0.0 (Timer0) CAP0.2 (Timer0) CAP0.3 (Timer0) EINT3 CONNECT (SSP)

11
CAP0.2 MAT1.2 (Timer1) MAT1.3 (Timer1) CAP1.2 (Timer1) EINT3 CAP1.3 (Timer1) MAT0.0 (Timer0) MAT0.2 (Timer0) MAT0.3 (Timer0) CAP0.0 (Timer0) -

PINSEL2 0xE002C014 Bit Symbol 0 0-1 2 GPIO/DEBUG P1.36-26 are used as GPIO pins 3 GPIO/TRACE P1.25-16 are used as GPIO pins 4-31 -

1 P1.36-26 are used as a Debug port P1.25-16 are used as a Trace port

GPIO
Pins
P0.0 - P0.31 P1.16 - P1.31 //PINS available on P0 and P1 for GPIO

Registers
1) IO0DIR 0xE0028008 IO1DIR 0xE0028018 2) IO0SET 0xE0028004 IO1SET 0xE0028014 3) IO0CLR 0xE002800C IO1CLR 0xE002801C 4) IO0PIN 0xE0028000 IO1PIN 0xE0028010 //set an IO pin to input(0) or output(1)

//set an IO pin to high (i.e. connect to 3.3V source) if set to output

//set an IO pin to low (i.e. connect to GND) if set to output

//to read if pin is high or low

ADC
Pins
AD0.1 - AD0.4 AD0.6 - AD0.7 AD1.0 - AD1.7 //PINS available on P0 and P1 for ADC

Registers
1) AD0CR 0xE0034000 AD1CR 0xE0060000 Bit 7-0 15-8 16 Symbol SEL CLKDIV BURST //A/D Control Register

19-17 CLKS 21 PDN 26-24 START 27 EDGE

// To use appropriate AD0.x/AD1.x pin(channel) out of AD0.0 to AD0.7 // value to divide PCLK (12MHz usually) by to determine which speed the A/D converter should operate at (up to a maximum of 4.5MHz) // If set to 0, repeated conversions will stop except the present conversion; START bits must be 000 when BURST=1 or conversions won't start // Takes value 000 (10 bits) to 111 (3 bits) indicate the range of values // 0 (power down - default) or 1 (operational) // 000 No start 001 Start conversion now 010-111 Start conversion when the edge selected by bit 27 occurs on... // significant only when the START field contains 010-111

2) AD0DR0 AD1DR0 AD0DR1 AD1DR1 AD0DR7 AD1DR7 Bit 15-6 30 31

0xE0034010 0xE0060010 0xE0034014 0xE0060014 0xE003402C 0xE006002C

A/D Channel 0 Data Register - contains the result of the most recent conversion completed on channel 0 A/D Channel 1 Data Register - contains the result of the most recent conversion completed on channel 1 A/D Channel 7 Data Register - contains the result of the most recent conversion completed on channel 7

Symbol RESULT OVERRUN DONE

//if DONE is 1 it will contain the result of A/D conversion as 10-bit number //set to 1 if the results of conversion were lost when converting in BURST mode //set to 1 when conversion is complete. Cleared when this register is read

3) AD0GDR AD0GDR Bit 15-6 26-24 30 31

0xE0034004 0xE0060004

A/D Global Data Register. This register contains the ADCs DONE bit and the result of the most recent A/D conversion

Symbol RESULT CHANNEL OVERRUN DONE

//if DONE is 1 it will contain the result of A/D conversion as 10-bit number //contain the channel from which the RESULT bits were converted (000 111) //set to 1 if the results of conversion were lost when converting in BURST mode //set to 1 when a conversion is complete. Cleared when this register is read

UART
Pins
RXD0 RXD1 TXD0 TXD1 // Serial input (PINSEL0 bits 0-1 value 01) // Serial input (PINSEL0 bits 16-17 value 01) // Serial output (PINSEL0 bits 2-3 value 01) // Serial output (PINSEL0 bits 18-19 value 01)

Registers
1) U0FCR 0xE000C008 U1FCR 0xE0010008 Bit 0 1 2 7-6 Symbol FIFO enable RX FIFO Reset TX FIFO Reset RX trigger level // FIFO control registers

//00 (level 0) 11 (level 3)

2) U0LCR 0xE000C00C U1LCR 0xE001000C Bit 1-0 2 3 5-4 6 7

// Line control registers

Symbol Word length select // 00 (5-bit character) 11 (8-bit character) Stop bit select // 0 (1 stop bit), 1 (2 stop bits) Parity Enable Parity select // 00 (odd parity) - 01 (even parity) 10 (Forced "1" stick parity) 11 (Forced "0" stick) Enable break transmission DLAB // Divisor Latch Access Bit

3) U0RBR 0xE000C000 U1RBR 0xE0010000 4) U0THR 0xE000C000 U1THR 0xE0010000 5) U0DLL 0xE000C000 U1DLL 0xE0010000

// (8-bit register Read only) contains top byte (oldest) of the RX FIFO when DLAB=0

// (8-bit register Write only) to write into top byte (newest) of the TX FIFO when DLAB=0

// holds lower 8 bits of the divisor used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock

U0DLM 0xE000C004 U1DLM 0xE0010004 6) U0FDR 0xE000C028 U1FDR 0xE0010028 Bit 3-0 7-4 Symbol DIVADDVAL MULVAL

// holds higher 8 bits of the divisor used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock

// Fractional Divider Register

// if DIVADDVAL > 0 and UxDLM = 0, the value of UxDLL register must be 3 or greater

The value of MULVAL and DIVADDVAL should comply with the following conditions: 1. 0 < MULVAL <= 15 2. 0 <= DIVADDVAL <= 15 7) U0LSR 0xE000C014 U1LSR 0xE0010014 Bit 0 1 2 3 4 5 6 7

// Line Status Register (Read-only) provides status information on the UART1 TX and RX

If value = 1 Receiver Data Ready (i.e. U1RBR contains valid data) Overrun Error Parity Error Framing Error Break Interrupt Transmitter Holding Register Empty Transmitter Empty Error in RX FIFO

8) U1MCR 0xE0010010 // UART1 Modem Control Register 9) U1MSR 0xE0010018 // UART1 Modem Status Register

Timers
Pins
CAP0.0 CAP0.3 CAP1.0 CAP1.3 CAP0.0 (3 pins) CAP0.1 (1 pin) CAP0.2 (3 pin) CAP0.3 (1 pin) CAP1.0 (1 pin) CAP1.1 (1 pin) CAP1.2 (2 pins) CAP1.3 (2 pins) MAT0.0 MAT0.3 MAT1.0 MAT1.3 MAT0.0 (2 pins) MAT0.1 (1 pin) MAT0.2 (2 pin) MAT0.3 (1 pin) MAT1.0 (1 pin) MAT1.1 (1 pin) MAT1.2 (2 pins) MAT1.3 (2 pins) // (input) Capture Signals - A transition on a capture pin can be configured to load one of the // capture registers with the value in the Timer Counter and optionally generate an interrupt P0.2 P0.4 P0.6 P0.29 P0.10 P0.11 P0.17 P0.18 P0.22 P0.30 P0.16 P0.28

P0.19 P0.21

// External Match Output

P0.3 P0.5 P0.16 P0.29 P0.12 P0.13 P0.17 P0.18

P0.22 P0.28

P0.19 P0.20

Registers
1) T0IR T1IR Bit 0 1 2 3 4 5 6 7 0xE0004000 0xE0008000 Symbol MR0 Interrupt MR1 Interrupt MR2 Interrupt MR3 Interrupt CR0 Interrupt CR1 Interrupt CR2 Interrupt CR3 Interrupt // Timer Interrupt Registers

2) T0TCR 0xE0004004 T1TCR 0xE0008004 Bit 0 1 7:2

// Timer Control Registers

Symbol Counter Enable // Timer Counter and Prescale Counter are enabled for counting Counter Reset // Timer Counter and Prescale Counter are reset on the next positive edge of PCLK Reserved

3) T0CTCR 0xE0004070 T1CTCR 0xE0008070 Bit 1-0

// Count Control Register

Description 00 Timer Mode: 01 Counter Mode: 10 Counter Mode: 11 Counter Mode: 00 01 10 11 -

PC (Prescale counter) incremented on every rising PCLK edge TC incremented on rising edges on the CAP input selected by bits 3:2 TC incremented on falling edges on the CAP input selected by bits 3:2 TC incremented on both edges on the CAP input selected by bits 3:2

3-2

CAPx.0 (CAP0.0 for TIMER0 and CAP1.0 for TIMER1) CAPx.1 (CAP0.1 for TIMER0 and CAP1.1 for TIMER1) CAPx.2 (CAP0.2 for TIMER0 and CAP1.2 for TIMER1) CAPx.3 (CAP0.3 for TIMER0 and CAP1.3 for TIMER1)

7-4

4) T0TC T1TC 5) T0PR T1PR 6) T0PC T1PC

0xE0004008 0xE0008008

// Timer Counter (TC) - Incremented when Prescale Counter (PC) reaches its terminal count

0xE000400C 0xE000800C

// Prescale Register (PR) - Specifies the maximum value for the PC

0xE0004010 0xE0008010

// Prescale Counter (PC) - Incremented on every PCLK

7) T0MR0 T0MR1 T0MR2 T0MR3 T0MR0 T0MR1 T0MR2 T0MR3

0xE0004018 0xE000401C 0xE0004020 0xE0004024 0xE0004018 0xE000401C 0xE0004020 0xE0004024

// Match Registers

Match Register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically

8) T0MCR T1MCR Bit 0 1 2 5-3 8-6 11-9 15-12

0xE0004014 0xE0008014

// Match Control Registers

Symbol MR0I // interrupt to be generated when MR0 matches the value in the TC MR0R // TC to be reset when MR0 matches the value in the TC MR0S // TC and PC to be stopped when MR0 matches the value in the TC similar similar similar -

9) T0CR0 T0CR1 T0CR2 T0CR3 T0CR0 T0CR1 T0CR2 T0CR3

0xE000402C 0xE0004030 0xE0004034 0xE0004038 0xE000802C 0xE0008030 0xE0008034 0xE000803C

// Capture Registers

Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin.

10) T0CCR 0xE0004028 T1CCR 0xE0008028 Bit 0 1 2 5-3 8-6 11-9 15-12 Symbol CAP0RE CAP0FE CAP0I similar similar similar -

// Capture Control Register - determine if the capture function is enabled and whether a capture event happens on the rising, the falling edge, or on both edges of CAPx.0

// Capture on CAPx.0 rising edge // Capture on CAPx.0 falling edge // Interrupt generation on CAPx.0 event