A Multi-Standard Monolithic CMOS RF Transceiver

Thomas Cho, Jacques Rudell, Jeff Ou, Todd Weigandt, Sekhar Narayanaswami, Srenik Mehta, George Chien, Carrol Barrett, Francesco Brianti*, and Prof. Paul Gray. University of California, Berkeley *SGS Thomson

Thomas B. Cho, UC Berkeley

Outline

. . . . .
Thomas B. Cho, UC Berkeley

Background/Motivation A monolithic CMOS RF transceiver Design considerations Key building blocks Future plan

Low Power Terminal Design

Architecture Optimization Low-Power RF Design BATTERY (40+ lbs) Low-Power ADC/DAC Low-Power Digital and DSP Power-Optimized Display Etc

Next Step: Multi-Standard, Adaptive Modes of Communication

Thomas B. Cho, UC Berkeley

Overall Objective
Single RF Modem with interface capability to:

. . . .

Public Cellular Network Cordless Phones/PBXs Wireless LANs Other emerging PCS Systems

Focus of this research:

What are the important technical problems from the perspective of the RF modem design?

Thomas B. Cho, UC Berkeley

Adaptive, Multistandard RF Modems

BATTERY (40+ lbs)

Thomas B. Cho, UC Berkeley

Motivation
Design Goal:

Design Objectives:
Low power consumption Low cost implementation Multi-Standard capability

. . . .

Radio transceiver for personal communications.

Thomas B. Cho, UC Berkeley

. .

Research Goals
Single-chip implementation
Integrate both RF & Baseband circuits on the same chip Eliminate off-chip high frequency signal paths to reduce off-chip components for low power, low cost & smaller form factors (ext. LC-tank, ext. IF BPF, ..) Baseband digital signal processing for programmable multistandard capability

CMOS technology
High integration and low cost

Thomas B. Cho, UC Berkeley

Conventional Approach
RF LNA/Mixer
65 mW

IF AGC
60 mW

Receiver
IF Mixer
45 mW ADC 90 I

50mW VCO 40 mW VCO

ADC

250mW per ADC

DAC 90 DAC

Transmitter

A typical example of RF Transceiver

Thomas B. Cho, UC Berkeley

VCO

20 mW per DAC

Modulator
165 mW

40 mW

Our Approach

Using DECT standard as a vehicle to study various problems/issues

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Thomas B. Cho, UC Berkeley

A Quasi-Direct Conversion Approach

Thomas Cho Thomas Cho Francesco Brianti George Chien Jacques Rudell I ADC Q Frequency Synthesizer Todd Weigandt Srenik Mehta Carol Barrett LPF Sekhar Narayanaswami Jacques Rudell DAC DSP

Jeff Ou

Data

Thomas B. Cho, UC Berkeley

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Receiver Path (DECT)

Image BPF Desired Signal f 1.30 - 1.32G 1.6G 1.88 - 1.9G BPF LO 1 f LPF1 LO 1 LO 2 280M LPF2 1.728M 1.728M f LO 2 300M Single RC f

ADC
Thomas B. Cho, UC Berkeley 11

. .

Transmitter Path (DECT)

Power Amplier(PA) design is near completion. Transmitter architecture still in early research phase

Frequency Synthesizer To BPF & Antenna

Under Research

LPF

DAC

Data

Power Amplier
Thomas B. Cho, UC Berkeley 12

Whats different?
A Quasi-Direct Conversion Receiver

. .

No external IF BPF => Little or No IF Filtering => Selective ltering at Baseband Two Local Osc. freqs. LO1 : a xed freq. osc LO2 : a tuned osc to the desired channel => Elimination of carrier feedthrough compared to direct conversion arch. => Relaxed phase noise requirement on LO2 (tuned osc).

Thomas B. Cho, UC Berkeley

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. .

Design Challenges
System: - Data recovery in the presence of strong interferers and noise w/o ext. IF lters! - Image-Reject Mixer required - Low phase noise osc w/o ext. high-Q LC tank Circuit: - CMOS design - Power efcient circuit topologies - Low voltage design: 3.3V

Thomas B. Cho, UC Berkeley

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Design Considerations (I): System

LPF2 ~60dB! After ltering+gain f Desired Undesired f

Proper signal level control along the receiver signal path

IM3 component! Undesired Desired

Baseband channel select lter/gain design

Distortion performance: Intermodulation(IM3)

Thomas B. Cho, UC Berkeley 15

Noise performance: Power vs. noise

Design Considerations (II):Block

Low noise/pwr/disto. On-chip inductor Low noise/pwr/disto. Close I/Q path matching Carrier leakage I ADC Q Low phase noise/ spurious tones I/Q generation Frequency Synthesizer Low power Dynamic range DSP Blocking performance Linearity, Group-delay DC-offset

LPF Power efciency Power control

Thomas B. Cho, UC Berkeley 16

DAC

Data

Design Considerations (III): Others

. .

Substrate noise coupling - Noise isolation required

Substrate noise

@ LNA ~50 V @ ADC 3.3V!

Package modelling - Bond wire modelling for LNA & PAs I/O impedance matching
Die Package

Thomas B. Cho, UC Berkeley

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Key Building Blocks

. . . . . .

LNA

Jeff Ou Jacques Rudell Todd Weigandt, Srenik Mehta, Carol Barrett Thomas Cho, Francesco Brianti Thomas Cho, George Chien Sekhar Narayanaswami

Image-Reject Mixer : Freq. Synthesizer Baseband Filter /Gain A/D Convertert PA : : : :

Thomas B. Cho, UC Berkeley

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. . .

RF Low Noise Amplier

A single-stage differential-mode amplier On-chip spiral inductors for input impedance matching and output load tuning Critical Issues: Modelling of spiral inductors, Package modelling.. Noise Figure: 2.1 dB
-Vout+ Bias Bias

Gain: 20dB @1.9GHz IP3: -2 dBm (input)

+Vin-

Power: 20mW @3V Tech: 0.6 m CMOS

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assume ( Rs=50 )
Thomas B. Cho, UC Berkeley

Image-Reject Mixer
Image Desired I-I LO 1 f LO1I
LO2I

I-Q

LO2Q

LNA Q-I LO1Q

LO2I

Desired Q-Q

LO2Q

Image

Extra 35dB of image rejection required due to insufcient image rejection from RF BPF
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Thomas B. Cho, UC Berkeley

. . .

Image Reject Mixer Cell

Gilbert Cell Based Topology. Variable Gain via Vro. Cascode stage to isolate input stage from the Local Osc. IP3 : 10dBm.
Vout Vro LO Vbias

Common Mode Feedback

Variable Gain : 10dB ~ 35dB Image-Rejection: ~35dB Total Power : 40mW

Vrf

Thomas B. Cho, UC Berkeley

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Freq. Synthesizer(I): Phase Noise Req.

Signal Strength
-73 -33 dBm (for DECT) -39 -58

On top of desired channel! => Degrades SNR! Vout

Desired channel

f
Signal Vout

Sx (f)
Local Osc. Output -97 dBc

LO2 Desired channel

Phase Noise Spurious Tone

fL02 fch
Thomas B. Cho, UC Berkeley

Phase noise req. for DECT : - 97dBc@ fch -115dBc@ 2fch fch= 1.728MHz

f
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Freq. Synthesizer(II): for DECT

Crystal 62.208 MHz Reference Phase Detector Loop Filter 26 Ring Osc. VCO

I Q
LO1: Fixed Frequency 1617.498 MHz

9
Phase Detector Loop Filter

Ring Osc. VCO

I Q

N N = 153 ... 162

LO2: Variable Frequency 264.384 - 279.936 MHz

DECT Channel Spacing = 1.728 MHz

Thomas B. Cho, UC Berkeley 23

Freq. Synthesizer(III): for Multistandard

Channel Spacing : DECT Other Standards (FDMA) 1.728 MHz 10 KHz, 30 KHz, 200 KHz

VCO

fref

P.D.

L.F.

fo= fref (N + m )! 64
Freq. Control Tap Select

64-TAP PHASE-INTERPOLATOR

PHASE INTERPOLATED FREQ. SYNTHESIZER for ner channel spacings while maintaining high ref. freq. and high PLL bandwidth.
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Thomas B. Cho, UC Berkeley

Baseband Filter/Gain Stage

Mixer output

+
DC offset

ADC

Anti-aliasing Filter:

Channel Selection Filter:

Sallen-Key continuous-time LPF - Out-of-DECT-Band signal rejection - BW= ~2MHz - ~ 4-5th order - DC offset correction

Switched capacitor sampled-data LPF + Gain - Adjacent channel rejection - constant group delay - BW = ~ fdata/2 - 6th order(fs=18x) + 3rd order Phase eq.

Thomas B. Cho, UC Berkeley

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A/D Converter A 10-bit 20MS/s 35mW Pipeline ADC*

The Next Generation of 10 bit 20MS/s CMOS ADC Tech Vdd Active Area Power
*:T. Cho & P. Gray @CICC 94, San Diego
Thomas B. Cho, UC Berkeley 26

1.2m 3.3V 3.2x3.3 mm2 35mW @ 20MS/s

0.6 or 0.8 m 3.3V ~1.5x1.5 mm2 ~10mW @ 20MS/s

. . .
Vin+

RF Power Amplier
A two-stage differential-mode amplier On-chip spiral inductors for tuning out gate capacitance and output impedance matching Require power control
VDD
RF Choke

Off-Chip
Antenna modeled as 50 load

Output Power: 250mW@1.9GHz Efciency: > 30% Tech: 0.6 m CMOS

M1 M2

VinM5

50
Bias

M6

CMFB

M3

M4

GND
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Thomas B. Cho, UC Berkeley

Future Plan

. . .

Tape out 1st version : Spring, 1995 - Individual blocks - The whole receiver channel Testing/Evaluation : Summer, 1995

Tape out 2nd version : Winter, 1995 - Both receiver/transmitter channels

Thomas B. Cho, UC Berkeley

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