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By Jon Mark Hancock, Senior Applications Engineer, Infineon Technologies NA, San Jose, Calif. A high-performance controller integrates protection functions using failure mode error analysis combined with the predictable switching behavior of superjunction MOSFETs and SiC Schottky diodes.
ne component in the quest for improved energy efficiency and power quality is the use of active harmonic filter power factor correction (PFC) in switched-mode power supplies (SMPSs) for computing and industrial applications. Active PFC offers several well-known benefits, including automatic line-voltage adjustment, marked improvement of ac mains power quality in medium- and high-power applications, and stabilization of the SMPS bulk bus voltage. These features, in turn, improve cost factors and the holdup time of the isolated PWM converter. Though the basic implementation of active PFC with a boost converter is topologically quite simple, the devil is in the details. One challenge is managing surge current at startup and during brownouts due to cycle skip. Its also difficult to achieve high efficiency and compact size simultaneously at higher power levels where continuous current mode (CCM) operation is preferred for the boost inductor because of the lower EMI and switch/diode stress associated with CCM. To demonstrate how these various requirements may be met, a design example for a 650-W power supply will be presented using a new high-integration PFC controller for continuous conduction mode PFC. This controller will be combined with a very low switching loss superjunction MOSFET and a SiC Schottky diode in hard switching. The basis of this design, the ICE1PCS01 controller, is the first CCM PFC with enhanced protection and management features integrated into compact 8-pin DIP or SOIC. This controller replaces other larger package types usually used for this application with no loss in functionality. The integration level of the ICE1PCS01 and the simplification of the PFC implementation are reflected in a simplified design process aided by an available XL design tool. While the PFC boost converter is a simple topology in principle, the inherently wide range of operating input voltage (85 Vac to 265 Vac in this example) requires evaluation in the design process. In particular, the wide input range relates to stress factors such as brownout and cycle skip recovery, when switch and diode current max out. Simple calculations can be used to establish the basic operating conditions and component values. Using a calculation program like MathCAD makes it feasible to estimate the operating waveforms and losses based on the waveforms expected over the complete ac operating cycle. This analysis makes possible a more complete design synthesis in the first pass before building and testing hardware. With this approach, well explore two variants on a 650-W PFC design. One version uses a 250-kHz clock to achieve component size reduction, while the other trades size for other benefits with a more typical 100-kHz version. Requirements for the proposed design are listed in the table. About 10% extra power is budgeted to compensate for the efficiency loss of the PWM stage following the PFC Name
Input voltage range Nominal output voltage Rated output power to PWM Target efficiency Minimum bus operating voltage Inductor ripple current Operating pulse frequency Minimum holdup time Line dropout voltage (effective min low line)
Symbol
VINmin - VINmax Vout Pout h VBUSmin IRipple fS THoldup VIN_rms
Value
90 Vac to 265 Vac 400 V 650 W 92% + 300 V 20% to 30% IPk 250 kHz 20 msec 75 Vac
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RUNNING HEAD
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(3) The boost inductor is sized based on the ripple currentto-line current ratio, which has a typical range of 20% to 30%. The inductance value depends on the chosen switching frequency and the tolerable current ripple. Space limitations preclude a detailed discussion of the tradeoff, but lets examine two possibilities: One will be at 100-kHz reflecting typical industry practice with standard semiconductor components, and the other will be at 250 kHz, which is easily achieved with superjunction MOSFETs and silicon carbide Schottky rectifiers. The worst-case ripple current will be determined by the duty cycle of the switch at the peak voltage of low line and the clock frequency used. This wont be the point of highest duty cycle in the switch, but it will reflect the highest current and current ripple in the inductor. Considering the basic input-to-output duty cycle (D) transfer function of the boost converter: (4) Then, calculate the duty cycle at the peak of the waveform (substituting root of 2, times the ac value) in the equation: (5)
Power Electronics Technology October 2004
Bulk Capacitor
The bulk capacitor selection process is driven primarily by the required ripple current capability, hold-up time requirements and operating voltage. For a nominal bulk bus of 400 V, a 450-V capacitor should provide adequate margin considering the overvoltage protection (OVP) response characteristics of the ICE1PCS01.[2] Holdup time is dependent on the range of bulk bus operation for the PWM isolation converter. The wider the range over which the converter can operate, the smaller the bulk capacitor possible. However, at the same time, this widening of input voltage range compromises the efficiency and transformer utilization of the output converter. A typical compromise might be an operating range extending down to 300 V. Then, the necessary value can be calculated:
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Fig. 1. Boost switch and boost diode duty cycle for 75 Vac in, 400 V out.
Fig. 2. Average and min/max inductor current. Fig. 3. Average input current and switch/diode average current.
(8) The bulk capacitor was realized in the demonstration design using two 180-F caps. This parallel combination of two capacitors provides a higher total ripple current rating and better cooling (from increased surface area) than would a single capacitor.
Next, taking a data point at one quarter of the ac period interval should yield the peak input current: Iin_max = 13.93 A (12)
This agrees with the value calculated in equation (1). Using the same range variables, the duty cycle for the switch and diode can be calculated and plotted (see Fig. 1) over one ac mains period:
(13) Next, the ripple current I as a function of input voltage and operating duty cycle is calculated for the on time (switch) and off time (diode): (14)
(10) Using the previously calculated values for RMS input current, a waveform for the PFC input current is calculated: (11)
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0 ms
IS (tmain ) dtmain
2
The turn-off calculation is a complex function of current amplitude, RG and device type, which isnt shown in detail here for space limitations:
Waveforms of maximum and minimum switch current peak current are used to determine the switching losses:
(23)
PS _ off _ avg :=
1 NS
(18)
Then the switch conduction losses can be calculated, considering the RON, conduction time and current:
2 iS_min (tmain ) 1 PS _ cond (tmain ) := +iS _ max (tmain ) i S_min (tmain ) 3 2 +iS_max (tmain )
(24) In comparison, at 100 kHz the turn-on losses are estimated at 1.3 W and turn-off at 3 W. This amounts to a difference of ~7 W, partially offset by lower inductor losses by 3 W. Combining conduction and switching power losses in the boost switch (see Fig. 4):
Tmain
(25)
PS _ cond _ avg :=
1 Tmain
Tmain
0ms
Using data that is also incorporated in the data sheets regarding switching loss behavior for turn-on (Eon) and turn-off (Eoff), and switching behavior as a function of gate resistance and load current, functions have been defined in MathCAD, which calculate the turn-on and turn-off losses in joules per switching event (space limitations preclude including full details here). These switching event losses are multiplied based on the SMPS switching frequency to calculate the total loss. Switching loss behavior in superjunction MOSFETs such as CoolMOS is often much lower than for conventional vertical DMOS transistors because of the effect of the nonlinear output capacitance, which acts as a nonlinear snubber capacitor, reducing turn-off losses over those expected.[3]
PS _ on (tmain ) :=
ND NSiC _ test
(21)
PS _ on _ avg :=
1 Tmain
Tmain
0ms
PS _ on (tmain )dtmain
(22)
PS _ on _ avg = 3.251W
Power Electronics Technology October 2004
1 ND
(26)
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(32) In comparison, at 100 kHz, the estimated turn-off losses are 0.42 W, not a significant difference. Then the total power losses in the boost diode are the sum of conduction and switching loss: PD: = PD_cond_avg + PD_off PD = 6.897W
(27)
Heatsink Calculations
(28) Next, minimum and maximum diode currents can be calculated over one mains period: Heatsink calculations for the boost switch and diode must account for the thermal interface material between the transistor and diode package and the heatsink. This varies by type, but for popular TO-220 materials its in the range of 1.5 K/W, and for the TO-247 package, the greater area yields about 1 K/W. If one uses a maximum ambient of 50C and a maximum junction temperature target of 130C, for conservative derating practice, the heatsink to ambient impedance follows:
At this thermal impedance, forced air flow will make a substantial size reduction possible for the heatsink. With different requirements for junction temperature or ambient, the parameters can be modified accordingly. The diode heatsink requirements can be calculated similarly:
(30) (34) From integration of the results of this function the averaged loss over the mains period is calculated:
(31)
In the case of conventional ultrafast silicon diodes, calculating the switching losses is quite complex, if possible at all, due to the several nonlinear effects on Qrr behavior. These effects include rising effective Qrr with rising di/dt and rising temperature. For SiC Schottky diodes, the matter is greatly simplified, as there is no Qrr per se, only a displacement charge exists due to the depletion capacitance, for which loss is easily estimated per switching cycle.[4, 5, 6] For the proposed 6-A SiC Schottky rectifier:
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D6 IN4746
D7 IN4746 Shutdown
RLY1 G2RL-DC12 CY1 SIOV1 TB2 L2 SMV-10 F1 T5A L3 CX1 u68 CMV-60 4n7 CX2 u68 CY2 4n7 BR1 GBJ2506 D8 6A6-T L4 110uH
R11 201K C22 + 180uF +C18 R12 201K 180uF R17 5K11 +VO TB3
SPW35N60C3 Q2 C17 1u5 R5 R15 R25 6R8 12K OR1 R18 OR1 R19
GND-Vo
R20 220R IC1 ICE1PCS01 V+12 7 VCC C1 C21 2 Gate H 6 5 R23 10K C20 1u0
OR1
650W CCM-PFC
Shutdown 2N3904 Q1 C11 u22 R2 1K R1 1K
ICOMP
3
ISENSE FREQ
8
GATE GND
VSENSE
VCOMP
1 R24 22K6
areas, including loop transient response, THD for input current and the net power factor.[7] The maximum average input current, Iin_max, was previously calculated in equation 12. However, for the current-sense resistor calculation the effect of inductor ripple current, as shown in Fig. 2, must be used. Considering the soft limiting threshold of 700 mV for the current sense input to determine the maximum output power, the current sense resistor value is found from: IS _ peak = 15.321A RCS : + = 0.7V IS _ peak (35)
this resistor can be generated at initial charge of the bulk capacitor, its required to include a series resistor of ~200 on the current sense pin to prevent damage from excess voltage to the ISENSE input. The current loop is controlled by a transconductance amplifier OTA2, which has two inputs: a signal from the nonlinear gain block and a signal from the current-sense pin. The main variable from a design viewpoint is the switching frequency of the converter. Due to the influence of the nonlinear gain block, it is necessary to add an additional capacitance in the range of 0.5 nF to the calculated value:
GOTA 2 := 1.1 10 fSW := 250 10 C10 := GOTA 2 2 p fSW
3 3
RCS = 0.046 The current sense resistor should be a low-inductance type. Paralleled high-current surface-mount devices (SMDs) work better in this application than axial-leaded resistors because of the much lower inductance of the SMDs. In the design shown, SMD resistors were paralleled with a slightly lower resistance than the calculated value, as this is offset by the PCB trace resistance. Because a high surge current and voltage drop across
Power Electronics Technology October 2004
+ 0.5 10
C10 = 1.2 10
(36)
Output voltage setting (feedback loop) is determined by the internal VREF and R17 and R11+R12 externally; targeting 400 V, and assuming a value of 5.11 kO for the shunt resistor R17, 32
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(39) and the phase in degrees of this function calculated from this equation in MathCAD:
K1phase :=
i
180
The amplitude and phase transfer function are shown in Fig. 6, which shows a nominal loop bandwidth of ~6 Hz and ~20 phase margin.
RSeries :=
IC Protection Functionality
R17
(37)
RSeries = 403690
RSeries is split into two resistors R11 and R12 for reason of power handling and voltage withstanding; two 201K 1% resistors are suggested. This yields a calculated output of
VOUTnom :=
VREF
(38)
VOUTnom = 398.346V
The feedback signal from the output voltage divider is fed to OTA1 at pin 6 (VSENSE). OTA1 is a transconductance amplifier and charges the compensation network at VCOMP pin 5, consisting of R23, C11 and C20. Note that this current charge rate into the compensation network also determines the soft-start time. The output voltage at the bulk bus capacitors C18 and C22 contains a ripple voltage at double the frequency of
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The key to operational robustness, in addition to sizing the active and passive components correctly, is the protection and startup control functions of the controller. These functions have been designed according to failure mode error analysis (FMEA) and are managed by the inputs from just a few pins. Specifically, those pins are VSENSE, ISENSE and VCC, with VCOMP used to set loop compensation and manage soft-start-related protection functions. (For a basic state diagram, see Application Note AN-PFC-ICE1PCS01-1, available at www.infineon.com.) There are several off-state modes related both to safe startup conditions and protective shutdown. These include: q OFFbefore VCC reaches 11 V or when VCC drops below 10 V (UVLO) q OFFif VSENSE is below 0.8 V , due to external pull down (standby mode), VIN does not reach VIN(MIN) (undervoltage protection or UVP), or open loop protection (OLP), loss of feedback connection q OFFif VOUT drops below 50% of rated voltage (brownout protection or BOP) with ISENSE ~0.7 V q OFFwhen peak current limit is exceeded (peak 33
Power Electronics Technology October 2004
Fig. 7. Measured efficiency over line-voltage range for 600-W output running at 250 kHz.
1. flowPHASE 0
Switch the power I high power half bridge I NTC I 1200V: 100A, 150A
Tyco Electronics, Power Systems Rupert - Mayer - Str. 44 81359 Munich, Germany Tel.: +49 (0)89 722 - 28457 Fax: +49 (0)89 722 - 32936 www.em.tycoelectronics.com power.switches@tycoelectronics.com
Tyco Electronics, Power Systems is one of the market leaders in the field of Solid State Relays and Power Modules for applications such as motor drives, power supplies, welding machines, and soft starters. The product portfolio includes standard IGBT PIMs, Six Packs, H-Bridges and PFC solutions covering a range from 5A - 100A/600V and from 5A - 150A/1200V in more than six different housings.
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References
1. Magnetics Inc., Inductor Design in Switching Regulators, Technical Bulletin SR-1A. 2. Infineon Technologies, ICEPCS01Standalone Power Factor Correction Controller in Continuous Conduction Mode, Datasheet May 2003. 3. Wei Dong, Bing Lu, Qun Zhao and Fred C. Lee, Performance Evaluation of CoolMOS TM and SiC Diode for PFC Applications, APEC 2004. 4. R. Rupp, M. Treu, A. Mauder, E. Griebl, W. Werner, W. Bartsch, D. Stephani, Performance and Reliability Issues of
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