A New Cascaded Multilevel Inverter with Reduced Number of Switches

Abstract
This paper proposes a new topology for cascaded multilevel inverters. This structure consists of series connection of proposed basic unit blocks which are built with both unidirectional and bidirectional switches. The proposed structure has some advantages including: reduction in the number of switches and driver circuits, cost and installation area. Three algorithms for determination of dc voltage sources' magnitudes have also been proposed. The algorithms can produce all odd and even levels at the output voltage. The proposed structure also has fewer dc voltage sources variety and less maximum blocking voltage of switches compared to conventional inverters. The capability of proposed structure in producing all odd and even output voltage levels is proved by simulation result for a 21-level inverter.

1. INTRODUCTION
Nowadays, multilevel inverters have become more attractive for their use in high-voltage and high-power applications. In multilevel inverters, the desired output voltage is achieved by suitable combination of multiple low dc voltage sources used at the input side. As the number of dc sources is increased, the output voltage becomes closer to a pure sinusoidal waveform. The required dc voltage can be chosen from different sources such as batteries, photovoltaic, fuel cells, capacitors, the rectified output voltage of wind turbines, and other similar dc voltage sources [1-3]. Some advantages of multilevel inverters are good power quality, low switching losses and electromagnetic compatibility due to the low dv/dt transitions [4]. Some of the fundamental multilevel topologies include the cascaded H-bridge structures [5], flying capacitor [6], and diode-clamped converter [7]. Other proposed configurations for multilevel converters are mainly derived from these three basic topologies [2], [4], [8-9]. Among these three topologies, cascaded multilevel converter has got more attention in literatures [1011]. This paper particularly focuses on Cascaded multilevel converters. This topology is divided into two symmetrical and asymmetrical structures. If all dc voltage sources are equal, the inverter is then known as symmetrical multilevel inverter, otherwise it is known as asymmetrical multilevel inverter. In asymmetrical multilevel inverters, the number of produced output voltage levels is high when compared to symmetrical multilevel inverter with the same number of dc voltage sources and switches [12]. One of the main challenges in multilevel inverters is to reduce the number of power electronic switches while considering operational conditions. Although low voltage rate switches can be utilized in a multilevel inverter, each switch requires related deriver circuits. This may cause the overall circuit to be more expensive and complex. So in practical implementation reducing the number of switches and gate deriver circuits are very important. In recent years, many configurations are presented in order to reduce the number of overall switches used in cascaded multilevel inverters. Some of these structures are in references [4] and [13]. The presented structures aim in reducing the number of switches while having the availability to produce all odd and even levels at the output voltage. The structures presented in these literatures have significant reduction in the number of switches and consequently reduction in installation area. However in the structures of [8] and [13], the implemented switches are

bidirectional (consisting of two IGBTs and two anti-parallel diodes). So the total number of IGBTs is high which increases cost. Nevertheless, because of using one deriver circuit for each switch, the overall numbers of deriver circuits needed for the recommended topologies are fewer compared to conventional multilevel inverter. This paper proposes a new topology for cascaded multilevel inverters which uses a combination of bidirectional and unidirectional switches. It should be considered that by suitable combination of bidirectional and unidirectional switches, fewer deriver circuits and IGBTs can be achieved. Moreover, to produce all odd and even levels at the output voltage, three procedures for determination of dc voltage sources' magnitudes have also been proposed. The capability of proposed structure in producing all odd and even output voltage levels is proved by simulation result for a 21-level inverter.

MULTILEVEL INVERTER
An inverter is an electrical device that converts direct current (DC) to alternating current (AC); the converted AC can be at any required voltage and frequency with the use of appropriate transformers, switching, and control circuits. Static inverters have no moving parts and are used in a wide range of applications, from small switching power supplies in computers, to large electric utility high-voltage direct current applications that transport bulk power. Inverters are commonly used to supply AC power from DC sources such as solar panels or batteries. The electrical inverter is a high-power electronic oscillator. It is so named because early mechanical AC to DC converters were made to work in reverse, and thus were "inverted", to convert DC to AC. The inverter performs the opposite function of a rectifier

Cascaded H-Bridges inverter A single-phase structure of an m-level cascaded inverter is illustrated in Figure 31.1. Each separate dc source (SDCS) is connected to a single-phase full-bridge, or H-bridge, inverter. Each inverter level can generate three different voltage outputs, +Vdc, 0, and Vdc by connecting the dc source to the ac output by different combinations of the four switches, S1, S2, S3, and S4. To obtain +Vdc, switches S1 and S4 are turned on, whereas Vdc can be obtained by turning on switches S2 and S3. By turning on S1 and S2 or S3 and S4, the output voltage is 0. The ac outputs of each of the different full-bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. The number of output phase voltage levels m in a cascade inverter is defined by m = 2s+1, where s is the number of separate dc sources. An example phase voltage waveform for an 11-level cascaded H-bridge inverter with 5 SDCSs and 5 full bridges is shown in Figure 31.2. The phase voltage van = va1 + va2 + va3 + va4 + va5. For a stepped waveform such as the one depicted in Figure 31.2 with s steps, the Fourier Transform for this waveform follows

Single-phase structure of a multilevel cascaded H-bridges inverter

Output phase voltage waveform of an 11-level cascade inverter with 5 separate dc sources.

The magnitudes of the Fourier coefficients when normalized with respect to Vdc are as follows:

The conducting angles, 1, 2, ..., s, can be chosen such that the voltage total harmonic distortion is a minimum. Generally, these angles are chosen so that predominant lower frequency harmonics, 5th, 7th, 11th, and 13th, harmonics are eliminated [25]. More detail on harmonic elimination techniques will be presented in the next section. Multilevel cascaded inverters have been proposed for such applications as static var generation, an interface with renewable energy sources, and for battery-based applications. Three-phase cascaded inverters can be connected in wye, as shown in Figure 31.3, or in delta. Peng has demonstrated a prototype multilevel cascaded static var generator connected in parallel

with the electrical system that could supply or draw reactive current from an electrical system [20-23]. The inverter could be controlled to either regulate the power factor of the current drawn from the source or the bus voltage of the electrical system where the inverter was connected. Peng [20] and Joos [24] have also shown that a cascade inverter can be directly connected in series with the electrical system for static var compensation. Cascaded inverters are ideal for connecting renewable energy sources with an ac grid, because of the need for separate dc sources, which is the case in applications such as photovoltaics or fuel cells. Cascaded inverters have also been proposed for use as the main traction drive in electric vehicles, where several batteries or ultracapacitors are well suited to serve as SDCSs [19, 26]. The cascaded inverter could also serve as a rectifier/charger for the batteries of an electric vehicle while the vehicle was connected to an ac supply as shown in Figure 31.3. Additionally, the cascade inverter can act as a rectifier in a vehicle that uses regenerative braking.

Three-phase wye-connection structure for electric vehicle motor drive and battery charging.

The main advantages and disadvantages of multilevel cascaded H-bridge converters are as follows Advantages: The number of possible output voltage levels is more than twice the number of dc sources (m = 2s + 1). The series of H-bridges makes for modularized layout and packaging. This will enable the manufacturing process to be done more quickly and cheaply.

Disadvantages: Separate dc sources are required for each of the H-bridges. This will limit its application to products that already have multiple SDCSs readily available.

Diode-Clamped Multilevel Inverter The neutral point converter proposed by Nabae, Takahashi, and Akagi in 1981 was essentially a three-level diode-clamped inverter [5]. In the 1990s several researchers published articles that have reported experimental results for four-, five-, and six-level diode-clamped converters for such uses as static var compensation, variable speed motor drives, and highvoltage system interconnections [18-31]. A three-phase six-level diode-clamped inverter is shown in Figure 31.5. Each of the three phases of the inverter shares a common dc bus, which has been subdivided by five capacitors into six levels. The voltage across each capacitor is V dc, and the voltage stress across each switching device is limited to V dc through the clamping diodes. Table 31.1 lists the output voltage levels possible for one phase of the inverter with the negative dc rail voltage V0 as a reference. State condition 1 means the switch is on, and 0 means the switch is off. Each phase has five complementary switch pairs such that turning on one of the switches of the pair requires that the other complementary switch be turned off. The complementary switch pairs for phase leg a are (Sa1, Sa1), (Sa2, Sa2), (Sa3, Sa3), (Sa4, Sa4), and (Sa5, Sa5). Table 31.1 also shows that in a diode-clamped inverter, the switches that are on for a

particular phase leg are always adjacent and in series. For a six-level inverter, a set of five switches is on at any given time.

Three-phase six-level structure of a diode-clamped inverter.

Diode-clamped six-level inverter voltage levels and corresponding switch states.

Advantages: All of the phases share a common dc bus, which minimizes the capacitance requirements of theconverter. For this reason, a back-to-back topology is not only possible but also practical for uses such as a high-voltage back-to-back inter-connection or an adjustable speed drive. The capacitors can be pre-charged as a group. Efficiency is high for fundamental frequency switching.

Disadvantages: Real power flow is difficult for a single inverter because the intermediate dc levels will tend to overcharge or discharge without precise monitoring and control. The number of clamping diodes required is quadratically related to the number of levels, which can be cumbersome for units with a high number of levels.

Flying Capacitor Multilevel Inverter Meynard and Foch introduced a flying-capacitor-based inverter in 1992 [32]. The structure of this inverter is similar to that of the diode-clamped inverter except that instead of using clamping diodes, the inverter uses capacitors in their place. The circuit topology of the flying capacitor

multilevel inverter is shown in Figure 31.7. This topology has a ladder structure of dc side capacitors, where the voltage on each capacitor differs from that of the next capacitor. The voltage increment between two adjacent capacitor legs gives the size of the voltage steps in the output waveform.

Three-phase six-level structure of a flying capacitor inverter.

One advantage of the flying-capacitor-based inverter is that it has redundancies for inner voltage levels; in other words, two or more valid switch combinations can synthesize an output voltage. Table 31.2 shows a list of all the combinations of phase voltage levels that are possible for the six-level circuit shown in Figure 31.7. Unlike the diode-clamped inverter, the flying-

capacitor inverter does not require all of the switches that are on (conducting) be in a consecutive series. Moreover, the flying-capacitor inverter has phase redundancies, whereas the diodeclamped inverter has only line-line redundancies [2, 3, 33]. These redundancies allow a choice of charging/discharging specific capacitors and can be incorporated in the control system for balancing the voltages across the various levels. In addition to the (m-1) dc link capacitors, the m-level flying-capacitor multilevel inverter will require (m-1) (m-2)/2 auxiliary capacitors per phase if the voltage rating of the capacitors is identical to that of the main switches. One application proposed in the literature for the multilevel flying capacitor is static var generation [2, 3]. The main advantages and disadvantages of multilevel flying capacitor converters are as follows [2, 3].

Advantages: Phase redundancies are available for balancing the voltage levels of the capacitors. Real and reactive power flow can be controlled. The large number of capacitors enables the inverter to ride through short duration outages and deep voltage sags.

Disadvantages: Control is complicated to track the voltage levels for all of the capacitors. Also, precharging all of the capacitors to the same voltage level and startup are complex. Switching utilization and efficiency are poor for real power transmission. The large numbers of capacitors are both more expensive and bulky than clamping diodes in multilevel diode-clamped converters. Packaging is also more difficult in inverters with a high number of levels.

Flying-capacitor six-level inverter redundant voltage levels and corresponding switch states

Other Multilevel Inverter Structures

Besides the three basic multilevel inverter topologies previously discussed, other multilevel converter topologies have been proposed; however, most of these are hybrid circuits that are combinations of two of the basic multilevel topologies or slight variations to them. Additionally, the combination of multilevel power converters can be designed to match with a specific application based on the basic topologies. In the interest of completeness, some of these will be identified and briefly described. A. Generalized Multilevel Topology Existing multilevel converters such as diode-clamped and capacitor-clamped multilevel converters can be derived from the generalized converter topology called P2 topology proposed by Peng [34] as illustrated in Figure 31.8. The generalized multilevel converter topology can balance each voltage level by itself regardless of load characteristics, active or reactive power conversion and without any assistance from other circuits at any number of levels automatically. Thus, the topology provides a complete multilevel topology that embraces the existing multilevel converters in principle. Figure 31.8 shows the P2 multilevel converter structure per phase leg. Each switching device, diode, or capacitors voltage is 1Vdc, for instance, 1/ (m-1) of the DC-link voltage. Any converter with any number of levels, including the conventional bi-level converter can be obtained using this generalized topology [1, 34].

Generalized P2 multilevel converter topology for one phase leg. B. Mixed-Level Hybrid Multilevel Converter To reduce the number of separate DC sources for high-voltage, high-power applications with multilevel converters, diode-clamped or capacitor-clamped converters could be used to replace the full-bridge cell in a cascaded converter [35]. An example is shown in Figure 31.9. The nine-level cascade converter incorporates a three-level diode-clamped converter as the cell. The original cascaded H-bridge multilevel converter requires four separate DC sources for one phase leg and twelve for a three-phase converter. If a five-level converter replaces the full-bridge cell, the voltage level is effectively doubled for each cell. Thus, to achieve the same nine voltage levels for each phase, only two separate DC sources are needed for one phase leg and six for a three-phase converter. The configuration has mixed-level hybrid multilevel units because it embeds multilevel cells as the building block of the cascade converter. The advantage of the topology is it needs less separate DC sources. The disadvantage for the topology is its control will be complicated due to its hybrid structure.

Mixed-level unit

hybrid

configuration using the three-level diode-clamped converter as the cascaded converter cell to increase the voltage levels.

Zero-voltage switching capacitor-clamped inverter circuit.

C. Soft-Switched Multilevel Converter Some soft-switching methods can be implemented for different multilevel converters to reduce the switching loss and to increase efficiency. For the cascaded converter, because each converter cell is a bi-level circuit, the implementation of soft switching is not at all different from that of conventional bi-level converters. For capacitor-clamped or diode-clamped converters, soft-switching circuits have been proposed with different circuit combinations. One of softswitching circuits is a zero-voltage-switching type which includes auxiliary resonant commutated pole (ARCP), coupled inductor with zero-voltage transition (ZVT), and their combinations [1, 36] as shown in Figure 31.10.

D. Back-to-Back Diode-Clamped Converter Two multilevel converters can be connected in a back-to-back arrangement and then the combination can be connected to the electrical system in a series-parallel arrangement as shown in Figure 31.11. Both the current demanded from the utility and the voltage delivered to the load can be controlled at the same time. This series-parallel active power filter has been referred to as a universal power conditioner [37-43] when used on electrical distribution systems and as a universal power flow controller [44-48] when applied at the transmission level. Previously, Lai and Peng [30] proposed the back-to-back diode-clamped topology shown in Figure 31.12 for use as a high-voltage dc inter connection between two asynchronous ac systems or as a rectifier/inverter for an adjustable speed drive for high-voltage motors. The diode-clamped inverter has been chosen over the other two basic multilevel circuit topologies for use in a universal power conditioner for the following reasons: All six phases (three on each inverter) can share a common dc link. Conversely, the cascade inverter requires that each dc level be separate, and this is not conducive to a back-to-back arrangement. The multilevel flying-capacitor converter also shares a common dc link; however, each phase leg requires several additional auxiliary capacitors. These extra capacitors would add substantially to the cost and the size of the conditioner.

Because a diode-clamped converter acting as a universal power conditioner will be expected to compensate for harmonics and/or operate in low amplitude modulation index regions, a more sophisticated, higher-frequency switch control than the fundamental frequency switching method will be needed. For this reason, multilevel space vector and carrier-based PWM approaches are compared in the next section, as well as novel carrier-based PWM methodologies. Multilevel Converter PWM Modulation Strategies Pulse width modulation (PWM) strategies used in a conventional inverter can be modified to use in multilevel converters. The advent of the multilevel converter PWM modulation methodologies can be classified according to switching frequency as illustrated in Figure 31.13. The three multilevel PWM methods most discussed in the literature have been multilevel carrier-based PWM, selective harmonic elimination, and multilevel space vector

PWM; all are extensions of traditional two-level PWM strategies to several levels. Other multilevel PWM methods have been used to a much lesser extent by researchers; therefore, only the three major techniques will be discussed in this chapter.

Series-parallel connection to electrical system of two back-to-back inverters.

Six-level diode-clamped back-to-back converter structure.

Classification of PWM multilevel converter modulation strategies

Multilevel converter design example Number of levels and voltage rating of active devices In a multilevel inverter, determining the number of levels will be one of the most important factors because this affects many of the other sizing factors and control techniques. Tradeoffs in specifying the number of levels that the power conditioner will need and the advantages and complexity of having multiple voltage levels available are the primary differences that set a multilevel filter apart from a single level filter.

As a starting point, known is the nominal RMS voltage rating, Vnom, of the electrical system to which the diode clamped power conditioner will be connected. The dc link voltage must be at least as high as the amplitude of the nominal line-neutral voltage at the point of connection, or2Vnom. The parallel inverter must be able to inject currents by imposing a voltage across the parallel inductors, LPI, that is the difference between the load voltage VL and parallel inverter output voltage VPI. The most difficult time to impose a voltage across the inductors is when the load voltage waveform is at its maximum or minimum. Simulation results have shown that the amplitude of the desired load voltage Vnom should not be more than 70 percent of the overall dc link voltage for the parallel inverter to have sufficient margin to inject appropriate compensation currents. Without this margin, complete compensation of reactive currents may not be possible. This margin can be incorporated into a design factor for the inverter. Because the dc link voltage and the voltage at the connection point can both vary, the design factor used in the rating selection process incorporates these elements as well as the small voltage drops that occur in the inverters during active device conduction. The product of the number of the active devices in series (m-1) and the voltage rating of the devices Vdev must then be such that

The minimum number of levels and the voltage rating of the active devices (IGBTs, GTOs, power MOSFETs, etc.) are inversely related to each other. More levels in the inverter will lower the required voltage device rating of individual devices; or looking at it another way, a higher voltage rating of the devices will enable a fewer minimum number of levels to be used.

Electrical system connection of multilevel diode-clamped power conditioner.

Increasing the number of levels does not affect the total voltage blocking capability of the active devices in each phase leg because lower device ratings can be used. Some of the benefits of using more than the minimum required number of levels in a diode clamped inverter are as follows: 1. Voltage stress across each device is lower. Both active devices and dc link capacitors could be used that have lower voltage ratings (which sometimes are much cheaper and have greater availability). 2. The inverter will have a lower EMI because the dV/dt during each switching will be lower. 3. The output of the waveform will have more steps, or degrees of freedom, which enables the output waveform to more closely track a reference waveform. 4. Lower individual device switching frequency will achieve the same results as an inverter with a fewer number of levels and higher device switching frequency. Or the switching frequency can be kept the same as that in an inverter with a fewer number of levels to achieve a better waveform.

The drawbacks of using more than the required minimum number of levels are as follows:

1. Six active device control signals (one for each phase of the parallel inverter and the series inverter) are needed for each hardware level of the inverter i.e., 6(m-1) control signals. Additional levels require more computational resources and add complexity to the control. 2. If the blocking diodes used in the inverter have the same rating as the active devices, their number increases dramatically because 6(m-2)(m-1) diodes would be required for the back-toback structure.

Considering the trade-offs between the number of levels and the voltage rating of the devices will generally lead the designer to choose an appropriate value for each.

Fault diagnosis in multilevel converters Since a multilevel converter is normally used in medium to high power applications, the reliability of the multilevel converter system is very important. For instance industrial drive applications in manufacturing plants are dependent upon induction motors and their inverter systems for process control. Generally, the conventional protection systems are passive devices such as fuses, overload relays, and circuit breakers to protect the inverter systems and the induction motors. The protection devices will disconnect the power sources from the multilevel inverter system whenever a fault occurs, stopping the operated process. Downtime of manufacturing equipment can add up to be thousands or hundreds of thousands of dollars per hour, therefore fault detection and diagnosis is vital to a companys bottom line. In order to maintain continuous operation for a multilevel inverter system, knowledge of fault behaviors, fault prediction, and fault diagnosis are necessary. Faults should be detected as soon as possible after they occur, because if a motor drive runs continuously under abnormal conditions, the drive or motor may quickly fail. The possible structure for a fault diagnosis system is illustrated in Figure 31.33. The system is composed of four major states: feature extraction, neural network classification, fault diagnosis, and switching pattern calculation with gate signal output. The feature extraction performs the voltage input signal transformation, with rated signal values as important features, and the output of the transformed signal is transferred to the neural network classification. The networks are trained with both normal and abnormal data for the MLID; thus, the output of this network is nearly 0 and 1 as binary code. The binary code is sent to the fault diagnosis to decode the fault type and its location. Then, the switching pattern is calculated to reconfigure the multilevel inverter. Switching patterns and the modulation index of other active switches can be adjusted to maintain voltage and current in a balanced condition after reconfiguration recovers from a fault. The MLID can continuously operate in a balanced condition; of course, the MLID will not be able to operate at its rated power. Therefore, the MLID can operate in balanced condition at reduced power after the fault occurs until the operator locates and replaces the damaged switch

Structure of fault diagnosis system of a multilevel cascaded H-bridges inverter. Applications: DC power source utilization

Inverter designed to provide 115 VAC from the 12 VDC source provided in an automobile. The unit shown provides up to 1.2 amperes of alternating current, or enough to power two sixty watt light bulbs. An inverter converts the DC electricity from sources such as batteries, solar panels, or fuel cells to AC electricity. The electricity can be at any required voltage; in particular it can operate AC equipment designed for mains operation, or rectified to produce DC at any desired voltage. Grid tie inverters can feed energy back into the distribution network because they produce alternating current with the same wave shape and frequency as supplied by the distribution system. They can also switch off automatically in the event of a blackout. Micro-inverters convert direct current from individual solar panels into alternating current for the electric grid.[1] Uninterruptible power supplies An uninterruptible power supply (UPS) uses batteries and an inverter to supply AC power when main power is not available. When main power is restored, a rectifier is used to supply DC power to recharge the batteries. Induction heating Inverters convert low frequency main AC power to a higher frequency for use in induction heating. To do this, AC power is first rectified to provide DC power. The inverter then changes the DC power to high frequency AC power. HVDC power transmission With HVDC power transmission, AC power is rectified and high voltage DC power is transmitted to another location. At the receiving location, an inverter in a static inverter plant converts the power back to AC.

Variable-frequency drives A variable-frequency drive controls the operating speed of an AC motor by controlling the frequency and voltage of the power supplied to the motor. An inverter provides the controlled power. In most cases, the variable-frequency drive includes a rectifier so that DC power for the inverter can be provided from main AC power. Since an inverter is the key component, variablefrequency drives are sometimes called inverter drives or just inverters. Electric vehicle drives Adjustable speed motor control inverters are currently used to power the traction motors in some electric and diesel-electric rail vehicles as well as some battery electric vehicles and hybrid electric highway vehicles such as the Toyota Prius. Various improvements in inverter technology are being developed specifically for electric vehicle applications.[2] In vehicles with regenerative braking, the inverter also takes power from the motor (now acting as a generator) and stores it in the batteries. Air conditioning An air conditioner bearing the inverter tag uses a variable-frequency drive to control the speed of the motor and thus the compressor. The general case A transformer allows AC power to be converted to any desired voltage, but at the same frequency. Inverters, plus rectifiers for DC, can be designed to convert from any voltage, AC or DC, to any other voltage, also AC or DC, at any desired frequency. The output power can never exceed the input power, but efficiencies can be high, with a small proportion of the power dissipated as waste heat.

PULSE WIDTH MODULATION What is PWM?

Pulse Width Modulation (PWM) is the most effective means to achieve constant voltage battery charging by switching the solar system controllers power devices. When in PWM regulation, the current from the solar array tapers according to the batterys condition and recharging needs Consider a waveform such as this: it is a voltage switching between 0v and 12v. It is fairly obvious that, since the voltage is at 12v for exactly as long as it is at 0v, then a 'suitable device' connected to its output will see the average voltage and think it is being fed 6v exactly half of 12v. So by varying the width of the positive pulse - we can vary the 'average' voltage.

Similarly, if the switches keep the voltage at 12 for 3 times as long as at 0v, the average will be 3/4 of 12v - or 9v, as shown below.

and if the output pulse of 12v lasts only 25% of the overall time, then the average is

By varying - or 'modulating' - the time that the output is at 12v (i.e. the width of the positive pulse) we can alter the average voltage. So we are doing 'pulse width modulation'. I said earlier that the output had to feed 'a suitable device'. A radio would not work from this: the radio would see 12v then 0v, and would probably not work properly. However a device such as a motor will respond to the average, so PWM is a natural for motor control. Pulse Width modulator So, how do we generate a PWM waveform? It's actually very easy, there are circuits available in the TEC site. First you generate a triangle waveform as shown in the diagram below. You compare this with a d.c voltage, which you adjust to control the ratio of on to off time that you require. When the triangle is above the 'demand' voltage, the output goes high. When the triangle is below the demand voltage, the

When the demand speed it in the middle (A) you get a 50:50 output, as in black. Half the time the output is high and half the time it is low. Fortunately, there is an IC (Integrated circuit)

called a comparator: these come usually 4 sections in a single package. One can be used as the oscillator to produce the triangular waveform and another to do the comparing, so a complete oscillator and modulator can be done with half an IC and maybe 7 other bits. The triangle waveform, which has approximately equal rise and fall slopes, is one of the commonest used, but you can use a saw tooth (where the voltage falls quickly and rinses slowly). You could use other waveforms and the exact linearity (how good the rise and fall are) is not too important. Traditional solenoid driver electronics rely on linear control, which is the application of a constant voltage across a resistance to produce an output current that is directly proportional to the voltage. Feedback can be used to achieve an output that matches exactly the control signal. However, this scheme dissipates a lot of power as heat, and it is therefore very inefficient. A more efficient technique employs pulse width modulation (PWM) to produce the constant current through the coil. A PWM signal is not constant. Rather, the signal is on for part of its period, and off for the rest. The duty cycle, D, refers to the percentage of the period for which the signal is on. The duty cycle can be anywhere from 0, the signal is always off, to 1, where the signal is constantly on. A 50% D results in a perfect square wave. (Figure 1)

A solenoid is a length of wire wound in a coil. Because of this configuration, the solenoid has, in addition to its resistance, R, a certain inductance, L. When a voltage, V, is applied across

an inductive element, the current, I, produced in that element does not jump up to its constant value, but gradually rises to its maximum over a period of time called the rise time (Figure 2). Conversely, I does not disappear instantaneously, even if V is removed abruptly, but decreases back to zero in the same amount of time as the rise time.

Therefore, when a low frequency PWM voltage is applied across a solenoid, the current through it will be increasing and decreasing as V turns on and off. If D is shorter than the rise time, I will never achieve its maximum value, and will be discontinuous since it will go back to zero during Vs off period (Figure 3).* In contrast, if D is larger than the rise time, I will never fall back to zero, so it will be continuous, and have a DC average value. The current will not be constant, however, but will have a ripple (Figure 4).

At high frequencies, V turns on and off very quickly, regardless of D, such that the current does not have time to decrease very far before the voltage is turned back on. The resulting current through the solenoid is therefore considered to be constant. By adjusting the D, the amount of output current can be controlled. With a small D, the current will not have much time to rise before the high frequency PWM voltage takes effect and the current stays constant. With a large D, the current will be able to rise higher before it becomes constant. (Figure 5)

Dither Static friction, stiction, and hysteresis can cause the control of a hydraulic valve to be erratic and unpredictable. Stiction can prevent the valve spool from moving with small input changes, and hysteresis can cause the shift to be different for the same input signal. In order to counteract the effects of stiction and hysteresis, small vibrations about the desired position are created in the spool. This constantly breaks the static friction ensuring that it will move even with small input changes, and the effects of hysteresis are average out. Dither is a small ripple in the solenoid current that causes the desired vibration and there by increases the linearity of the valve. The amplitude and frequency of the dither must be carefully chosen. The amplitude must be large enough and the frequency slow enough that the spool will respond, yet they must also be small and fast enough not to result in a pulsating output. The optimum dither must be chosen such that the problems of stiction and hysteresis are overcome without new problems being created. Dither in the output current is a byproduct of low frequency PWM, as seen above. However, the frequency and amplitude of the dither will be a function of the duty cycle, which is also used to set the output current level. This means that low frequency dither is not independent of current magnitude. The advantage of using high frequency PWM is that dither can be generated separately, and then superimposed on top of the output current.

This allows the user to independently set the current magnitude (by adjusting the D), as well as the dither frequency and amplitude. The optimum dither, as set by the user, will therefore be constant at all current levels. Why the PWM frequency is important: The PWM is a large amplitude digital signal that swings from one voltage extreme to the other. And, this wide voltage swing takes a lot of filtering to smooth out. When the PWM frequency is close to the frequency of the waveform that you are generating, then any PWM filter will also smooth out your generated waveform and drastically reduce its amplitude. So, a good rule of thumb is to keep the PWM frequency much higher than the frequency of any waveform you generate. Finally, filtering pulses is not just about the pulse frequency but about the duty cycle and how much energy is in the pulse. The same filter will do better on a low or high duty cycle pulse compared to a 50% duty cycle pulse. Because the wider pulse has more time to integrate to a stable filter voltage and the smaller pulse has less time to disturb it the inspiration was a request to control the speed of a large positive displacement fuel pump. The pump was sized to allow full power of a boosted engine in excess of 600 Hp. At idle or highway cruise, this same engine needs far less fuel yet the pump still normally supplies the same amount of fuel. As a result the fuel gets recycled back to the fuel tank, unnecessarily heating the fuel. This PWM controller circuit is intended to run the pump at a low speed setting during low power and allow full pump speed when needed at high engine power levels. Motor Speed Control (Power Control) Typically when most of us think about controlling the speed of a DC motor we think of varying the voltage to the motor. This is normally done with a variable resistor and provides a limited useful range of operation. The operational range is limited for most applications primarily because torque drops off faster than the voltage drops.

Most DC motors cannot effectively operate with a very low voltage. This method also causes overheating of the coils and eventual failure of the motor if operated too slowly. Of course, DC motors have had speed controllers based on varying voltage for years, but the range of low speed operation had to stay above the failure zone described above. Additionally, the controlling resistors are large and dissipate a large percentage of energy in the form of heat. With the advent of solid state electronics in the 1950s and 1960s and this technology becoming very affordable in the 1970s & 80s the use of pulse width modulation (PWM) became much more practical. The basic concept is to keep the voltage at the full value and simply vary the amount of time the voltage is applied to the motor windings. Most PWM circuits use large transistors to simply allow power On & Off, like a very fast switch. This sends a steady frequency of pulses into the motor windings. When full power is needed one pulse ends just as the next pulse begins, 100% modulation. At lower power settings the pulses are of shorter duration. When the pulse is On as long as it is Off, the motor is operating at 50% modulation. Several advantages of PWM are efficiency, wider operational range and longer lived motors. All of these advantages result from keeping the voltage at full scale resulting in current being limited to a safe limit for the windings. PWM allows a very linear response in motor torque even down to low PWM% without causing damage to the motor. Most motor manufacturers recommend PWM control rather than the older voltage control method. PWM controllers can be operated at a wide range of frequencies. In theory very high frequencies (greater than 20 kHz) will be less efficient than lower frequencies (as low as 100 Hz) because of switching losses. The large transistors used for this On/Off activity have resistance when flowing current, a loss that exists at any frequency. These transistors also have a loss every time they turn on and every time they turn off. So at very high frequencies, the turn on/off losses become much more significant. For our purposes the circuit as designed is running at 526 Hz. Somewhat of an arbitrary frequency, it works fine.

Depending on the motor used, there can be a hum from the motor at lower PWM%. If objectionable the frequency can be changed to a much higher frequency above our normal hearing level (>20,000Hz) . PWM Controller Features: This controller offers a basic Hi Speed and Low Speed setting and has the option to use a Progressive increase between Low and Hi speed. Low Speed is set with a trim pot inside the controller box. Normally when installing the controller, this speed will be set depending on the minimum speed/load needed for the motor. Normally the controller keeps the motor at this Lo Speed except when Progressive is used and when Hi Speed is commanded (see below). Low Speed can vary anywhere from 0% PWM to 100%. Progressive control is commanded by a 0-5 volt input signal. This starts to increase PWM % from the low speed setting as the 0-5 volt signal climbs. This signal can be generated from a throttle position sensor, a Mass Air Flow sensor, a Manifold Absolute Pressure sensor or any other way the user wants to create a 0-5 volt signal. This function could be set to increase fuel pump power as turbo boost starts to climb (MAP sensor). Or, if controlling a water injection pump, Low Speed could be set at zero PWM% and as the TPS signal climbs it could increase PWM%, effectively increasing water flow to the engine as engine load increases. This controller could even be used as a secondary injector driver (several injectors could be driven in a batch mode, hi impedance only), with Progressive control (0-100%) you could control their output for fuel or water with the 0-5 volt signal. Progressive control adds enormous flexibility to the use of this controller. Hi Speed is that same as hard wiring the motor to a steady 12 volt DC source. The controller is providing 100% PWM, steady 12 volt DC power. Hi Speed is selected three different ways on this controller: 1) Hi Speed is automatically selected for about one second when power goes on. This gives the motor full torque at the start. If needed this time can be increased ( the value of C1 would need to be increased). 2) High Speed can also be selected by applying 12 volts to the High Speed signal wire. This gives Hi Speed regardless of the Progressive signal.

When the Progressive signal gets to approximately 4.5 volts, the circuit achieves 100% PWM Hi Speed. How does this technology help ?: The benefits noted above are technology driven. The more important question is how the PWM technology Jumping from a 1970s technology into the new millennium offers: Longer battery life: reducing the costs of the solar system reducing battery disposal problems More battery reserve capacity: increasing the reliability of the solar system reducing load disconnects opportunity to reduce battery size to lower the system cost Greater user satisfaction: get more power when you need it for less money!!

SPACE VECTOR PWM

The Space Vector PWM generation module accepts modulation index commands and generates the appropriate gate drive waveforms for each PWM cycle. This section describes the operation and configuration of the SVPWM module. A three-phase 2-level inverter with dc link configuration can have eight possible switching states, which generates output voltage of the inverter. Each inverter switching state generates a voltage Space Vector (V1 to V6 active vectors, V7 and V8 zero voltage vectors) in the Space Vector plane (Figure: space vector diagram). The magnitude of each active vector (V1to V6) is 2/3 Vdc (dc bus voltage). The Space Vector PWM (SVPWM) module inputs modulation index commands (U_Alpha and U_Beta) which are orthogonal signals (Alpha and Beta) as shown in Figure. The gain characteristic of the SVPWM module is given in Figure . The vertical axis of Figure represents the normalized peak motor phase voltage (V/Vdc) and the horizontal axis represents the normalized modulation index (M). The inverter fundamental line-to-line Rms output voltage (Vline) can be approximated (linear range) by the following equation: .. (1) Where dc bus voltage (Vdc) is in volts

Space Vector Diagram This document is the property of International Rectifier and may not be copied or distributed without expressed consent

Transfer Characteristics

The maximum achievable modulation (Umag_L) in the linear operating range is given by: .. (2) Over modulation occurs when modulation Umag > Umag_L. This corresponds to the condition where the voltage vector in (Figure: voltage vector rescaling)increases beyond the hexagon boundary. Under such circumstance, the Space Vector PWM algorithm will rescale the magnitude of the voltage vector to fit within the Hexagon limit. The magnitude of the voltage vector is restricted within the Hexagon; however, the phase angle () is always preserved. The transfer gain (Figure :transfer characteristics) of the PWM modulator reduces and becomes nonlinear in the over modulation region.

Voltage Vector Rescaling This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

PWM Operation Upon receiving the modulation index commands (UAlpha and UBeta) the sub-module SVPW M_Tm starts its calculations at the rising edge of the PWM Load signal. The SVPWM _Tm module implements an algorithm that selects (based on sector determination) the active space vectors (V1 to V6) being used and calculates the appropriate time duration (w.r.t. one PWM cycle) for each active vector. The appropriated zero vectors are also being selected. The SVPWM _Tm module consumes 11 clock cycles typically and 35 clock cycles (worst case Tr) in over modulation cases. At the falling edge of nSYNC, a new set of Space Vector times and vectors are readily available for actual PWM generation (PhaseU, PhaseV, PhaseW) by sub module Pwm Generation. It is crucial to trigger PwmLoad at least 35 clock cycles prior to the falling edge of nSYNC signal; otherwise new modulation commands will not be implemented at the earliest PWM cycle. The above Figures voltage vector rescaling illustrates the PWM waveforms for a voltage vector locates in sector I of the Space Vector plane (shown in Figure). The gating pattern outputs (PWMUH PWMWL) include dead time insertion

3-phase Space Vector PWM

2-phase (6-step PWM) Space Vector PWM

PWM Carrier Period: Input variable PwmCval controls the duration of a PWM cycle. It should be populated by the system clock frequency (Clk) and Pwm frequency (PwmFreq) selection. The variable should be calculated as:

.. (3) The input resolution of the Space Vector PWM modulator signals U_Alpha and U_Beta is 16-bit signed integer. However, the actual PWM resolution (PwmCval) is limited by the system clock frequency. Dead time Insertion Logic Dead time is inserted at the output of the PWM Generation Module. The resolution is 1 clock cycle or 30nsec at a 33.3 MHz clock and is the same as those of the voltage command registers and the PWM carrier frequency register.

The dead time insertion logic chops off the high side commanded volt*seconds by the amount of dead time and adds the same amount of volt*seconds to the low side signal. Thus, it eliminates the complete high side turn on pulse if the commanded volt*seconds is less than the programmed dead time.

Dead time Insertion The dead time insertion logic inserts the programmed dead time between two high and low side of the gate signals within a phase. The dead time register is also double buffered to allow on the fly dead time change and control while PWM logic is inactive. Symmetrical and Asymmetrical Mode Operation There are two modes of operation available for PWM waveform generation, namely the Center Aligned Symmetrical PWM (Figure) and the Center Aligned Asymmetrical PWM (Figure)The volt-sec can be changed every half a PWM cycle (Tpwm) since Pwm Load occurs every half a PWM cycle (compare Figure :symmetrical pwm and Figure :asymmetrical PWM). With Symmetrical PWM mode, the inverter voltage Config = 0), the inverter voltage can be changed at two times the rate of the switching frequency. This will provide an increase in voltage control bandwidth, however, at the expense of increased current harmonic

Asymmetrical PWM Mode Three-Phase and Two-Phase Modulation Three-phase and two-phase Space Vector PWM modulation options are provided for the IRMCx203. The Volt-sec generated by the two PWM strategies are identical; however with 2phase modulation the switching losses can be reduced significantly, especially when high switching frequency (>10Khz) is employed. Figure: three-phase and two phase modulation shows the switching pattern for one PWM cycle when the voltage vector is inside sector 1

Three Phase and Two Phase Modulation The field Two Phase PWM of the PWM Config write register group provides selection of three-phase or two-phase modulation. The default setting is three-phase modulation. Successful operation of two-phase modulation in the entire speed operating range will depend on hardware configuration. If the gate driver employs a bootstrap power supply strategy, disoperation will occur at low motor fundamental frequencies (< 2Hz) under two-phase modulation control. Sinusoidal Pulse Width Modulation In many industrial applications, Sinusoidal Pulse Width Modulation (SPWM), also called Sine coded Pulse Width Modulation, is used to control the inverter output voltage. SPWM maintains good performance of the drive in the entire range of operation between zero and 78 percent of the value that would be reached by square-wave operation. If the modulation index exceeds this value, linear relationship between modulation index and output voltage is not maintained and the over-modulation methods are required Space Vector Pulse Width Modulation A different approach to SPWM is based on the space vector representation of voltages in the d, q plane. The d, q components are found by Park transform, where the total power, as well as the impedance, remains unchanged.

Fig: space vector shows 8 space vectors in according to 8 switching positions of inverter, V* is the phase-to-center voltage which is obtained by proper selection of adjacent vectors V1 and V2.

Inverter output voltage space vector

Determination of Switching times The reference space vector V* is given by Equation (1), where T1, T2 are the intervals of application of vector V1 and V2 respectively, and zero vectors V0 and V7 are selected for T0. V* Tz = V1 *T1 + V2 *T2 + V0 *(T0/2) + V7 *(T0/2).(4)

Space Vector Pulse Width Modulation (continued) Fig. below shows that the inverter switching state for the period T1 for vector V1 and for vector V2, resulting switching patterns of each phase of inverter are shown in Fig. pulse pattern of space vector PWM.

Inverter switching state for (a)V1, (b) V2

Pulse pattern of Space vector PWM Comparison In Fig:- comparison, U is the phase to- center voltage containing the triple order harmonics that are generated by space vector PWM, and U1 is the sinusoidal reference voltage. But the triple order harmonics are not appeared in the phase-to-phase voltage as well. This leads to the higher modulation index compared to the SPWM.

Comparison of SPWM and Space Vector PWM As mentioned above, SPWM only reaches to 78 percent of square wave operation, but the amplitude of maximum possible voltage is 90 percent of square-wave in the case of space vector PWM. The maximum phase-to-center voltage by sinusoidal and space vector PWM are respectively Vmax = Vdc/2 : Sinusoidal PWM Vmax = Vdc/3 : Space Vector PWM Where, Vdc is DC-Link voltage. This means that Space Vector PWM can produce about 15 percent higher than Sinusoidal PWM in output voltage.

SVM PWM Technique The Pulse Width modulation technique permits to obtain three phase system voltages, which can be applied to the controlled output. Space Vector Modulation (SVM) principle differs from other PWM processes in the fact that all three drive signals for the inverter will be created simultaneously. The implementation of SVM process in digital systems necessitates less operation time and also less program memory. The SVM algorithm is based on the principle of the space vector u*, which describes all three output voltages ua, ub and uc : u* = 2/3 . ( ua + a . ub + a2 . uc ) (5) Where a = -1/2 + j . v3/2 We can distinguish six sectors limited by eight discrete vectors u0u7 (fig:- inverter output voltage space vector), which correspond to the 23 = 8 possible switching states of the power switches of the inverter.

Space vector Modulation The amplitude of u0 and u7 equals 0. The other vectors u1u6 have the same amplitude and are 60 degrees shifted. By varying the relative on-switching time Tc of the different vectors, the space vector u* and also the output voltages ua, ub and uc can be varied and is defined as: ua = Re ( u* ) ub = Re ( u* . a-1) uc = Re ( u* . a-2) (6)

During a switching period Tc and considering for example the first sector, the vectors u0, u1 and u2 will be switched on alternatively.

Definition of the Space vector Depending on the switching times t0, t1 and t2 the space vector u* is defined as: u* = 1/Tc . ( t0 . u0 + t1 . u1 + t2 . u2 ) u* = t0 . u0 + t1 . u1 + t2 . u2

u* = t1 . u1 + t2 . u2 Where t0 + t1 + t2 = Tc and t0 + t1 + t2 = 1

.. (7)

t0, t1 and t2 are the relative values of the on switching times. They are defined as: t1 = m . cos ( a + p/6) t2 = m . sin a t0 = 1 - t1 - t2

Their values are implemented in a table for a modulation factor m = 1. Then it will be easy to calculate the space vector u* and the output voltages ua, ub and uc. The voltage vector u* can be provided directly by the optimal vector control laws w1, vsa and vsb. In order to generate the phase voltages ua, ub and uc corresponding to the desired voltage vector u* the following SVM strategy is proposed.

Total harmonic distortion:

The total harmonic distortion, or THD, of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. Lesser THD allows the components in a loudspeaker, amplifier or microphone or other equipment to produce a more accurate reproduction by reducing harmonics added by electronics and audio media. A THD rating < 1% is considered to be in high-fidelity and inaudible to the human ear

To understand a system with an input and an output, such as an audio amplifier, we start with an ideal system where the transfer function is linear and time-invariant. When a signal passes through a non-ideal, non-linear device, additional content is added at the harmonics of the original frequencies. THD is a measurement of the extent of that distortion. When the input is a pure sine wave, the measurement is most commonly the ratio of the sum of the powers of all higher harmonic frequencies to the power at the first harmonic, or fundamental, frequency: According to Wikipedia, the online encyclopedia for all things defined, Total Harmonic Distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. Lesser THD, for example, allows the components in a loudspeaker, amplifier or microphone or other equipment to make a violin sound like a violin when played back and not a cello or simply a distorted noise. (1) As a musician, I typically have learned about harmonics in terms of chords, distortion and found them useful in tuning guitars at various frets across the neck of the guitar. For those of us in the lighting and electrical world, THD refers to the Harmonic Distortion present with most electrical equipment, and more specifically now, the distortion present with electronic ballasts. THD is the measurement of the distortion created from the equipments current draw. True resistive loads, such as an incandescent light bulb, do not have THD. Equipment containing coils and capacitors, such as motors, drives, fluorescent lighting and HID lighting, have some measure of THD. In the true engineering sense; only fundamental frequency current can provide real power. Systems with Power Factor correction capacitors and motors are considered to be linear loads with acceptable (negligible) distortion levels. However, solid-state electronic devices have been shown to be the largest contributor to distortion due to the switching of diode bridges producing a discontinuous current, which then causes a distorted sine wave. (2) In four wire WYE systems such as 120/208 and 277/480-volt systems; harmonics may cause a problem with overheating of the neutral wire. The phase wires should also be designed for the increased harmonic current, but since the triplens are additive, the problem is especially

critical on the neutral. The third harmonic and other triplens (9th, 15th, etc.) Are additive. Total Harmonic Distortion is the percentage of all of these additive values in relation to the total load. The sum of triplen harmonics greater than 33 percent will result in neutral current greater than individual line currents. The resultant current exceeds the neutral conductors rating and causes overheating of the neutral and/or transformer. It is a common misconception that electronic ballasts increase THD. Currently available electronic ballasts actually decrease the THD on an electrical system compared to a system applying magnetic ballasts. ANSI C82.11 requires that the maximum THD of electronic ballasts not exceed 32 percent and the maximum triplens not exceed 30 percent. Electronic ballasts today are rated at less than 20 percent, 15 percent, or less than 10 percent THD. The magnetic ballast is rated in the 20 to 28 percent range. Electronic ballasts reduce THD in two ways. 1. The electronic ballast has a lower THD percentage than the magnetic ballast. 2. The biggest reduction comes from the fact that electronic ballasts reduce the total load.

BASICS OF TWO-LEVEL A ND MULTILEVEL INVERTERS

Two-Level Inverters This is the most widely used topology in various lowand medium-power applications. The full-bridge configuration of the three-phase voltage source inverter is shown in Figure 1. The witching logic to obtain output voltage for a 1200 mode of operation is shown in Table 1. This topology can be used at a very high switching frequency to obtain low THD by using PWM techniques. Power devices are to be connected in seriesparallel to achieve a large power capability. They suffer from static and dynamic voltage sharing problems in series and parallel connection of power devices, high rate of change of voltage due to synchronous commutation of Series devices and inclusion of high switching frequency harmonic contents in inverter output voltage [3]. Multilevel Inverters Multilevel inverters have grown as better counterparts to conventional two-level inverters. Commonly employed multilevel inverter topologies are Diode Clamped, Capacitor Clamped and Cascaded Multilevel inverters. In all these topologies, the output voltage is synthesized from several levels of input voltages obtained from several capacitors connected across the dc bus. In a capacitor clamped inverter, both real and reactive power can be controlled, but it suffers from higher switching losses due to real power transfer thus reducing the efficiency of power conversion. Also, it requires a large number of storage capacitors at higher levels. The cascaded inverter uses a large number of separate dc sources for each of the bridges. However, in the diode clamped topology, all devices are switched at the fundamental frequency resulting in low switching losses and high efficiency. Other main features of this topology are controlled reactive power flow between source and load, much better dynamic voltage sharing among switching devices and

Simple topological structure. Therefore, diode clamped inverter topology is considered here for study. The control logic is simple, especially for back-to-back inter-tie connections of two systems. However, it requires a large number of clamping diodes for a large number of output Voltage levels. To produce an m-level output phase voltage, (m-1) switches are required for each half phase leg, a total of (m-1) dc link capacitors for energy storage and (m-1)*(m-2) clamping diodes for each phase leg [1-2]. Three-Level Diode Clamped Multilevel Inverter (DCMLI) Three-phase diode clamped three-level inverter (neutral point clamped) topology is shown in Figure 2. The circuit consists of two dc link capacitors, 12 power switches and six clamping diodes. The middle point of the dc bus capacitor is known as neutral point n. The main feature Of this topology is clamping diodes that clamp the switch voltage to half of the dc bus voltage, reducing the voltage stress of the switching device. The output voltage has three different states: +, 0 and and the corresponding output phase voltages are +Vdc/2, 0 and -Vdc/2. Switching States to synthesize the output voltages for phase A are defined in Table 2. A similar logic can be applied for the other two phases. Five-Level DCMLI The circuit diagram of the five-level DCMLI topology is shown in Figure 3. It consists of 24 power switches and 36 clamping diodes. The DC bus has four capacitors for a DC bus voltage Vdc. The voltage across each capacitor

Figure Three-phase two-level inverter.

Is Vdc/4; thus, the voltage stress across each device will Be limited to Vdc/4 through the clamping diode. Table 3 shows the switching combinations and corresponding Output phase voltage levels where switching state 1 represents the switch is in on condition and state 0 indicates the switch is in off condition. When the Number of levels is high enough in the DCMLI, harmonic contents in the output voltage and current get reduced to avoid the need for filters. 3. Switching Loss Calculations: Consider a single MOSFET switch connected across a dc voltage of value Vdc. Current through switch during on time is considered as Idc. Figure 4 shows the waveforms of the voltage across and the current through the switch when it is operated at a switching frequency of Fs = 1/Ts, where Ts is the switching period. To simplify the expressions, the switching waveforms are

represented by linear approximations. In the figure, vm and im are the voltage across and the current through the MOSFET [3, 5]. Switching losses can be calculated from the turn-on and Turn-off characteristics of the devices. Instantaneous voltage and current during turn on time tc(on) are

Instantaneous power during the interval tc(on) is

And energy dissipated during this interval is tc(on),

And during turn-off transition, of t c(off), the current falls fr om Idc to zero and the Von rises linearly to Vdc.

The instantaneous voltage and current during this period are

The instantaneous power dissipated during the interval

Hence, the energy dissipated can be found as tc(off),tc(off) is

With a switching frequency of Fs, the average switching loss in the switch during each transition of turn on and Turn off can be found as

Hence, the average switching loss Psw in the switch is

Eqn. (11) shows that the switching power loss in a semiconductor switch varies linearly with the switching frequency and switching times. Therefore, with the devices having short switching times, it is possible to operate them at a higher switching frequency thus avoiding excessive switching power losses in the device [8-10].

4. Modulation Technique Modulation techniques for voltage source inverters may be carrier based or carrier-less and open loop or Closed loop. These modulation or control techniques for multilevel voltage source inverters are classified in Figure 5. Simulation investigation of different multilevel control techniques have been presented in [11]. The SPWM technique is considered for study in this paper. It is the simple technique to be implemented. In the SPWM technique, a triangular carrier wave at a high switching frequency is compared with the sinusoidal Reference wave at a fundamental output frequency. The SPWM technique is again divided into Alternate Phase Opposition Disposition, Phase Opposition Disposition and In Phase (PH) [12]. Figure 6 shows the generation of switching pulses for power device S1 of the two-level inverter shown in Figure 1. One triangular carrier wave is compared with a sinusoidal reference wave to generate switching pulses. For power device S4, the complementary of this pulse is to be given. The control principle of the SPWM is to use several triangular carrier signals keeping only one modulating sinusoidal signal. If an m-level inverter is employed, (m-1) level shifted carriers will be needed.

Two and four triangular carrier signals are needed for three- and five-level inverters, respectively. The carriers Have the same frequency fc and the same peak-to-peak amplitude Ac. The zero reference is placed in the middle Of the carrier set. The modulating signal is a sinusoid of frequency fm and amplitude Am. At every instant, each Carrier is compared with the modulating signal. Each comparison switches the switch on if the modulating Signal is greater than the triangular carrier assigned to that switch. Obviously, the actual driving signals for The power devices can be derived from the results of the modulatingcarrier comparison by means of a control Logic circuit. Figure 7 shows the generation of switching pulses for power devices Sa1 and Sa2 of the three-level inverter shown in Figure 2. Pulses for the lower two devices Sa1 and Sa2 are complementary to these pulses,

Respectively. Figure 8 shows the generation of switching pulses for power devices Sa1, Sa2, Sa3 and Sa4 of the fivelevel Inverter shown in Figure 3. Pulses for the lower four devices Sa1 , Sa2 , Sa3 and Sa4 are complementary to these pulses, respectively. Vr is the reference sin wave and Vt1, Vt2, Vt3, Vt4 are four carrier signals

Structure of 21-level based on proposed multilevel inverter:

SWITCHING PATTERN TO PRODUCE DIFFERENT OUTPUT VOLTAGE LEVELS

CHAPTER
MATLAB
Matlab is a high-performance language for technical computing. It integrates computation, visualization, and programming in an easy-to-use environment where problems and solutions are expressed in familiar mathematical notation. Typical uses include Math and computation Algorithm development Data acquisition Modeling, simulation, and prototyping Data analysis, exploration, and visualization Scientific and engineering graphics Application development, including graphical user interface building. Matlab is an interactive system whose basic data element is an array that does not require dimensioning. This allows you to solve many technical computing problems, especially those with matrix and vector formulations, in a fraction of the time it would take to write a program in a scalar no interactive language such as C or Fortran. The name matlab stands for matrix laboratory. Matlab was originally written to provide easy access to matrix software developed by the linpack and eispack projects. Today, matlab engines incorporate the lapack and blas libraries, embedding the state of the art in software for matrix computation. Matlab has evolved over a period of years with input from many users. In university environments, it is the standard instructional tool for introductory and advanced courses in mathematics, engineering, and science. In industry, matlab is the tool of choice for highproductivity research, development, and analysis. Matlab features a family of add-on application-specific solutions called toolboxes. Very important to most users of matlab, toolboxes allow you to learn and apply specialized technology. Toolboxes are comprehensive collections of matlab functions (M-files) that extend the matlab environment to solve particular classes of problems. Areas in which toolboxes are available include signal processing, control systems, neural networks, fuzzy logic, wavelets, simulation, and many others. The matlab system consists of five main parts: Development Environment. This is the set of tools and facilities that help you use matlab functions and files. Many of these tools are graphical user interfaces. It includes the matlab

desktop and Command Window, a command history, an editor and debugger, and browsers for viewing help, the workspace, files, and the search path. The matlab Mathematical Function Library. This is a vast collection of computational

algorithms ranging from elementary functions, like sum, sine, cosine, and complex arithmetic, to more sophisticated functions like matrix inverse, matrix eigenvalues, Bessel functions, and fast Fourier transforms. The matlab Language. This is a high-level matrix/array language with control flow

statements, functions, data structures, input/output, and object-oriented programming features. It allows both "programming in the small" to rapidly create quick and dirty throw-away programs, and "programming in the large" to create large and complex application programs. Matlab has extensive facilities for displaying vectors and matrices as graphs, as well as annotating and printing these graphs. It includes high-level functions for two-dimensional and three-dimensional data visualization, image processing, animation, and presentation graphics. It also includes low-level functions that allow you to fully customize the appearance of graphics as well as to build complete graphical user interfaces on your matlab applications. The matlab Application Program Interface (API). This is a library that allows you to write C and Fortran programs that interact with matlab. It includes facilities for calling routines from matlab (dynamic linking), calling matlab as a computational engine, and for reading and writing MAT-files.

SIMULINK:
Introduction: Simulink is a software add-on to matlab which is a mathematical tool developed by The Math works,(http://www.mathworks.com) a company based in Natick. Matlab is powered by extensive numerical analysis capability. Simulink is a tool used to visually program a dynamic system (those governed by Differential equations) and look at results. Any logic circuit, or control system for a dynamic system can be built by using standard building blocks available in Simulink Libraries. Various toolboxes for different techniques, such as Fuzzy Logic, Neural Networks, dsp, Statistics etc. are available with Simulink, which enhance the processing power of the tool. The main advantage is the availability of templates / building blocks, which avoid the necessity of typing code for small mathematical processes. Concept of signal and logic flow: In Simulink, data/information from various blocks are sent to another block by lines connecting the relevant blocks. Signals can be generated and fed into blocks dynamic / static).Data can be fed into functions. Data can then be dumped into sinks, which could be scopes, displays or could be saved to a file. Data can be connected from one block to another, can be branched, multiplexed etc. In simulation, data is processed and transferred only at Discrete times, since all computers are discrete systems. Thus, a simulation time step (otherwise called an integration time step) is essential, and the selection of that step is determined by the fastest dynamics in the simulated system.

Fig Simulink library browser

Connecting blocks:

fig Connectung blocks To connect blocks, left-click and drag the mouse from the output of one block to the input of another block. Sources and sinks: The sources library contains the sources of data/signals that one would use in a dynamic system simulation. One may want to use a constant input, a sinusoidal wave, a step, a repeating sequence such as a pulse train, a ramp etc. One may want to test disturbance effects, and can use

the random signal generator to simulate noise. The clock may be used to create a time index for plotting purposes. The ground could be used to connect to any unused port, to avoid warning messages indicating unconnected ports. The sinks are blocks where signals are terminated or ultimately used. In most cases, we would want to store the resulting data in a file, or a matrix of variables. The data could be displayed or even stored to a file. the stop block could be used to stop the simulation if the input to that block (the signal being sunk) is non-zero. Figure 3 shows the available blocks in the sources and sinks libraries. Unused signals must be terminated, to prevent warnings about unconnected signals.

fig Sources and sinks Continuous and discrete systems:

All dynamic systems can be analyzed as continuous or discrete time systems. Simulink allows you to represent these systems using transfer functions, integration blocks, delay blocks etc.

fig continous and descrete systems Non-linear operators:

A main advantage of using tools such as Simulink is the ability to simulate non-linear systems and arrive at results without having to solve analytically. It is very difficult to arrive at an analytical solution for a system having non-linearities such as saturation, signup function, limited slew rates etc. In Simulation, since systems are analyzed using iterations, non-linearities are not a hindrance. One such could be a saturation block, to indicate a physical limitation on a parameter, such as a voltage signal to a motor etc. Manual switches are useful when trying simulations with different cases. Switches are the logical equivalent of if-then statements in programming.

fig simulink blocks Mathematical operations: Mathematical operators such as products, sum, logical operations such as and, or, etc. .can be programmed along with the signal flow. Matrix multiplication becomes easy with the matrix gain block. Trigonometric functions such as sin or tan inverse (at an) are also available. Relational operators such as equal to, greater than etc. can also be used in logic circuits

fig Simulink math blocks SIGNALS & DATA TRANSFER: In complicated block diagrams, there may arise the need to transfer data from one portion to another portion of the block. They may be in different subsystems. That signal could be dumped into a goto block, which is used to send signals from one subsystem to another. Multiplexing helps us remove clutter due to excessive connectors, and makes matrix(column/row) visualization easier.

fig signals and systems Making subsystems Drag a subsystem from the Simulink Library Browser and place it in the parent block where you would like to hide the code. The type of subsystem depends on the purpose of the block. In general one will use the standard subsystem but other subsystems can be chosen. For instance, the subsystem can be a triggered block, which is enabled only when a trigger signal is received. Open (double click) the subsystem and create input / output PORTS, which transfer signals into and out of the subsystem. The input and output ports are created by dragging them from the Sources and Sinks directories respectively. When ports are created in the subsystem, they automatically create ports on the external (parent) block. This allows for connecting the appropriate signals from the parent block to the subsystem. Setting simulation parameters: Running a simulation in the computer always requires a numerical technique to solve a differential equation. The system can be simulated as a continuous system or a discrete system based on the blocks inside. The simulation start and stop time can be specified. In case of

variable step size, the smallest and largest step size can be specified. A Fixed step size is recommended and it allows for indexing time to a precise number of points, thus controlling the size of the data vector. Simulation step size must be decided based on the dynamics of the system. A thermal process may warrant a step size of a few seconds, but a DC motor in the system may be quite fast and may require a step size of a few milliseconds.

SIMULATION RE SULTS:COMPARISON OF THE PROPOSED S TRUCTURE WITH CONVENTIONAL CASCADED MULTILEVEL INVERTER The main purpose of this paper is reduction of the components of the cascaded multilevel inverters. As mentioned in previous section, the proposed structure is a combination of bidirectional and unidirectional switches. Since each switch needs only one deriver circuit, the overall number of deriver circuits is equal to the number of switches (N drive,) . In Table III, different parameters of proposed structure concerning the number of voltage steps in the three algorithms are summarized.

To examine the performance of proposed multilevel inverter in generation of a desired output voltage waveform, a 21-level inverter based on proposed topology as shown in Fig. 6 is simulated in MA TLABSIMULINK environment. It should be mentioned that the magnitude of structure in Fig. 6 is chosen based on second algorithm. This inverter can generate staircase output voltage waveform with maximum of 200V. The load is a series R-L with magnitudes R = 70Q and L = 55mH , respectively. There are several modulation strategies [8, 13]. In this work, the fundamental frequency switching technique has been used. Table IV shows the switching pattern of structure in Fig. 6 to produce different output voltage levels. Fig. 7 shows the control block diagram of inverter. The main idea in control strategy is to deliver the load a voltage that minimizes the error with respect to reference voltage. For highlighting sufficiency of proposed structure, different parameters of recommended structure for the same conditions are compared to that presented in [4] (Fig. 4(a, [13] (Fig. 4(b and conventional cascaded multilevel converters (FigA(c. It is noteworthy that switches used in reference [13] are bidirectional. Although, two IGBTs are used in bidirectional switches, in case of using common emitter configuration, one circuit deriver can be used for them [2]. The dc voltage source magnitudes of [4] and [13] and conventional cascade converter must be selected in a way which all odd and even voltage steps can be produced. For this purpose, for the structure offered in [4], two method including symmetrical (all dc voltage sources are equal) and binary (in which the magnitude of dc sources are selected as a power of 2) is used. Likewise, for the structure offered in [13], only one state can be considered in which all dc voltage sources are set to be equal. Also for the conventional cascaded multilevel inverter three algorithms (symmetrical, binary and trinary) can be considered. The results of comparison for the recommended configuration and pre-mentioned structures are investigated. Fig. 5 compares the recommended configuration with the structures recommended in [4] and [13] and conventional cascaded multilevel inverter concerning the number of switches, number of IGBTs, number of deriver circuits, number of dc voltage sources, variety of sources and maximum standing voltage for symmetrical and asymmetrical structures. Figures 8 -11 shows the output voltage of different parts in structure. As these figures clearly show, the output voltage of each unit can only produce zero or positive values. By adding H-bridge inverter at the output terminal of circuit shown in Fig. 2, it's possible to produce negative value of output

voltage. For the simulated 21-level inverter, the voltage waveforms of load voltage and current are shown in Figs. 12 and 13. From Fig. 13, it's clear that the proposed structure can produce both positive and negative values of output voltage.

MATLAB DESIGN OF CASE STUDY & RESULTS:

Simulation Results:-

CONCLUSION
In this paper, a new topology has been introduced for cascaded multilevel inverters. The proposed structure is a compound of both bidirectional and unidirectional switches which has the advantage of using fewer IGBTs and deriver circuits. Therefore the proposed topology results in reduction of installation area and cost. Also three procedures have been presented for the determination of dc voltage sources' magnitude. Using these algorithms, both symmetrical and asymmetrical configuration has been made for sources of studied structures and by concerning different points of view including the number of IGBTs, deriver circuit, the variety of dc voltage magnitudes, a comparison has been made between the proposed topology and other referred three structures. The results of the simulation for proposed 2I-level inverter demonstrate that the proposed configuration has prominent feature compared to other cascaded multilevel inverters.

REFERENCES:[1] 1.S. Lai and F.Z. Peng, "Multilevel converters - a new breed of power converters, " IEEE Trans. Ind Appl., vol. 32, no. 3, pp. 509-17, May/June 1996. [2] 1. Ebrahimi, E. Babaei, and G.B. Gharehpetian "A new multilevel converter topology with reduced number of power electronic components," Accepted and will be published on IEEE Trans. Ind. Electron. [3] S. De, D. Banerjee I , K. Siva kumar, K. Gopakumar, R. Ramchand, and C. Patel, "Multilevel inverters for low-power application," lET Power Electron., vol. 4, no. 4, pp. 384-392, 2011. [4] E. Babaei and S.H. Hosseini, "New cascaded multilevel inverter topology with minimum number of switches," Elsevier Journal of Energy Conversion and Management, vol. 50, no. II, pp. 2761-2767, Nov. 2009. [5] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, "A non conventional power converter for plasma stabilization," in Proc. Power Electron. Spec. Conj., 1988, pp. 122-129. [6] T.A. Meynard and H. Foch, "Multi-level choppers for high voltage applications," in Proc. Eur. Con! Power Electron. Appl., 1992, vol. 2, pp. 45-50. [7] A. Nabae, 1. Takahashi, and H. Akagi, "A new neutral-pointclamped PWM inverter," IEEE Trans. Ind Appl., vol. IA-17, no. 5,p p. 518-523,S ep./Oct. 1981. [8] E. Babaei, "A cascade multilevel converter topology with reduced number of

switches," IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2657-2664, Nov. 2008. [9] J. Ebrahimi, E. Babaei, and G.B. Gharehpetian "A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications," Accepted and will be published on IEEE Trans. Power Electron.

[10] S. Mekhilef and M.N. Abdul Kadir, "Novel vector control method for three-stage hybrid cascaded multilevel inverter," IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1339-1349, April 2011. [II] S.D.G. Jayasinghal, D.M. Vilathgamuwal, and U.K. Madawala, "Cascade multilevel static synchronous compensator configuration for wind farms," lET Power Electron., vol. 4, no. 5, pp. 548-556,2011. [12] E. Babaei and M.S. Moeinian, "Asymmetric cascaded multilevel inverter with charge balance control of a low resolution symmetric subsystem," Elsevier Journal of Energy Conversion and Management, vol. 51, no. 11, pp. 2272-2278, Nov. 2010. [13] E. Babaei, S.H. Hosseini, G.B. Gharehpetian, M. Tarafdar Haque, and M. Sabahi, "Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology," Elsevier Journal of Electric Power Systems Research, vol. 77, no. 8, pp. 10731085, June 2007.