Three-phase high power factor AC/DC converter

B.-R. Lin and T.-Y. Yang

Abstract: A unidirectional three-phase AC/DC converter is proposed to obtain almost unity power
factor, draw sinusoidal line currents and keep the DC-bus voltage constant. Two active switches
and two power diodes are used in each converter leg to generate a three-level PWM waveform on
the AC terminal voltages. The proposed converter has simpler circuit configuration compared with
the conventional three-level PWM converters. The classical proportional-integral voltage controller
and the hysteresis current controller are adopted in the control scheme to achieve DC-bus voltage
regulation and line-current command tracking. A neutral-point voltage compensator is used to
balance the neutral-point voltage due to load change. The validity and effectiveness of the proposed
control algorithm is verified through simulations and experimental results.

1 Introduction disadvantages of the multilevel rectifiers are the large

Diode or phase-controlled rectifiers are widely utilised in the
front-end converter for the uncontrollable or controllable
DC-bus voltage in industrial and commercial applications.
However, low power factor and nonsinusoidal line currents
are drawn from the AC source owing to a large electrolytic
capacitor used on the DC link. Power pollutants such as
reactive power and current harmonics result in line-voltage
distortion, heating of the transformer core and electrical
machines, and increased losses in the transmission and
distribution line. To meet the relevant standards in Europe
and America, several current wave-shaping solutions [1–4]
have been proposed to achieve power factor correction and
current-harmonic reduction. In [1] conventional single-
phase rectifiers with one, two or four switches were used
to achieve power factor correction based on two-level
(unipolar or bipolar) pulse-width modulation (PWM). In [2]
the single-phase voltage-doubler boost rectifiers with one,
two, three or four switches were used to achieve power
factor correction and DC-bus voltage regulation. The DC-
bus voltage is twice the peak mains voltage. Switched mode
rectifiers with three or four rectifier legs can achieve high
power factor and low current harmonics in the three-phase
three-wire or four-wire systems. Six or eight power switches
are used in the three-leg or four-leg converter of [5–9] to
generate bipolar PWM waveforms on the AC terminal. If
the bidirectional power flow is not necessary in the
application system, switched-mode rectifiers are not a good
choice for the large number of power switches. Multilevel
rectifiers and inverters have been proposed [10–15] for high-
power and medium-voltage applications because they
provide advantages such as the low voltage rating of power
semiconductors and low voltage harmonics. However, the
r IEE, 2005
IEE Proceedings online no. 20045201
doi:10.1049/ip-epa:20045201
Paper first received 28th October 2004 and in final revised form 15th January
2005. Originally published online: 8th April 2005
The authors are with the Power Electronics Research Laboratory, Department
of Electrical Engineering, National Yunlin University of Science and
Technology, Touliu City, Yunlin 640, Taiwan, ROC
number of power semiconductors in the circuit, a complex
control scheme and the neutral-point voltage balance
problem. In industrial applications with a unidirectional
power flow, conventional multilevel converters are too
expensive and complicated to implement.
A three-phase three-level AC/DC converter with fewer
power switches is presented to achieve almost unity power
factor, to regulate the DC-link voltage and to achieve fast
dynamic response. Six active switches are required in the
proposed converter. Compared with conventional neutral-
point diode-clamped or capacitor-clamped converters the
proposed converter has fewer power switches and a simple
control scheme. Two control loops are used in the proposed
control algorithm: a proportional-integral voltage controller
in the outer control loop to maintain the DC-link voltage
constant, and an hysteresis-based current controller in the
inner control loop to track line-current commands. A
voltage compensator is adopted to balance the neutral-point
voltage. Three voltage levels are generated on the AC
terminal to neutral-point voltages. The effectiveness and
validity of the proposed control strategy are verified
through computer simulation and experimental results.
2 System configuration and operation principle
2.1 System configuration
Conventional three-level AC/DC converters are based on
neutral-point clamped, flying capacitor and series connec-
tions of H-bridge topologies. A three-level neutral-point
diode-clamped converter needs four active switches and two
clamping diodes in each converter leg to achieve power
factor correction. A three-level converter with flying
capacitor topology needs four active switches and one
flying capacitor to draw a sinusoidal line current from the
utility system. Figure 1a shows the proposed single-phase
unidirectional power flow rectifier to draw a sinusoidal line
current with almost unity power factor and maintain the
DC-bus voltage constant. There are a boost inductor L, two
power diodes Da1 and Da2, two DC-bus capacitors C1 and
C2, and two active switches Sa1 and Sa2 in the proposed
converter. The voltage stress of switch Sa2 and diode Da2 is
equal to half the DC-bus voltage, and the voltage stress of

IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 485
 vdc vdc
p vsa > 0 isa p
i1 io i1 io
Da 2 vC 1
L, r Da 2
L, r vC 1
isa a C1
isa a C1
vsa Sa1 Sa 2

load
o vsa

load
i2
o
vC 2
Da1 i2
C2
vC 2
i3
n C2
a
n
a

vsa Da 2 vdc
L, r a
vdc vsa > 0 isa
isa p
p io
Sa1 Sa 2 i1 io
Da1 L, r vC 1
vC 1

Db 2 C1 isa a C1
iso vsb L, r Sa 2
b o vsa

load

load
isb o
i2 i2
Sb1 Sb 2
vC 2
Db1 vC 2
C2
C2
i3
vsc Dc 2 n
L, r
c n
isc
Sc1 Sc 2 b
Dc1
vdc
b
vsa < 0 isa p
io
Fig. 1 Proposed unidirectional AC/DC converter v
L, r C1
a Single-phase circuit configuration
b Three-phase circuit configuration isa a C1
vsa Sa1

load
o
switch Sa1 and diode Da1 is equal to the DC-bus voltage. i2
No clamping capacitor or diode is needed in the proposed vC 2
C2
single-phase converter. A unipolar PWM voltage waveform
is generated on the voltage vao. Figure 1b shows the system n
configuration of the proposed three-phase three-level AC/ c
DC converter. It consists of three converter legs, three boost
inductors on the AC side and two capacitors in series on the vdc
DC side. Two power switches and two fast recovery diodes vsa < 0 isa p
are used in each leg. The main functions of the proposed io
vC 1
three-phase converter are current harmonic elimination, L, r
neutral-point voltage balance, unity power factor and DC- a
isa C1
link voltage regulation. Two control loops in the system vsa o load
achieve DC-link voltage regulation and line-current track-
ing. The hysteresis comparators in the inner control loop i2
track the line-current commands. The proportional-integral vC 2
Da1 C2
controller in the outer control loop maintains the DC-link
i3
voltage constant. n
d
2.2 Principle of operation
There are two independent active switches in the proposed Fig. 2 Operating states of proposed single-phase AC/DC converter
converter leg. Unipolar PWM voltage waveforms can be a State 1
generated on the AC terminal to neutral-point voltages. b State 2
c State 3
Before analysis of the proposed converter the following
d State 4
assumptions are made: the power switches are ideal; the
supply voltage is constant during one switching period;
Sxy ¼ 1 (or 0) if active switch Sxy is turned on (or off),
x ¼ aBc, y ¼ 1B2; and the capacitor voltages on the DC (vL ¼ vsa
vdc/2o0). Figure 2b gives the equivalent circuit of
side are equal (vC1 ¼ vC2 ¼ vdc/2). In each converter leg there second operating state. The line current flows through the
are four operation states shown in Fig. 2 to generate three body diode of active switch Sa1 and active switch Sa2. The
different voltage levels. Figure 2a gives the equivalent circuit AC-side voltage vao equals 0. The boost inductor voltage
of the first operating state. In this state, positive line current equals vsa. The line current isa is linearly increasing if the
flows through the body diode of active switch Sa1 and mains voltage vsa is positive. Figure 2c shows the equivalent
diode Da2 to charge capacitor C1. The AC-side voltage third operating state. The negative line current flows
vao equals vdc/2. The line current isa is linearly decreasing through switch Sa1 and the body diode of switch Sa2 to
in this state because the boost inductor voltage is negative obtain AC-side voltage vao ¼ 0. The line current is linearly
486 IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
decreasing because vL ¼ vso0. The equivalent circuit of the Based on (1)–(6) the system equations of the proposed
fourth operating state is given in Fig. 2d. The line current converter can be rewritten as
flows through capacitor C2 and Da1 to generate AC 2 3
disa
terminal voltage vao ¼
vC2. The negative line current will 6 dt 7
6 disb 7
charge capacitor C2. The boost inductor voltage equals 6 7
6 dt 7
6 di 7
vsa+vC240 such that the line current is linearly increasing. 6 sc 7
6 dt 7
In state 4 only one diode Da1 is conducting as shown 6 7
6 dvC1 7
6 dt 7
in Fig. 2d. However, there are two devices conducting in 4
dvC2
5
states 1–3 (Fig. 2a–2c). dt

Based on this analysis of four operating states in each 2 r

0 0
converter leg, two operating states can be selected in each 6
6
L
6 r
half cycle of mains voltage to control the line current with 6 0

L
0
6
almost unity power factor. During the positive line current, 6
¼6 0 0

r
states 1 and 2 are used to generate high voltage level (vdc/2) 6 L
6
6 1
Sa2  signðv Þ 1
Sb2  signðv Þ 1
Sc2  signðv Þ
and low voltage level (0) on the voltage vao. During the 6
4 C1 sa C1 sb C1 sc

negative phase voltage, states 3 and 4 are selected to
1
C2Sa1 ½1
signðvsa Þ
1
C2Sb1 ½1
signðvsb Þ
1
C2Sc1 ½1
signðvsc Þ
generate voltage levels 0 (high voltage level) and
vdc/2 (low 3
voltage level) on the AC terminal voltage, respectively.
1
L Sa2 signðvsa Þ 1
LSa1 ½1
signðvsa Þ
7
7
During each half cycle of mains voltage, the high voltage
1
L Sb2 signðvsb Þ 1
LSb1 ½1
signðvsb Þ 7
7
level on the AC side is used to decrease the line current and 7

1
L Sc2 signðvca Þ 1
L Sc1 ½1
signðvsc Þ 7
7
a low voltage level is adopted to increase line current. The 1 1 7
7

RC
5
same analysis of phase-b and phase-c can be achieved 1 RC 1

according to the same analysis. The system behaviour of the
1 RC2
1RC2

proposed AC/DC converter can be expressed as 2

isa
3 2 vsa 3
L
2 3 2 r 32 3 6 7 6 vsb 7
isa
L 0 0 0 0 isa 6 isb
6
7 6 L 7
7 6 7
6 isb 7 6 0
L 0 r
0 0 76 isb 7 6
6 isc
7 þ 6 vsc 7
7 6 L 7 ð8Þ
d6 7 6
6 isc 7 ¼ 6 0 0
Lr 0
76
0 76 isc 7
7 6
4 vC1
7 6 7
5 4 0 5
dt 6 7 6
4 vC 5 4 0 0 1 1 76
0
RC1
RC1 54 vC1 5
7 vC2 0
1
v C2 0 0 0
RC1 2
RC1 2 v C2 Figure 3 gives the simplified circuit of the proposed
2 vsa
vao 3 converter. If the switching signals of the active switches
L are given the state equations (8) can be used to obtain the
6 vsb
vbo 7 line current and DC-side voltages vC1 and vC2 by computer
6 L 7
6 vsc
vco 7 simulation.
þ6 6 7
L
i1 7
6 7
4 C1 5 3 Control scheme

Ci32
The following functions are implemented: almost unity
ð1Þ power factor is achieved; sinusoidal line currents are drawn
from the AC sources; constant DC bus voltage is obtained;
where vao, vbo and vco are AC terminal to neutral-point and the neutral-point voltage on the DC bus is balanced.
voltages and i1 and i3 are DC-side currents. Based on the on The internal high-bandwidth current control system is
and off states of the active switches in the proposed designed to achieve a short settling time and the outer
converter, the DC-side currents and AC terminal voltages low-bandwidth voltage control system is designed to be
can be expressed as somewhat slower.
vao ¼ð1
Sa2 Þsignðvsa ÞvC1
ð1
Sa1 Þ
ð2Þ 3.1 DC-bus voltage regulation
½1
signðvsa ÞvC2 To achieve the power balance between the AC-source side
and DC-load side of the AC/DC converter, a proportional-
vbo ¼ð1
Sb2 Þsignðvsb ÞvC1
ð1
Sb1 Þ integral voltage controller is used to obtain the amplitude of
ð3Þ the line current commands. The amplitude of line current
½1
signðvsb ÞvC2
command is expressed as
Z
vco ¼ð1
Sc2 Þsignðvsc ÞvC1
ð1
Sc1 Þ Is ¼ kp Dvdc þ ki Dvdc dt ð9Þ
ð4Þ
½1
signðvsc ÞvC2
where kp and ki are proportional and integral gains,
respectively, and Dvdc ¼ v*dc
vdc is the DC-bus voltage error,
i1 ¼ð1
Sa2 Þsignðvsa Þisa þ ð1
Sb2 Þsignðvsb Þisb v*dc is the voltage command and vdc is the measured DC-side
ð5Þ
þ ð1
Sc2 Þsignðvsc Þisc voltage. The parameters of voltage controller can be
selected from the given system transfer function and the
designed damping factor and natural angular frequency of
i3 ¼ð1
Sa1 Þ½1
signðvsa Þisa þ ð1
Sb1 Þ the voltage response. The voltage error between the voltage
ð6Þ
½1
signðvsb Þisb þ ð1
Sc1 Þ½1
signðvsc Þisc command and the measured DC-bus voltage can be
reduced by adjusting the amplitude of the line currents.
where To achieve unity power factor at the input side of the

converter, a phase-locked loop circuit generates three unit
1; vsx 40 sinusoidal waves with 1201 phase shift. A VCO- type phase-
signðvsx Þ ¼ ; x ¼ a; b; c ð7Þ
0; vsx o0 locked loop IC (CD4066) and a counter IC (CD4040) are

IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 487
 (1−Sa1)[sign(vsa )−1]−vC 2
i sa

vsa r L
(1−Sa2)sign(vsa)vC 1
(1−Sb1)[sign(vsb )−1]−vC 2
i so i sb

vsb r L
(1−Sb2)sign(vsb)vC 1
(1−Sc1)[sign(vsc )−1]−vC 2
i sc

v sc r L
(1−Sc 2)sign(vsc)vC 1

i1
(1-Sa2)sign(vsa)isa

(1-Sb2)sign(vsb)isb

(1-Sc 2)sign(vsc)isc
[Sa 2 sign(vsa)+
Sa1(1-sign(vsa))]isa

C1
[Sb2 sign(vsb)+ vC 1

Sb1(1-sign(vsb))]isb

R
(1-Sa1)[1-sign(vsa)]isa

(1-Sb1)[1-sign(vsb)]isb

(1-Sc 1)[1-sign(vsc)]isc

[Sc 2 sign(vsc)+ i2
Sc1(1-sign(vsc)]isc
vC 2
C2

i3

Fig. 3 Equivalent circuit of adopted three-phase AC/DC converter

used to achieve an eight-bit signal which is input to the in the next line period. Therefore the capacitor voltage VC1 is
digital signal processor. The digital signal processor compensated. The resultant line-current commands are
generates three balanced sinusoidal waves using a look-up illustrated as
table with the input eight-bit digital signal. These balanced 2  3 2 3 2 3
isa ðtÞ Is sin ot 1
sinusoidal waves are synchronised to three-phase source 4 isb ðtÞ 5 ¼ 4 Is sinðot
2p=3Þ 5 þ Inpc 4 1 5
voltages and expressed as
2 3 2 3 isc ðtÞ Is sinðot þ 2p=3Þ 1
ea ðtÞ sin ot 2 3
4 eb ðtÞ 5 ¼ 4 sinðot
2p=3Þ 5 ð10Þ Is sinðotÞ þ Inpc
ec ðtÞ sinðot þ 2p=3Þ ¼ 4 Is sinðot
2p=3Þ þ Inpc 5 ð13Þ
Is sinðot þ 2p=3Þ þ Inpc
Input-current references are calculated by multiplying the
amplitude of the input-current commands and the gener-
ated unit sinusoidal waves 3.3 Line-current command tracking
2 3 2 3 2 3 Hysteresis current comparators track the input-current
isa ðtÞ ea ðtÞ Is sin ot
4 isb ðtÞ 5 ¼ Is 4 eb ðtÞ 5 ¼ 4 Is sinðot
2p=3Þ 5 references. The appropriate PWM generator obtains the
ð11Þ switching signals for the power switches. The line-current
isc ðtÞ ec ðtÞ Is sinðot þ 2p=3Þ errors between the measured line currents and the current
commands are sent to the hysteresis comparators to
3.2 Neutral-point voltage compensation generate the proper PWM signals for active switches. Based
To balance the neutral-point voltage under load variation a on the operation states shown in Fig. 2, there are three
voltage compensator is used in the control scheme to voltage levels vdc/2, 0 and
vdc/2 generated in each converter
compensate the neutral-point voltage. This additional leg. One high voltage level and one low voltage level can be
current for neutral-point balance is given as selected during the positive and negative half cycle of phase
voltage to track the line current command. During the
Inpc ¼ K½VC2
VC1  ð12Þ
positive half cycle, high voltage levels vdc/2 and low voltage
where VC1 and VC2 are average voltages across capacitors C1 level 0 are generated on the AC terminal to neutral-point
and C2, respectively, and K is a small gain of the neutral- voltage. During the negative half cycle, high voltage level 0
point voltage compensator. To avoid a large DC term in the and low voltage level
vdc/2 are generated on the AC side
line current command due to unbalance neutral-point to control the line current. The high voltage level is adopted
voltage, a limiter can be placed after the neutral-point to decrease the line current and low voltage level is used to
voltage compensator. If the DC capacitor voltage VC2 is increase the line current. Figure 4a shows the source
greater than VC1 , then a small DC value is added to the line- voltage, line current, PWM signals and AC-side voltage for
current command. Capacitor voltage VC1 will be increased each converter leg where x ¼ a, b, c. Figure 4b gives the
488 IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
 vsx power switch shown in Fig. 4b are expressed as
i*sx
i*sx+h Sa1 ¼ signðvsa Þ  hysðDisa Þ ð14Þ
Sa2 ¼ signðvsa Þ  hysðDisa Þ ð15Þ
isx i*sx −h
Sb1 ¼ signðvsb Þ  hysðDisb Þ ð16Þ
Sb2 ¼ signðvsb Þ  hysðDisb Þ ð17Þ
sign(vsx ) 1
0 Sc1 ¼ signðvsc Þ  hysðDisc Þ ð18Þ
hys(
isx ) 1
0 Sc2 ¼ signðvsc Þ  hysðDisc Þ ð19Þ
1
Sx 1 0 where
1


Sx 2 1; ifDisx 4h
0 hysðDisx Þ ¼ ð20Þ
vdc /2 0; ifDisx o
h
vxo 0

−vdc /2 1; if vsx 40
signðvsx Þ ¼ ð21Þ
a 0; if vsx o0

>h Sx 1off, Sx 2 on and Disx ¼ i*sx
isx, signðvsa Þ ¼ 1
signðvsa Þ, x ¼ a, b, c.

Figure 5 gives the block diagram of the proposed control
scheme. The DC-bus voltage controller is used to obtain the
hys(
isx )
amplitude of the line current command. Because the system
>0 input power factor is controlled to be unity, the current
< −h Sx 1 Sx 2 off amplitude from the output of DC-bus voltage controller is
vsx
multiplied with three unit sinusoidal waves in phase with
vsx
mains voltages. A neutral-point voltage compensator
>h Sx 1 Sx 2 off balances the neutral-point voltage. An hysteresis current
<0 controller tracks the line-current commands to achieve
hys(
isx )
power factor correction.

4 Simulation and experimental results

< −h
b
Fig. 4 Phase voltage, current, PWM signals and control strategy
for each converter leg
relationship between the measured phase voltage, hysteresis
current comparator and the PWM signals for active
switches in each converter leg. The PWM signals of active
Sx 1on, Sx 2 off
The proposed three-phase unidirectional AC/DC converter
with power factor correction was verified through simula-
tions and experimental results. A computer software
package based on MATLAB/SIMULINK simulated the
system behaviour. The RMS AC mains voltage is 220 V
with 60 Hz; the boost inductance is 3 mH; the capacitance
of the two capacitors is 2,200 mF; the hysteresis current
band is 0.5 A and the DC-bus voltage vdc is equal to 400 V
in the proposed converter. Figure 6 shows the simulated

neutral-point voltage compensator

VC 1

VC 2 K limiter

isa PWM Generator

Is isa hys(
isa)
i*sa
isa
v*dc PI
isb Sa 2

isb i*sb
isb hys(
isb)

vdc
isc Sb 2
DC-bus voltage regulator hys(
isc)
isc i*sc
isc
Sc 2
sin(t)
vsa + sign(vsa)
vsa~vsc
sin(t−2π /3) Sa 1
PLL −
sin(t+2π /3) vsb + sign(vsb)
Sb 1
−
vsc + sign(vsc)
Sc 1
−

Fig. 5 Block diagram of adopted converter

IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 489
 vsa vsa vsb vsc
200V
0V
20A 50V
0A
isa isb isc
isa

Sa1 20V 10A

0V 0
Sa 2 20V
0V

10ms
vao
200V
0V
5ms
a
a

vsb
200V
0V isa isb isc
20A
0A
isb 10A
0A

Sb1 20V
0V
Sb 2 20V
0V iso
10ms 0A
v bo
200V
0V
5ms
b
b

vsc 200V
vC 1
0V 5V
20A
200V
0A
isc
vC 2
5V
20V 200V
Sc1
0V
20V
Sc 2
0V vC 1+vC 2 5V
10ms 400V

vco 200V
0V 10ms
c
c Fig. 7 Simulated results of proposed converter
Fig. 6 Simulated results of phase voltage, line current, PWM a Three-phase voltage and line current
signals and AC-side voltage b Three-phase current and line neutral current
a Converter leg a c Capacitor voltages on dc side
b Converter leg b
c Converter leg c

In the experimental tests a scaled down laboratory

results of phase voltage, line current, PWM signals and AC
terminal to neutral-point voltage in each phase. Power
switches Sx2 (x ¼ a, b, c) are active during each positive
phase voltage and switches Sx1 are active during each
negative phase voltage. Figure 7a shows the simulated
results of three-phase mains voltages and line currents. The
line currents are balanced and sinusoidal waves with almost
unity power factor. Figure 7b gives the simulated three-
phase line current and neutral-line current. The neutral-line
current is close to zero. The DC-bus capacitor voltages are
illustrated in Fig. 7c. Two capacitor voltages on the DC side
are almost balanced.
490
prototype circuit was implemented to verify the system
performance. The MUR 1560 fast-recovery diode is
adopted for the main power diodes Da1BDc2. MOSFETs
(IRFP460) are used for the active switches Sa1BSc2. The
RMS line voltage of the proposed rectifier is 110 V with 60
Hz; the boost inductance is 3 mH; the capacitance of the
two capacitors is 2,200 mF; the hysteresis current band is
0.5 A and the DC-bus voltage vdc is equal to 200 V in the
proposed converter. The control parameters of DC-bus
voltage controller used in the experimental tests are kp ¼ 0.3
and ki ¼ 6. The gain of neutral-point voltage compensator
is K ¼ 0.03. A single-chip digital signal processor
(TMS320C32) is adopted as the kernel in the implementa-
tion of a digital controller. The control program was written
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
in assembly language and downloaded to the target board.
vsa
The line voltage, inductor current and capacitor voltages are
measured with a potential transformer, current transducer
and optocoupler, respectively. Figure 8 shows the three- isa
phase mains voltage and current before and after the PWM
operation in the proposed converter. Before the PWM
operation, three nonsinusoidal line currents are drawn from
the AC source.
vao

before PWM after PWM

vsa

isa
a
vsb

isb vsb

vsc
isb

isc

vbo

Fig. 8 Experimental results of three-phase mains voltage and

current before and after PWM operation in the proposed converter
vsa, vsb, vsc 100 V/div; isa, isb, isc 10 A/div; time 20 ms/div

After the PWM operation the balanced and sinusoidal b

line currents with nearly unity power factor are drawn from
the AC source. Figure 9 gives the measured results of phase
vsc
voltage, line current and AC side to neutral-point voltage
for each converter leg. Based on the measured results with a
power meter analyser, Tables 1 and 2 give the measured isc
power factor and total harmonic distortion under various
output loads. The power factor is close to 0.995 and THD is
3.4% at the rated output power. Since the hysteresis
comparator is used in the current control loop, the large
total harmonic distortion of line current at light load is vco
measured and shown in Table 2. The measured switching
frequency range is from 5.2 to 7.5 kHz. Figures 10 shows
the experimental results of three-phase voltage and line
current under the balanced and unbalanced AC mains
voltage. In the proposed control scheme three balanced line
currents are drawn from the AC source even if the AC
c

Fig. 9 Measured results of phase voltage, line current and AC-side

voltage
Table 1: Measured power factor of proposed converter a a-phase
under various output powers b b-phase
c c-phase
Output power (W) 100 200 400 600 800 1000

Power factor 0.98 0.99 0.992 0.994 0.995 0.995

mains voltages are unbalanced. Figure 11 shows the
measured source currents including neutral line current
before and after the PWM operation in the proposed
converter. The neutral line current is almost zero after
Table 2: Measured THD of proposed converter under the PWM operation. Figure 12 gives the measured
various output powers dynamic voltage response of the proposed converter due
to load change from 3 to 5 A. Due to the instant
Output power (W) 100 200 400 600 800 1000 load change the energy stored on the capacitors is
discharged to the load. The voltage controller will be
Total harmonic 7.8 6.1 4.6 4.1 3.7 3.4
used to compensate the DC-bus voltage error with the
distortion (%)
change of input-current command. Recovery time of

IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 491
 vsa vC1

i sa

vsb vC2

isb
Io
vsc

isc

load change

a
Fig. 12 Measured results of the two capacitor voltages and load
vsa vsb vsc current from 3 to 5 A output load change
vC1, vC2 20 V/div.; Io 3 A/div.; time 20 ms/div.

5 Conclusions

A novel three-phase unidirectional AC/DC converter with

less power switches has been presented to achieve power
isa isb i sc
factor correction, low current distortion, three-level PWM
operation and regulated DC-bus voltage. Two active
switches and two diodes are used in each converter leg.
Only six switches and six diodes are used in the proposed
converter. Three and five different voltage levels are
generated on the AC terminal to neutral-point voltages
and AC-side line-to-line voltages, respectively. The DC-bus
b
voltage controller is used in the outer loop to achieve the
Fig. 10 Measured results of three-phase voltage and line current. amplitude of line-current command. An hysteresis current
a Balanced AC mains voltages; vsa, vsb, vsc 100 V/div.; isa, isb, isc 20 controller is used in the inner loop to track the line-current
A/div.; time 10 ms/div. command. The simulation and experimental results show
b Unbalanced AC mains voltages; vsa, vsb, vsc 50 V/div.; isa, isb, isc 10 good line-current waveforms with nearly unity power factor
A/div.; time 4 ms/div. and low current harmonics.

isa isb isc 6 References

iso
Fig. 11 Measured three-phase current and line neutral current
before and after PWM operation
isa, isb, isc, iso 5 A/div.; time 20 ms/div.
10 Nabae, A., Takahashi, I., and Akagi, H.: ‘A new neutral-point
the DC-link voltage due to load change is about three cycles
of line frequency. Based on the adopted control scheme two
11 Lai, J.S., and Peng, F.Z.: ‘Multilevel converters – a new breed
DC-side capacitor voltages are balanced before and after
the load variation.
1 Salmon, J.C.: ‘Techniques for minimising the input current distortion
of current-controlled single-phase boost rectifier’, IEEE Trans. Power
Electron., 1993, 8, (4), pp. 509–520
2 Salmon, J.C.: ‘Circuit topologies for single-phase voltage-
doubler boost rectifier’, IEEE Trans. Power Electron., 1993, 8, (4),
pp. 521–529
3 Manias, S.: ‘Novel full-bridge semicontrolled switch mode rectifier’,
IEE Proc. B, 1991, 138, (5), pp. 252–256
4 Martinez, R., and Enjeti, P.N.: ‘A high-performance single-phase
rectifier with input power factor correction’, IEEE Trans. Power
Electron., 1996, 11, (2), pp. 311–317
5 Wong, C., Mohan, N., and He, J.: ‘Adaptive phase control for
three phase PWM AC to DC converters with constant switching
frequency’. Proc. Conf. PCC-Yokohama, Yokohama, Japan, 1993,
pp. 73–78
6 Kwon, B.-H., and Min, B.-D.: ‘A fully software-controlled PWM
rectifier with current link’, IEEE Trans. Ind. Electron., 1993, 40, (3),
pp. 355–363
7 Dawarde, M.S., Kanetkar, V.R., and Dubey, G.: ‘Three-phase switch-
mode rectifier with hysteresis current control’, IEEE Trans. Power
Electron., 1996, 11, (3), pp. 466–471
8 Itoh, R., Ishizaka, K., and Goromaru, T.: ‘Three-phase voltage-source
converter with controlled DC for the minimisation of filter
capacitance’, IEE Proc.-B, 1990, 137, (5), pp. 327–333
9 Wu, R., Dewan, S.B., and Slemon, G.R.: ‘A PWM AC-DC converter
with fixed switching frequency’, IEEE Trans. Ind. Appl., 1990, 26, (5),
pp. 880–886
clamped PWM inverter’, IEEE Trans. Ind. Appl., 1981, 17, (5),
pp. 518–523
of power converters’, IEEE Trans. Ind. Appl., 1996, 32, (3),
pp. 509–551

492 IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
12 Sinha, G., and Lipo, T.A.: ‘A four-level rectifier-inverter system
for drive applications’, IEEE Ind. Appl. Mag., 1998, 4, (1),
pp. 66–74
13 Lin, B.R., and Yang, T.Y.: ‘Single-phase half-bridge rectifier with
power factor correction’, IEE Proc. – Elect. Power Appl., 2004, 151,
(4), pp. 443–450
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
14 Rodriguez, J., Lai, J.-S., and Peng, F.-Z.: ‘Multilevel inverters: a
survey of topologies, controls and applications’, IEEE Trans. Ind.
Electron., 2002, 49, (4), pp. 724–738
15 Meynard, T.A., Foch, H., Thomas, P., Courault, J., Jakob, R., and
Nahrstaedt, M.: ‘Multicell converters: basic concepts and industry
applications’, IEEE Trans. Ind. Electron., 2002, 49, (5), pp. 955–964
493