Do t h e Designs Work?

Ken Rose Center for Integrated Electronics Rensselaer Polytechnic Institute Troy, New York 12180-3590
(518) 276-2981

Linking theory and practice is a long-standing issue in academic settings. In engineering the balance shifted from practice to theory and is now shifting ba.ck toward practice. The capstone design requirement required by ABET for accreditation illustrates this trend. Requiring students to desi n, however, is dangerous if there is no way of checking wfether, in fact, the designs work. Early experiences teaching a Mead-Conway based VLSI Design course showed me that students could relatively easily lay out a several thousand transistor, full-custom chip. There was, however, no way of assuring whether or not their design would work - unless one happened to notice that one of the polysilicon lines was unconnected, to say nothing of spotting timing problems. This has led to significant modifications and, I believe, improvements in our approach to VLSI design. Interestingly, and not surprisingly, our approach has evolved toward industrial practice. Appropriate CAE software tools are essential for a VLSI design environment. At Rensselaer we have an evolving mix of industrial and home-grown tools. In the basic VLSI Design course we introduce students to a Calma GDS I1 system for layout and Teradyne's LASAR software for logic and timing verification. Initial design projects are based on a catalog of digital standard cells we created which are compatible with MOSIS 3 pm double-level-metal (DLM) CMOS design rules. The use of standard cells as a basis for university design was novel when we began. We find it allows much better checking of design performance. It is very compatible with the use of logic and timing simulators such as LASAR. In the Advanced VLSI Desi n course students learn to use a circuit extractor (MT-IDA7 and simulator (SPICE) to create standard cells. We also introduce behavioral simulation (VHDL) and fault simulation as design aids at the architectural level. Projects may involve standard cell design, continuation of designs initiated in VLSI Design, or new designs. For the past two years, development of a chip for control of communications between computers in an automobile has served as a focus for design activities.

Our philosophy of VLSI Design education is based on four premises. Managing a VLSI Design requires a hierarchical approach. A library of standard cells simplifies and increases design reliability. VLSI Design requires interaction between the designer and a supportive CAE environment. To allow reliable design by inexperienced designers, the CAE environment must assure design correctness. Training inexperienced designers requires providing feedback (including grades) on whether or not their designs work. The CAE tools must provide this feedback at all levels of the design process: layout circuit, logic, and architecture. At the layout level, automatic design rule checking has long been recognized as essential. Automatic circuit extraction is equally essential at the circuit level. At the logic level, logic and timing simulation is essential and fault simulation is helpful, but more tools are required to improve testability. A hierarchical approach to design means that large designs can be handled by teams of designers with personal computer support. This is a useful perspective in a university setting where fled ling designers and personal computers abound. MT-IDA $Microcomputer Terminal Interactive Design Assistant)' is an example of CAE software we have developed to meet these requirements. It runs on IBMcompatible PCs with EGA cards and provides layout entry, design rule checking, circuit extraction, switch model simulation, and exhaustive test pattern generation. It is an aid to the developer of standard cells using the MOSIS 3 pm CMOS DLM design rules for Manhattan geometrics. MT-IDA is currently being revised to improve its user interface, support hierarchical design, and support yield management. Support of hierarchical design will allow us to develop placement and routing for use with standard cells; this is currently a weak link in our design environment. Yield management tools will be based on our circuit extractor and assess the effect of both parametric and catastrophic defects. Other tools are being developed to expand our desi n environment. We have recently developed a MacIntosfbased schematic capture system (MacVIDA) which produces schematic drawings and LASAR wire lists. We are also involved in a research project to create an Object Oriented Computer Aided Design Environment (OOCADE) which will support the VHDL language. SRAhf and PLA generators are being developed in conjunction with this project.

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Our designs have been based on standard cells which we designed. Consequently, we wanted to assure ourselves that our standard cells work the way we thought they did. The recently introduced MOSIS Tiny Cllip with a 2.3 x 3.4 mm* area inside the MOSIS pad frame was a convenient vehicle for testing our cell designs. We designed a Tiny Chip. This chip includes a variety of simple gates, a sevenstage ring oscillator, a 2:l Quad Mux, a D latch, an LSSD latch, a parity generator, and a 4 x 1 SRAM. Apart from problems with the parity generator inputs, all of the cells work as designed. This gives us confidence in using these cells as a basis for larger designs. To summarize, assuring that designs work is a necessary part of design education. To achieve this, Feedback to designers is essential at all levels and stages of the design process. This requires CAE tools which check designs at all levels and stages. Hierarchical, standard cells designs help and can be supported to a large extent by PC-based CAE software. More tool development is needed to support upper levels of the design process, especially design verification and design for testability. In our experience, there is still a great imbalance between design resources and test resources in a university environment.

1. S.-S. Chang, and K. Rose, MT-IDA: a Microprocessor

Terminal Interactive Design Assistant for VLSI Design, 1987 IEEE Workstation Technology and Systems Workshop, pp. 30-33.

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