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All Programmable: from Silicon to System

Ivo Bolsens, Senior Vice President & CTO


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Copyright 2012 Xilinx

Moores Law: The Technology Pipeline

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Industry Debates Variability

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Industry Debates on Cost

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Nothing New: Power Challenge

MultiMulti -Core
Source: Intel Page 5

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Nothing New: Productivity Gap

Source: SEMATECH Page 6

ESL Design Flow IP Re Re-Use


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Nothing New: I/O Bandwidth Gap

Multi-Gigabit MultiSerDes
Source: Xilinx, Inc. Page 7

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Doubt is not an agreeable condition, but certainty is absurd.


Franois-Marie Arouet de Voltaire, French Philosopher

Photo Source: Wikipedia Page 8

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Dont believe everything you read on the Internet.


Abraham Lincoln, U.S. President

Photo Source: Wikipedia Page 9

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Extending and Leveraging Moores Law

Add Value : Programmable System Integration


Programmability 3D Integration

Collaborate
Supply Chain
Wider more Complexity Deeper earlier Engagement

From System to Silicon

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Value of Programmability: Configurability

Partial Reconfiguration
Time-multiplexing hardware

Lower Power

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Value of Programmability: I/O


28.05Gb/s

SFP+ Test Board

13.1Gb/s

Quad B Ch 1 TX Quad A Ch 1 RX Quad A Ch 0/1/2/3 TX Quad B Ch 0/2/3 TX

Optical

12.5 Gb/s

Backplane

Quad B Ch 0/1/2/3 RX Quad A Ch 0/2/3 RX


6.6Gb/s

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Value of Programmability: GOPS/Watt

ARM CoreSight Multi-core & Trace Debug NEON/FPU Engine Cortex-A9 MP Core 32/32 KB I/D Caches 512 KB L2 Cache Timers / Counters General Interrupt Controller NEON/FPU Engine Cortex-A9 MP Core 32/32 KB I/D Caches Snoop Control Unit (SCU) 256 KB On-Chip Memory DMA Configuration
s

Interface
ACP m s AXI4 LITE interconnect s s s

m s

AXI_DMA

AXI_DMA

Accelerator
AMBA Switches

Accelerator

From 100 Watt to 2 Watt 10x Performance Acceleration


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Future Challenge: HW + SW co-design


OpenCL

C
Compile / Debug

C-HLS
Accelerator synth

HW-SW Integration
ARM Processor Encryption
Video codec

FPGA Packet Processing Search FFT

A9

A9

Application-Specific Commercial Software Ecosystem

Exploit Parallelism and Heterogeneity


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3D Integration: Add Value

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Value of 3D Integration: Bandwidth/Watt

100x

3D Interconnect

BW / Watt

10x

SerDes & Standard I/O

1x

10x

100x

1,000x

Total Die-to-Die Connections

100x bandwidth/watt advantage over conventional methods

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Value of 3D Integration: Cost/Gate


Big Single Monolithic Die Multiple Small Die Slices

Die Cost

Greater capacity, faster yield ramp

Area
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Value of 3D Integration: Heterogeneous ICs

Logic Memory

PLD

Mixed functions

Memory Analog Processor

Mixed processes

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Value of 3D Integration: Heterogeneous ICs


Highest bandwidth FPGA with 2.78 Tb/s serial connectivity Electrically-isolated 28G transceivers for optimal signal integrity

Homogeneous digital logic


28G Transceivers

Different silicon processes

28G Transceivers

Passive interposer 13G Transceivers


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Noise isolation

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Value of 3D Integration: Lower Power


Silicon Interposer with 28nm FPGA Slices

7 Series Static Power vs. Logic Cells at Tj=85C and Max Process
18.0 16.0

28 nm FPGA Slice 28 nm FPGA Slice 28 nm FPGA Slice 28 nm FPGA Slice

Max Static Power

14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Virtex-7 Monolithic Virtex-7 Multi-Slice

Very Leaky

500

1000

1500

2000

A
Slow

D
Fast

LCs/1000

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3D Integration: Challenges Ahead


Improve Cost
Wafer backside processing is complicated Device quality wafers used for interposers KGD methodologies still emerging

Scalability
Micro-bump scaling is limited Super-sized interposers. Improve TSV aspect ratio

Design Support
Multi-die analysis without Multi-mode Multi-corner explosion Thermal modeling based on vertical hotspots

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3D Integration: Industry Call-to-Action


Design Enablement
Models 3D Process Development Kit

Manufacturing Standards
DFM rules for TSV, -bump Materials TSV, -bump Thermal budget

Test
Test HW Known-good-die method -bump probing Burn-in bare die

Interoperability of Silicon Thin wafer handling Shipping methods Chip-to-chip interfaces

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Supply Chain Collaboration: Early Engagement


Heterogeneous Stacked Silicon Interconnect Technology

Stacked 90nm Process Silicon Integration Interconnect And Modular Development Development Started

90nm Test Vehicle Completed

65nm Test Vehicle Completed

28nm Test Vehicle Completed

Design Tools Available

2006

2007

2008
Design Enablement and Supply Chain Validation

2009

2010

2011

2012

Initial Reliability Assessment

Process Qualification

Design Validation

Worlds First 3D Stacked Silicon Interconnect Device

Today

3D Integration
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Supply Chain Collaboration: Early Engagement

Technology path finder

Integration and basic devices

Basic Circuit blocks, elements: process-design RAM, RF, interactions, Std Cell, etc. pilot prep

More circuit blocks, & later products

28nm starts TV0 TV1 TV2 TV3 TV4 TV5

2008

2009

2010

2011

28nm Process Technology

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Supply Chain Collaboration: Product Ramp Up


FAB
Advanced InIn-Line Inspection

FPGA
Wafer Sort Root Cause Analysis Yield Improvement

Continuous, early feedback loop for initial ramping Enables accelerated learning days vs. months
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Supply Chain Collaboration: Mutual Benefit


FPGA architecture drives yield & quality improvements

The FPGA is a powerful yield learning vehicle with multiple layers of programmable features Defect Reduction: quick to detect defects
If you cant find it, you cant fix it

Process Control: powerful to measure variations


If you cant measure it, you cant improve it

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Supply Chain 1998 - 2010

Test Outside FAB Bump Assy


DB

In-house

Bin

Mark

FG

PP

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Todays Supply Chain


R&D Consortia EDA, Equipment Suppliers
Die Sep

Test
Top die attach Outside
Bin

Mark
Std eFuse1 eFuse2
FG

FAB

Sort

Bump

DB bins

In-house

Chip-on-Die
Top side proc. Bot side proc. Bump

3rd party die

Interposer

I-poser attach Pkg assy

Chip-on-Wafer

PP

Bump Bot side proc.

Top side proc.

Interposer 3rd party die

Die stack

Wider and Deeper


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From Silicon to System

Applications SW

How to monetize SW?

System Company

System Architecture Product Features Product IP/HW/SW Power, performance cost, integration How to ramp yield faster?

FablessVendor
DFM

Package Who controls 3D supply chain? Supplier Wafer

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Conclusions
Moores Law: - From mostly cost reduction to more value-based innovation System figure of merit defines value Xilinx programmable system integration - Programmability - 3D integration Supply chain partnerships to enable - Efficiency - Standardization - Innovation

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What Xilinx Makes Possible:

ALL PROGRAMMABLE
ALL Programmable Electronic Systems ALL Programmable Technologies ALL Programmable Devices

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Follow Xilinx

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youtube.com/XilinxInc

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