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MultiMulti -Core
Source: Intel Page 5
Multi-Gigabit MultiSerDes
Source: Xilinx, Inc. Page 7
Collaborate
Supply Chain
Wider more Complexity Deeper earlier Engagement
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Partial Reconfiguration
Time-multiplexing hardware
Lower Power
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13.1Gb/s
Optical
12.5 Gb/s
Backplane
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ARM CoreSight Multi-core & Trace Debug NEON/FPU Engine Cortex-A9 MP Core 32/32 KB I/D Caches 512 KB L2 Cache Timers / Counters General Interrupt Controller NEON/FPU Engine Cortex-A9 MP Core 32/32 KB I/D Caches Snoop Control Unit (SCU) 256 KB On-Chip Memory DMA Configuration
s
Interface
ACP m s AXI4 LITE interconnect s s s
m s
AXI_DMA
AXI_DMA
Accelerator
AMBA Switches
Accelerator
C
Compile / Debug
C-HLS
Accelerator synth
HW-SW Integration
ARM Processor Encryption
Video codec
A9
A9
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100x
3D Interconnect
BW / Watt
10x
1x
10x
100x
1,000x
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Die Cost
Area
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Logic Memory
PLD
Mixed functions
Mixed processes
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28G Transceivers
Noise isolation
7 Series Static Power vs. Logic Cells at Tj=85C and Max Process
18.0 16.0
14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Virtex-7 Monolithic Virtex-7 Multi-Slice
Very Leaky
500
1000
1500
2000
A
Slow
D
Fast
LCs/1000
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Scalability
Micro-bump scaling is limited Super-sized interposers. Improve TSV aspect ratio
Design Support
Multi-die analysis without Multi-mode Multi-corner explosion Thermal modeling based on vertical hotspots
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Manufacturing Standards
DFM rules for TSV, -bump Materials TSV, -bump Thermal budget
Test
Test HW Known-good-die method -bump probing Burn-in bare die
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Stacked 90nm Process Silicon Integration Interconnect And Modular Development Development Started
2006
2007
2008
Design Enablement and Supply Chain Validation
2009
2010
2011
2012
Process Qualification
Design Validation
Today
3D Integration
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Basic Circuit blocks, elements: process-design RAM, RF, interactions, Std Cell, etc. pilot prep
2008
2009
2010
2011
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FPGA
Wafer Sort Root Cause Analysis Yield Improvement
Continuous, early feedback loop for initial ramping Enables accelerated learning days vs. months
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The FPGA is a powerful yield learning vehicle with multiple layers of programmable features Defect Reduction: quick to detect defects
If you cant find it, you cant fix it
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In-house
Bin
Mark
FG
PP
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Test
Top die attach Outside
Bin
Mark
Std eFuse1 eFuse2
FG
FAB
Sort
Bump
DB bins
In-house
Chip-on-Die
Top side proc. Bot side proc. Bump
Interposer
Chip-on-Wafer
PP
Die stack
Applications SW
System Company
System Architecture Product Features Product IP/HW/SW Power, performance cost, integration How to ramp yield faster?
FablessVendor
DFM
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Conclusions
Moores Law: - From mostly cost reduction to more value-based innovation System figure of merit defines value Xilinx programmable system integration - Programmability - 3D integration Supply chain partnerships to enable - Efficiency - Standardization - Innovation
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ALL PROGRAMMABLE
ALL Programmable Electronic Systems ALL Programmable Technologies ALL Programmable Devices
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