FPGA Implementation of Embedded

Controller for IC Engine

MTP Presentation
by
R.A.S.Jagadish (05323001)

Under Guidance of
Prof. Kavi Arya
and
Prof. Shashikanth Suryanarayanan

IDP in System and Control Engineering

IIT Bombay, India
July 2007
1
 Outline
z Introduction

z Problem Statement

z Theory

z Experimental Work

z Results and Conclusion

z Future Work

z References
2
What is Embedded System?
z Embedded system composed of Hardware
and Software components are designed to
interact with a physical environment in
real-time in order to fulfill control objectives
and design specifications.

z A system designed to perform a single well

defined function life-long. 3
 Controller
zController is a mechanism that interacts with part of the world (the
“plant”) by measuring certain variables and exerting some influence
in order to steer it toward desirable states.

Timing Diagram

The execution of a control program with a period T4

Engine Controller Unit

z The ECU is essentially a control device

that given information about the status
of an engine can determine what to do
and when to do it.

5
Engine Sensors and Actuators:

ƒInputs to the System

M.A.P Diaphragm-based Manifold Air Pressure
sensor
Crank Shaft Variable Reluctance ( Inductive
Coupling) sensor

ƒOutputs of system
Spark Ignition To give the signal to ignition driver
Driver relative to the crank position
Fuel Injection To give the signal to fuel injection driver
driver relative to the crank position
6
Problems

z Identify 45 BTDC from crank position sensor

using Hardware
z Calculation of Engine Speed (RPM)
z Spark Advance Table (Using interpolator)
z Ignition Time Calculation
(Ignition Driver)
z Fault detection
z Operate in Synchrony

7
Block Diagram of EMS

Manifold Air
Pressure (MAP)
Sensor

IC
Fuel Injector Engine FPGA
Board
with ADC/DAC
Crank
Fuel Position
Pump Sensor
Spark
Ignition
Driver
DRIVER
INPUT
(On/Off)

8
Digital Controller (2nd order)

b0 + b1 z −1 + b2 z −2 Y ( z )
C ( z) = −1 −2
=
1 + a1 z + a2 z X ( z)

Y ( z )(1 + a1 z −1 + a2 z −2 ) = X ( z )(b0 + b1 z −1 + b2 z −2 )
y (n) = − a1 y (n − 1) − a2 y (n − 2) + b0 x(n) + b1 x(n − 1) + b2 x(n − 2)

9
 Implementation of Discrete time Controller

−1
b0 + b1 z + ... Y ( z)
C ( z) = −1 −2
=
1 − a1 z − a2 z − ... U ( z )
Y ( z )(1 − a1 z −1 − a2 z −2 − ...) = U ( z )(b0u (k ) + b1 z −1 + ...)
y (k ) = a1 y (k − 1) + a2 y (k − 2) + ... + b0u (k ) + b1u (k − 1) + ...

Algorithm :

1.Read u(k)
2.Calculate y(k) = bo*u(k) + history
3.Output y(k)
4.Calculate history for the next cycle
10
 What is FPGA

z The innovative development of FPGAs whose configuration could

be re-programmed an unlimited number of times

z a new field in which many different hardware algorithms could

execute

z on a single device, just as many different software algorithms can

run on a conventional processor.

z The speed advantage of direct hardware execution on the FPGA –

routinely 10X to 100X the equivalent software algorithm

z FPGA can be configured to contain exactly and only those

operations that appear in the algorithm.
 FPGA Architecture

P RO GRAM M I/O BLO CK

ABLE
IN T ERCO N N E
CT

C O N F IG U R A B LE LO G IC B LO CK ( CLB)
So u r c e : X ilin x

Field Programmable Gate Array (FPGA) devices feature a

reconfigurable digital circuit architecture with a matrix of Configurable
Logic Blocks (CLBs) surrounded by a periphery of I/O Blocks.
Signals can be routed within the FPGA matrix in any arbitrary manner by
Programmable Interconnect switches and wire routes.
Using a Von-Neumann M/C for Computing

1. Algorithmic Description : Using High level

programming Languages
2. Compilation : Extracting local parallel,
resource usage optimization.
Generate the final program to be executed.
3. Execution - Execute the program on
processor
An Alternative path : The FPGA

- An array of Programmable logic gates

-programmable interconnect
Which allows the direct-mapping of an
arbitrary logic circuit.
wire to wire, Logic gate to logic gate
Using FPGA for Computing

z Express the algorithm as a logic circuits.

-Need good tools to convert high level algorithm
descriptions to logic circuit equivalents.

z Map the circuit to the FPGA - synthesis, placement

and routing problems need to be solved.
Stimulate the mapped circuit in real time to execute
the algorithm.

program + circuit = circuit

Capability Comparison

FPGA & Von-Neumann processors are equivalent

- Because Von-Neumann process is a logic circuit
- Because a logic circuit can be simulated by a Von-
Neumann processor.
Thus the FPGA or Von-Neumann processor decision
is driven by "Optimality" Criteria
-Size of problem
-Performance requirements
-Cost/Energy budget
 Advantages of Von-Neumann Processor

1. Highly optimized data paths

which are heavily utilized
2. Easy to scale to large problem by using
more memory
3. Well understood, optimized computation flow
4. Multi-processing on a chip promises
unlimited performance scaling
 Drawbacks of Von-Neumann
1. Communication between operation is often expensive
i.e implemented through memory
energy/delay inefficient.
2. Difficult to exploit parallelism
- Pipeline is effective, but not scalable beyond a limit.
Overloads of instruction fetching/decoding
- Memory bottlenecks
- Fixed memory architecture
( Caching methods, Interleaving Memory)
Fixed nature of architecture
 Advantages of FPGAs

1. Circuits can be customized to the algorithm eg.

Choice of operations, storage architecture
2. Direct communication is possible
Parallelism can be exploited to "an arbitrary
degree"
- provided that the algorithm has it and enough
recourses available.
3. Flexible memory architecture
 But some draw backs

z Area Efficiency is poor

- Programmable logic & interconnect occupy
more space
z Delay efficiency is poor
- Delay of a programmable gate/ wire is
higher.
z Unpredictable wire delays
- Due to unfavorable placement
Where can the FPGA fit?

In highly parallel problems with bit-level

operations
In signal processing problems
To overcome memory bottle necks
For energy efficiency
Challenges in system design

z Multiple levels of abstraction: logic to

CPUs.
z Multiple
and conflicting constraints: low
cost and high performance
z Short design time: Late products are
often irrelevant.
The system design process

z Part of larger product design.

z Major levels of abstraction:
– specification;
– architecture;
FPGA-based system design
– logic design;
– circuit design;
– layout.
Dealing with complexity

z Divide-and-conquer: limit the number of

components we deal with at any one time.
z Group several components into larger
components:
– transistors form gates;
– gates form functional units;
– functional units form processing elements;
– etc.
Levels of abstraction

z Specification: function, cost, etc.

z Architecture: large blocks.
z Logic: gates + registers.
z Circuits: transistor sizes for speed,
power.
z Layout: determines parasitics.
 Design abstractions

English specification
Executable Throughput,
program
behavior design time
register- Function units,
function Sequential clock cycles cost
transfer
machines
Literals,
Logic gates logic logic depth

transistors circuit nanoseconds

rectangles layout microns

Why do we care about layout?

z Need not design layout.

z Layout determines:
– Logic delay.
– Interconnect delay.
– Energy consumption.
z Need
to understand sources of
FPGA characteristics.
FPGA
Design
Flow
Block Diagram of A/F injection controller
FPGA Based controller Implementation

30
 Controller Building Block in System generator

Fs = 1;
data_width = 12;
1 − 1.6929 z −1 + z −2 Y ( z) b0 = 1;
data_binary_pt = 11;
C ( z) = −1 −2
=
1 + 1.2591z + 0.825 z
b1 = -1.6929;
coef_width = 12; X ( z) b2 = 1;
coef_binary_pt = 10;
31
a1 = 1.2591;
Step Responses

ƒMatlab simulation

ƒXilinx System Generator

Simulation
 Comparison of Frequency Responces
For Stepped Sine wave input
z Peak error : 6.8738e-2 units
z Error Variance : 2.0988e-3 units

Actual Transfer Function FPGA transfer function

in simulink using system generator33
 Input Signal to the controller

Sensor signal from Inductive coupling

Sparking (before TDC)

TDC
5V

0v

45 BTDC 45 BTDC BDC

 Approach To Design

For Hardware Synthesis Approach

Brain Body

Path

ƒConditional Signals/ Data dependency signals Eg : over_flow, err

ƒControl Signals Eg: enable_timer, load_counter

35
 Main Blocks for Spark Ignition control (open loop)
Top level View
Ignition puls
width
Inductive
couple Edge detectors
sensor o/p
and 45 BTDC Ignition time Ignition signal
Measuring time detector calculation duration
of inductive sensor calculation

Signal to
Positive level count
Ignition
RPS Look up Table Spark Actuator
Time to frequency RPS vs Spark advanceConverts spark
converter Advance advance
angle In clocks

Negative level count

36
System Decomposition

z Decompose the System into Modules

z Further decompose the each module in
to Data path and Control path

Advantages
1. IP reusable
2. Scalable / Generic
3. Easy to Debug / Verification
37
Spark Ignition System Decomposition

z Synchronizer ( 45 BTDC finder)

Counts no. pulses in terms of high frequency clock
z Interpolator
Relation between the RPM and spark advance angel
z Ignition Driver
To calculate Time of Ignition and Duration of
Ignition

38
 Synchronizer Data Path Synthesis

Counter Register

Generated from VHDL code in Xilinx Integrated Simulation Environment

39
 Control Path for Synchronizer

Inputs
Outputs
Sensor1
Count_enable
Count_overflow
Reg_enable
Clk
Counter_reset
Reset
40
Reg_reset
State Diagram for Ignition Driver

41
 How to Find RPM?

0v

45 BTDC 45 BTDC BDC

f = 20MHz If count = 1000
t = 50 nsec
1 rev = 1000 clocks Accuracy
1 rev = 50 ms For 360 degrees 1000 clocks
? = 60 sec 1 degree = 2.5 clocks
1200 RPM
As the frequency increases accuracy increases
 Modified Block Diagram (Data Path)

FF counter Interpolater
Ignitio
sensor1 signal

adder
Driver

FF adjustment
counter

43
Plot between RPM vs. Spark advance

Matching 96.64%

Where x is rpm
 Some Issues in Implementing
z When inferring hardware from HDL, it is important to
keep in mind the type of hardware you want.
Ex. On the same signal we can’t detect both edges
--*as the CoolRunner-II FPGA is the only device that has dual-edge
triggered flip-flops.

z How to communicate between two different state

diagrams?
Sol : Include wait states in both state diagrams on condition of other
state.
z Setup and hold timing requirements to be satisfied

Ref: http://support.xilinx.com/support/software_manuals.htm45
Reset State
z Basically reset is to initialization
- To bring the system to a known state

- Although reset is asynchronous signal it should be released

synchronously
Q To ckt1

reset

Q To ckt2

clock
Fail-safe ECU System using Dynamic Reconfiguration

z When the system has many real-time

controllers
z There is a demand for improved circuit
reliability
z The fail-safe system is defined as
-To allow functional degradation after a
fault, but it prevents the system from
suffering fatal problems. 47
ECU Under Normal Operations

48
ECU in case of a fault engine controller

49
Watch Dog Timers Architecture

Input 1

Input 2

50
Design validation

z Checked at every step that errors

haven’t been introduced-the longer an
error remains, the more expensive it
becomes to remove it.
z Forward checking: compared results of
less- and more-abstract stages.
 Results

Simulation Results of Level ‘1’ and level ‘0’ counter

52
Simulation results of 45BTDC detector

53
Synchronizer Control Path in Xilinx ISE Synthesis
tool for Spartan 3 (XC3S200FT256) board

54
Synchronizer Data Path in Xilinx ISE Synthesis
tool for Spartan 3 (XC3S200FT256) board

55
Conclusion

z Second order controller implemented using direct

form 1, simulated and verified in Matlab

z 45 BTDC Detector, Ignition time calculator simulated,

functionally verified and synthesized

z Proposed Fail-safe ECU architecture using Dynamic

Reconfiguration FPGA
Future Work

z Integration of all blocks and Synthesis

z Timing Verification of controller
z Testing on the IC engine
z Implementation of Fail safe controller using
dynamic reconfigurable FPGA
z Test the over all controller on the IC engine
z Variable Valve Timing (VVT) controller
z Knock detection algorithm implementation
using Fuzzy logic
z Transmission Control system, A/C control 57

z Hybrid vehicle control system

Bibliography

1. Clive Max Maxfield “Design Warrior’s guide to FPGA”

, Elsevier publications 2004.
2. Allan W. M. Bonnick, “Automotive Computer
Controlled Systems” 2001.
3. William B. Ribbens, “Understanding Automotive
Electronics” Fifth Edition 1998.
4. CARROLL DASE, JEANNIE SULLIVAN FALCON,
and BRIAN MACCLEERY “Motorcycle Control
Prototyping Using an FPGA-Based Embedded Control
System” OCTOBER 2006 IEEE CONTROL
SYSTEMS MAGAZINE.
5. A. Çebi, L. Güvenç At all, “A Low Cost, Portable
Engine Electronic Control Unit Hardware-in-the-Loop
Test System”, IEEE ICSE June 2005.
58
Thank You

Questions?

Suggestions?

59
 Conversion floating math to fixed point

C N = 1.4 RN − 1.12 RN −1 + 1.6CN −1 − 0.6CN − 2

In order to represent 1.4 or 1.12, we must scale integers and
use fixed-point math
Since these constants less than 2 (most of z-functions consts.)
Scale maximum value of the μP constant to 2. if 16-bit

Division can be executed with a shift right of 14 places.

To accelerate execution, we can also shift it left 2 places and take the most significant word