Outline

Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults
Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults

ECE-470 Digital Design II Fault Modeling

Summary
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Motivation for Modeling

Models are often easier to work with Models are portable Models can be used for simulation, thus avoiding expensive hardware/actual circuit implementation Nearly all engineering systems are studied using models All the above apply for logic as well as for fault modeling
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Defect, Fault, Error

Defect: in an electronic system, is the unintended difference between the implemented hardware and its intended design Fault: a representation of a defect at the abstracted functional level Error: a wrong output signal produced by a defective system; is an effect whose cause is some defect
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Why Model Faults?

Real defects - often mechanical - too numerous and often not analyzable (see next slide) A fault model makes analysis possible: fault analysis becomes a logical rather than physical A fault model identifies targets for testing
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Some Real Defects in Chips

Processing defects
Missing contacts Parasitic transistors Oxide breakdown ...

Material defects

Time-dependent failures Packaging failures

Contact degradation Seal leaks ... Dielectric breakdown Electromigration ...

Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) ...

Common Fault Models

Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (pp. 60-70) of the book
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Single Stuck-at Fault: Overview

Single stuck-at faults Multiple stuck-at faults Fault detection: combinational, sequential Fault equivalence Fault dominance and checkpoint theorem
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Single Stuck-at Fault

Three properties define a single stuck-at fault
Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate

Single Stuck-at Fault

How effective is this model?
Empirical evidence supports the use of this model (justified by the frequent testing strategy) Has been found to be effective to detect other types of faults Easy to use
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Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults
Faulty circuit value Good circuit value 0/1 1/0 z 1 k c 1 0 a b d e f Test vector for h s-a-0 fault

s-a-0
g 1 h i

Multiple Stuck-at Fault

A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1 A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare Statistically, single fault tests cover a very large number of multiple faults
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Example: Masking Among Multiple Faults

a 0 b 1 c 1 s-a-1 f d e s-a-0 1 1

g 0

Test vector 011 detects c s-a-0 If a s-a-1 as a second fault, the test vector 011 does not detect c s-a-0 anymore
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Fault Detection: Combinational Circuits

A test (vector) t detects a fault f iff Zf(t) Z(t)
c 1 0 a b d e g 1 f k j h h i 1 j 0 1

Two Basic Concepts

Test t detects a fault f by:
Activate f: generate an error by creating different value on the fault site/line Propagate the error to a PO: all values along at least a path from fault site to PO have different values from the good circuit (lines along such path are called sensitized to the fault f by the test t)
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s-a-0
1 0

1 0

zf

Test vector t for h s-a-0 fault

Example: Path Sensitization

0 x2 0 x3 1 x1 G1 G3 G2 0/1 x s-a-1 G4 G5 0/1 0/1

Detectability
Fault f is detectable is there exists a test t that detects f. For an undetectable fault f, Zf(t) = Z(t) and no test can simultaneously activate f and create a sensitized path to a PO A detectable fault may become undetectable due to the presence of another fault Complete detection test-set: detects every detectable fault Fault detectability is related to redundancy
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x4

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Example: Undetectable fault

A B s-a-1 x D C

Fault Detection: Sequential Circuits

More difficult compared to combinational circuits: a test sequence is typically required Test-sequence T strongly detects the fault f iff the output sequences R(q, T) and Rf (qf , T) are different for every possible pair of initial-states q and qf. Test-sequence T detects the fault f iff the output sequences R(q, T) and Rf (qf , T) are different for some ti T, for every possible pair of initialstates q and qf.
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Two Step Approach

Step 1: Initialization sequence TI; brings the circuits to initial states qI and qIf Step 2: Apply sequence T; R(qI , T) and Rf(qIf , T) are predictable now; ti is the first vector for which an error is observed at POs

Fault Equivalence: Combinational Circuits

Two faults f and g are said to be functionally equivalent iff , Zf(x) = Zg(x) Functional equivalence partitions the set of all faults in equivalence classes A test t is said to distinguish between two faults f and g if Zf(t) Zg(t). For a single-output circuit, the set of all tests that distinguish f and g includes all solutions of: Zf(t) XOR Zg(t) = 1
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Equivalence Fault Collapsing

Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches) Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset
sa0 sa1 AND sa0 sa1

Equivalence Rules
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NOT sa1 sa0 sa1 NAND sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NOR sa0 sa1 sa0 sa1 FANOUT
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sa0 sa1 WIRE

OR

sa0 sa1

sa1 sa0

sa0 sa1 sa0 sa1

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Equivalence Example: Reconvergent Fanout

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

Example: No Fanout
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

Faults in red removed by equivalence collapsing

sa0 sa1 sa0 sa1 sa0 sa1

20 Collapse ratio = ----- = 0.625 32

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Collapse ratio = ?
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Fault Dominance
If all tests of some fault g detect another fault f, then f is said to dominate g Dominance fault collapsing: If fault f dominates g, then f is removed from the fault list When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set If two faults dominate each other then they are equivalent
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Example: Fault Dominance

All tests of f g s-a-1 f s-a-1
000 001 010 011 100 101 110

Only test of g

s-a-1 s-a-1 s-a-1 s-a-0

A dominance and equivalence collapsed fault set

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Example: Dominance Fault Collapsing

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 15 Collapse ratio = ----- = 0.47 32
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Checkpoints
Primary inputs and fanout branches of a combinational circuit are called checkpoints Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit
Total fault sites = 16 Checkpoints ( ) = 10

Faults in red removed by dominance collapsing

Faults in blue removed by equivalence collapsing

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1

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Summary
Fault models are analyzable approximations of defects and are essential for a test methodology For digital logic, single stuck-at fault model offers best advantage of tools and experience Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests Memory and analog circuits need other specialized fault models and tests
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Age Defects: Electromigration

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