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Counters:
Ripple Counters Synchronous Counters Counter Applications EECC341 - Shaaban
#1 Lec # 18 Winter 2001 2-13-2002
Registers
An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits.
74LS175
1D
D CLR Q Q
2D
D CLR
Q Q
3D
D CLR
Q Q
4D
CLK /CLR
D CLR
Q Q
EECC341 - Shaaban
#2 Lec # 18 Winter 2001 2-13-2002
Shift Registers
Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle)
Shift Left is towards MSB
Q3 Q2 Q1 Q0 0 1 1 1 LSI Q3 Q2 Q1 Q0 1 1 1 LSI
EECC341 - Shaaban
#3 Lec # 18 Winter 2001 2-13-2002
SRG n > SI SO
D CLK
For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 serout: - - - - 1 0 1 1 0 0 clock:
SEROUT
D CLK
EECC341 - Shaaban
#4 Lec # 18 Winter 2001 2-13-2002
1Q
> SI
D CLK
2Q
1Q 2Q nQ
(SO)
nQ
Serial to Parallel Converter 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 101100111 2Q: - - 10110011 3Q: - - - 1011001 4Q: - - - - 101100 clock:
D CLK
EECC341 - Shaaban
#5 Lec # 18 Winter 2001 2-13-2002
SERIN 1D
S L S
1Q
D CLK Q
2Q
D CLK Q
2D
Parallel to Serial Converter Load/Shift=1 Di Qi Load/Shift=0 Qi Qi+1
S L
D
NQ
Q CLK
SEROUT
ND
EECC341 - Shaaban
#6 Lec # 18 Winter 2001 2-13-2002
SERIN 1D
S L S
D CLK
1Q
D CLK
2Q
2D
NQ
CLK
EECC341 - Shaaban
#7 Lec # 18 Winter 2001 2-13-2002
10 9
74x194
7 6 5 4 3 2
R
QD QC QB QA
4-bit Bi-directional Universal (4-bit) PIPO Function Hold Shift right/up Shift left/down Load Mode S1 S0 0 0 0 1 1 0 1 1 Next state QA* QB* QC* QA QB QC RIN QA QB QB QC QD A B C QD* QD QC LIN D
EECC341 - Shaaban
#8 Lec # 18 Winter 2001 2-13-2002
(11) (1) S1 S0
74x194
RIGHT LEFT
(7) 10
SL HO
00 (12)
(6)
LD
11
Q CLK
QD
SR
01
CLR
(10)
S1
10 (9)
S0
00 (3)
D
11
Q CLK
(15)
QA
A
(2)
RIN
01
CLR
Universal SR Circuit
EECC341 - Shaaban
#9 Lec # 18 Winter 2001 2-13-2002
EECC341 - Shaaban
#10 Lec # 18 Winter 2001 2-13-2002
Receiver
Serial DATA
One bit
Serial-toparallel converter
EECC341 - Shaaban
#11 Lec # 18 Winter 2001 2-13-2002
y7 7 >
y6 6
y5 5
Cin
CLK CLR
A FA Cout
CLEAR_C V
EECC341 - Shaaban
#12 Lec # 18 Winter 2001 2-13-2002
Counters
Clocked sequential circuit with single-cycle state diagram
Modulo-m counter = divide-by-m counter
S1
Sm
S2
S3
Most Common:
EECC341 - Shaaban
#14 Lec # 18 Winter 2001 2-13-2002
CLK
1
Q0 Q1
Q2
0 1 2 3
EECC341 - Shaaban
#15 Lec # 18 Winter 2001 2-13-2002
CLK
1
Q0 Q1
Q2 7
Should be 0
EECC341 - Shaaban
#16 Lec # 18 Winter 2001 2-13-2002
Synchronous Counters
All clock inputs connected to common CLK signal All flip-flop outputs change simultaneously tCQ after CLK Faster than ripple counters More complex logic Most frequently used type of counter
EECC341 - Shaaban
#17 Lec # 18 Winter 2001 2-13-2002
Q0
Flip-flops enabled when all lower flip-flops = 1. Enable propagates serially limits speed Requires (n-1) t < TCLK All outputs change simultaneously tCQ after CLK
CLK
EN >T
Q1
EN >T
Q2
EN >T
Q3
EECC341 - Shaaban
#18 Lec # 18 Winter 2001 2-13-2002
Q0
Q1
Q2
Q3
EECC341 - Shaaban
#19 Lec # 18 Winter 2001 2-13-2002
QA QB QC QD RCO
LSB MSB RCO = Ripple Carry Out, when Count = 1111 and ENT =1
EECC341 - Shaaban
#20 Lec # 18 Winter 2001 2-13-2002
Current State QD QC QB QA
X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
EECC341 - Shaaban
#21 Lec # 18 Winter 2001 2-13-2002
UP/DN = 1 = up RCO = 15 UP/DN = 0 = down RCO = 0 up down up Ex: 0,1,2, 1,0,15,14, 15,0,1,2 RCO RCO
QA QB QC QD RCO
EECC341 - Shaaban
#22 Lec # 18 Winter 2001 2-13-2002
Counter Applications
Count the number of times an event takes place Control the number of steps in a sequence of fixed actions (a sequencer) Generate timing signals (frequency divider, etc.)
ENTER CLK EXIT UP > DOWN COUNTER CTR DIV 6 EN # of spaces Comparator < = Decoder 0 1 2 3 1 4 2 5 4 6 7 CLR_R IN_A IN_B EXE EXE OUT_C
Lot Open
Lot Full
>
EECC341 - Shaaban
#23 Lec # 18 Winter 2001 2-13-2002