Registers & Counters

Registers. Shift Registers:

Serial in, serial out shift register Serial in, parallel out shift register Parallel in, serial out shift register Parallel in, parallel out shift register Shift Register Applications

Counters:
Ripple Counters Synchronous Counters Counter Applications EECC341 - Shaaban
#1 Lec # 18 Winter 2001 2-13-2002

Registers
An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits.
74LS175
1D
D CLR Q Q

1Q /1Q 2Q /2Q 3Q /3Q 4Q /4Q

Example: 74LS175 4-bit register

74LS175
CLK CLR 1D 2D 3D 4D 1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q

2D

D CLR

Q Q

3D

D CLR

Q Q

4D
CLK /CLR

D CLR

Q Q

EECC341 - Shaaban
#2 Lec # 18 Winter 2001 2-13-2002

Shift Registers
Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle)
Shift Left is towards MSB
Q3 Q2 Q1 Q0 0 1 1 1 LSI Q3 Q2 Q1 Q0 1 1 1 LSI

Shift Right (or Shift Up) is towards MSB

Q3 Q2 Q1 Q0 RSI 0 1 1 1 Q3 Q2 Q1 Q0 RSI 0 1 1

EECC341 - Shaaban
#3 Lec # 18 Winter 2001 2-13-2002

Serial In, Serial Out Shift Register

SERIN CLOCK
D CLK Q

SRG n > SI SO

D CLK

For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 serout: - - - - 1 0 1 1 0 0 clock:

SEROUT

D CLK

EECC341 - Shaaban
#4 Lec # 18 Winter 2001 2-13-2002

Serial In, Parallel Out Shift register

SRG n SERIN CLOCK
D CLK Q

1Q

> SI

D CLK

2Q

1Q 2Q nQ

(SO)

nQ

Serial to Parallel Converter 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 101100111 2Q: - - 10110011 3Q: - - - 1011001 4Q: - - - - 101100 clock:

D CLK

EECC341 - Shaaban
#5 Lec # 18 Winter 2001 2-13-2002

Parallel In, Serial Out Shift Register

CLOCK
LOAD/SHIFT

SERIN 1D

S L S

1Q
D CLK Q

2Q
D CLK Q

2D
Parallel to Serial Converter Load/Shift=1 Di Qi Load/Shift=0 Qi Qi+1

S L
D

NQ
Q CLK

SEROUT

ND

EECC341 - Shaaban
#6 Lec # 18 Winter 2001 2-13-2002

Parallel In, Parallel Out Shift Register

CLOCK
LOAD/SHIFT

SERIN 1D

S L S

D CLK

1Q

D CLK

2Q

2D

General Purpose: Makes any kind of (left) shift register S ND L

NQ

CLK

EECC341 - Shaaban
#7 Lec # 18 Winter 2001 2-13-2002

Bi-directional Universal Shift Registers

11 1

Modes: Hold Load Shift Right Shift Left

10 9

CLK CLR S1 S0 LIN D C B A RIN

12 13 14 15

74x194

7 6 5 4 3 2

R
QD QC QB QA

4-bit Bi-directional Universal (4-bit) PIPO Function Hold Shift right/up Shift left/down Load Mode S1 S0 0 0 0 1 1 0 1 1 Next state QA* QB* QC* QA QB QC RIN QA QB QB QC QD A B C QD* QD QC LIN D

EECC341 - Shaaban
#8 Lec # 18 Winter 2001 2-13-2002

CLK /CLR LIN

(11) (1) S1 S0

74x194
RIGHT LEFT

(7) 10

SL HO
00 (12)

(6)

LD
11

Q CLK

QD

SR
01

CLR

(10)

S1
10 (9)

S0
00 (3)

D
11

Q CLK

(15)

QA

A
(2)

RIN

01

CLR

Universal SR Circuit
EECC341 - Shaaban
#9 Lec # 18 Winter 2001 2-13-2002

Shift Register Applications

State Registers
Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position (i.e. a finite memory machine) Very effective for sequence detectors

Serial Interconnection of Systems

keep interconnection cost low with serial interconnect

Bit Serial Operations

Bit serial operations can be performed quickly through device iteration Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc). A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

EECC341 - Shaaban
#10 Lec # 18 Winter 2001 2-13-2002

Shift Register Applications:

Serial Interconnection of Systems

Transmitter

CLOCK Control Circuits /SYNC Control Circuits

Receiver

Parallel Data from ParallelA-to-D converter to-serial converter

Serial DATA
One bit

Serial-toparallel converter

Parallel Data to D-to-A converter

EECC341 - Shaaban
#11 Lec # 18 Winter 2001 2-13-2002

Shift Register Applications Example:

8-Bit Serial Adder

x7 CTL CLK 7 > y0 ... 0 x6 6 x5 5 ... x0 0 Sequential Implementation of: Z[7..0] = X[7..0] + Y[7..0]

y7 7 >

y6 6

y5 5

Cin

CLK CLR

A FA Cout

B S > z7 z6 z5 ... z0 7 6 5 ... 0

CLEAR_C V

EECC341 - Shaaban
#12 Lec # 18 Winter 2001 2-13-2002

Counters
Clocked sequential circuit with single-cycle state diagram
Modulo-m counter = divide-by-m counter
S1

Sm

S2

S3

Most Common:

n-bit binary counter, where m = 2n n flip-flops, counts 0 2n-1

EECC341 - Shaaban
#13 Lec # 18 Winter 2001 2-13-2002

4-bit Ripple Counter

Q CLK T Q Q T Q Q T Q Q T Q Q3 4 bit divide-by-16 Q2 3 bit divide-by-8 Q1 2 bit divide-by-4 Uses Minimal Logic Q0 1 bit divide-by-2

EECC341 - Shaaban
#14 Lec # 18 Winter 2001 2-13-2002

Ripple Counter Timing

CLK
1

Q0 Q1

Q2
0 1 2 3

EECC341 - Shaaban
#15 Lec # 18 Winter 2001 2-13-2002

Ripple Counter Problem

n TCQ for MSB change for n-bit ripple counter => minimum clk period

CLK
1

Q0 Q1

Q2 7

Should be 0

EECC341 - Shaaban
#16 Lec # 18 Winter 2001 2-13-2002

Synchronous Counters
All clock inputs connected to common CLK signal All flip-flop outputs change simultaneously tCQ after CLK Faster than ripple counters More complex logic Most frequently used type of counter

EECC341 - Shaaban
#17 Lec # 18 Winter 2001 2-13-2002

Synchronous Serial Counter

CNTEN EN >T
t

Q0

Flip-flops enabled when all lower flip-flops = 1. Enable propagates serially limits speed Requires (n-1) t < TCLK All outputs change simultaneously tCQ after CLK

CLK

EN >T

Q1

EN >T

Q2

EN >T

Q3

EECC341 - Shaaban
#18 Lec # 18 Winter 2001 2-13-2002

Synchronous Parallel Counter

CNTEN CLK
Single-level enable logic per flip-flop Fastest and most complex type of counter Requires t < TCLK All outputs change simultaneously tCQ after CLK

EN >T EN >T EN >T EN >T

Q0

Q1

Q2

Q3

EECC341 - Shaaban
#19 Lec # 18 Winter 2001 2-13-2002

74X163 4-bit Synchronous Parallel Counter

74X163
Common Clock Synchronous Clear Synchronous Load Count Enable = ENP ENT Load Data Inputs
>CLK CLR LD ENP ENT A B C D

QA QB QC QD RCO

LSB MSB RCO = Ripple Carry Out, when Count = 1111 and ENT =1

EECC341 - Shaaban
#20 Lec # 18 Winter 2001 2-13-2002

74X163 State Table

Inputs /CLR /LD ENT ENP
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Clear Load Hold Hold Count . . .

Current State QD QC QB QA
X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Next State QD* QC* QB* QA*

0 D QD QD 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 C QC QC 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 B QB QB 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A QA QA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

EECC341 - Shaaban
#21 Lec # 18 Winter 2001 2-13-2002

74X169 Up/Down Counter

74X169
>CLK UP/DN LD ENP ENT A B C D

UP/DN = 1 = up RCO = 15 UP/DN = 0 = down RCO = 0 up down up Ex: 0,1,2, 1,0,15,14, 15,0,1,2 RCO RCO

QA QB QC QD RCO

EECC341 - Shaaban
#22 Lec # 18 Winter 2001 2-13-2002

Counter Applications
Count the number of times an event takes place Control the number of steps in a sequence of fixed actions (a sequencer) Generate timing signals (frequency divider, etc.)
ENTER CLK EXIT UP > DOWN COUNTER CTR DIV 6 EN # of spaces Comparator < = Decoder 0 1 2 3 1 4 2 5 4 6 7 CLR_R IN_A IN_B EXE EXE OUT_C

Lot Open

Lot Full

>

EECC341 - Shaaban
#23 Lec # 18 Winter 2001 2-13-2002