CISC Processor Design

Virendra Singh Indian Institute of Science Bangalore

virendra@computer.org

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P Processor A Architecture hit t

Processor Architecture CISC RISC

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Processor Architecture
PI
Controlle r

From memory
Datapath

Control Signals

Status Signals

PO

To memory

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I t Instruction ti Set S t
Instruction Set Should be complete
One should O h ld be b able bl to t construct t t a machine hi level l l program to t evaluate any function

Should be efficient
Frequently required functions can be completed quickly using relatively few instructions

Should be regular
Should contain expected opcodes and addressing modes

Compatible ibl with i h existing i i machines hi

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I t Instruction ti Set S t
Instruction Format
Op-code Op code Operands

Addressing Register Specification Effective Address Implicit Reference

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Micro-coded Implementation
Clock-Phase Generator Control Store Bus Controller State Sequencer Control Word Decoder Controller
Program Counter

Instruction Decoder

Registers
R0 R1 Rn Shifter ALU

Datapath
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PLA Implementation I l t ti
Clock-Phase Generator Bus Controller Instruction Decoder Control Word Decoder Controller
Program Counter

PLA

Registers
R0 R1 Rn Shifter ALU

Datapath
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Random Logic Implementation

Clock-Phase Generator Bus Controller

Random Logic
Controller
Program Counter

Registers
R0 R1 Rn Shifter ALU

Datapath
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Micro-coded Implementation
Clock-Phase Generator
Control Store Instruction Sequencer

Bus Controller
Instruction Decoder
Instruction P f t h Prefetch Register

Encoded Control Word Fields

Control Word Decoder

Decoded Datapath Control

Address Out Reg.

Internal A Bus PC R0 R1 Internal B Bus Rn Shifter ALU

Data Reg.

Datapath

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I t Instruction ti
ADD R1, R1 D2(B2) 5A
0 8

R1
12

B2
16

D2
31

The second operand is added in the first The sum is placed in the first operand location The operand and the sum are treated as 16-bit signed binary integers The first operand is in the register specified by the R1 field The second operand is in the memory address is calculated by adding the displacement specified by the D2 field to the content of the base register specified by the B2 field
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E Execution ti St Steps
Steps for ADD instruction Execution 1. Fetch the first half word 2. Find ADD control word sequence 3. Fetch the remaining g instruction word 4. Calculate the operand address 5 Fetch the operand 5. 6. Add 7. Store the result
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E Execution ti St Steps
1 Fetch 1. F t h the th remaining i i instruction i t ti word d 2. Calculate the operand address 3 Fetch the operand 3. 4. Add 5 Store the result 5. 6. Update the program counter 7 Fetch the first half word for the next instruction 7. 8. Find the address of the next instructions control word sequence 9. Branch to the next instructions control word
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E Execution ti St Steps
1 Fetch the remaining instruction word 1.
One state to second half of the ADD instruction

2. Calculate the operand p address

One state to add D2 displacement and the content of the B2 register

3. Fetch the operand

One state to fetch the data half word (put the address on the pads and wait for the operand half-word)

4. Add
One state to add the operands

5. Store the result

One state to store the result in Register R1
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E Execution ti St Steps
1 Update 1. U d t the th program counter t
One state to increament PC One state to save the incremented value

2. Fetch the first half word for the next instruction

One state to put the PC value on the pads and wait for the first half of the next instruction

3. Find the address of the next instructions control word sequence

One state to put the next instruction into the instruction decoder

4. Branch to the next instructions control word

Zero state this step is accomplished as a part of the previous step
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P Processor - Block Bl k Diagram Di

Clock-Phase Generator Reset & Power-On O Logic Bus Controller Interrupt Logic

Control Store

Next State Control Branch Control unit

IR Decoder

Encoded Control Word Fields

Control Word Decoder

D Decoded d d Datapath D h Control C l

Instruction Prefetch Register

Address g Out Reg.

PC
Datapath

R0

R1

Internal A Bus Internal B Bus

Rn

Shifter

ALU

Data g Reg.
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Thank You
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