Professional Documents
Culture Documents
MC9S12GC Family
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola, Inc., 2002
Revision History
Author
Description of Changes
Original Version. Based on C32 user guide version 01.12 Enhanced PortK description Part number table revision in preface QFP112 Emulation pinout correction Enhanced part number explanation in preface Reduced pseudo STOP current spec. for C64,C96,C128 Enhanced PortAD signal description Corrected VDDR description in 2.4.2 Revised pin leakage in electrical parameters SPI timing parameter table correction Output drive high value reduced in 3V range PE[4:2] Pull-Up spec out of reset changed 3V Expansion bus timing parameters not tested in production Minimum bus frequency specication increased to 0.25MHz. Parameter classication added to Appendix Table C-2. IOH changed to 4mA for 3V range. LVR level dened.for C32. Run IDD changed for C32. Block guide reference table updated Added PCB layout guide for Pierce oscillator conguration IOL parameter updated in 3.3V range Updated PARTID listing due to C128 ECO revision Changed DOC number and CPU DOC reference number Included separate C32 LVI levels Changed PortM pull up reset state to enabled. Added References to the CAN-less GC-Family No major revision number increment, since silicon functionality is not changed. Added VDDX connection in PCB layout gures 8-1.to 8-6 Added Part ID for 2L45J mask set to Part ID table Table A-4 VDD/VDDPLL min when supplied externally now 2.35V Reference S12FTS128K1 in Preface (was S12FTS128K) Reference to CPU Guide corrected to Version2 Corrected ash sector sizes for C-Family devices with >64K Flash Corrected Preface Table 0-1 16K part listing to GC16 without CAN Added PPAGE specications to memory map diagrams Added ash timing parameters for 1024 byte sector size Removed IREG from electrical parameter table Added EXTAL pin voltage spec. to oscillator characteristic table NVM reliability denition of program/erase cycle count corrected. Added note for LVRF when VREG disabled Updated Part ID references in Tables 0-2,0-3,0-4 and 1-3
00.04
15.APR.03 15.APR03
00.05
05.MAY.03 05.MAY.03
00.06
21.MAY.03 21.MAY.03
15.JUL.03
15.JUL03
01.03
27.NOV.03 27.NOV.03
01.04
27.JAN.04 27.JAN.04
01.05
11.FEB.04 11.FEB.04
01.06
07.JUN.04 07.JUN.04
Author
Description of Changes
Removed LVRD from electrical parameter Table B-1. Removed fosc from Table A-4. (Covered in B-11) Adjusted VIL,VIH spec for EXTAL Added further notes to Figure 1-5. Updated NVM data retention electrical parameter table Adjusted minimum VDD voltage in electrical parameter table Added note that external LVR is needed if internal VREG disabled Adjusted VREG output voltage spec. Removed reference to ppm rate in NVM electricals Corrected PortAD I/O function description Updated Part Number Coding tables Added MC9S12GC96 part option Corrected PPAGE Table listing Updated GC16 memory map gure for PPAGE function
08.OCT.04 08.OCT.04
01.10
27.OCT.04 27.OCT.04
Inc.
Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Inc.
2.3.20 PJ[7:6] / KWJ[7:6] Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.21 PM5 / SCK Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.22 PM4 / MOSI Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.23 PM3 / SS Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.24 PM2 / MISO Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.25 PM1 / TXCAN Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.26 PM0 / RXCAN Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.27 PS[3:2] Port S I/O Pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.28 PS1 / TXD Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.29 PS0 / RXD Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.30 PPT[7:5] / IOC[7:5] Port T I/O Pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.31 PT[4:0] / IOC[4:0] / PW[4:0] Port T I/O Pins [4:0] . . . . . . . . . . . . . . . . . . . . . . . 63 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.1 VDDX,VSSX Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . 63 2.4.2 VDDR, VSSR Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 63 2.4.3 VDD1, VDD2, VSS1, VSS2 Internal Logic Power Pins . . . . . . . . . . . . . . . . . . 63 2.4.4 VDDA, VSSA Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 64 2.4.5 VRH, VRL ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.6 VDDPLL, VSSPLL Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 64
Section 8 Recommended Printed Circuit Board Layout Section 9 Clock Reset Generator (CRG) Block Description
9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Section 10 Oscillator (OSC) Block Description Section 11 Timer (TIM) Block Description Section 12 Analog to Digital Converter (ATD) Block Description
12.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.1.1 VRL (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Section 13 Serial Communications Interface (SCI) Block Description Section 14 Serial Peripheral Interface (SPI) Block Description Section 15 Flash Block Description
Freescale Device User Guide 9S12C128DGV1/D V01.10Semiconductor, Section 16 RAM Block Description
Inc.
Section 17 Pulse Width Modulator (PWM) Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module (PIM) Block Description Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Inc.
List of Figures
Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 3-1 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Figure B-5 Figure C-1 Figure C-2 Figure C-3 Figure C-4 Figure C-5 Figure D-1 Figure D-2 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MC9S12C-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MC9S12C128 and MC9S12GC128 User configurable Memory Map . . . . . . 29 MC9S12C96 and MC9S12GC96 User Configurable Memory Map. . . . . . . . 30 MC9S12C64 and MC9S12GC64 User Configurable Memory Map. . . . . . . . 31 MC9S12C32 and MC9S12GC32 User Configurable Memory Map. . . . . . . . 32 MC9S12GC16 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 33 Pin Assignments in 80 QFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . . 52 Pin assignments in 52 LQFP for MC9S12C-Family. . . . . . . . . . . . . . . . . . . . 53 Pin Assignments in 48 LQFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . 54 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Recommended PCB Layout for 48 LQFP Pierce Oscillator . . . . . . . . . . . . . 77 Recommended PCB Layout for 52 LQFP Pierce Oscillator . . . . . . . . . . . . . 78 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . 79 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 96 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 128 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 129
Inc.
Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 130 Figure 19-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no. 841B)133
List of Tables
Table 0-1 List of MC9S12C and MC9S12GC Family members. . . . . . . . . . . . . . . . . . . . 17 Table 0-2 MC9S12C-Family Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 0-3 MC9S12GC-Family Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 0-4 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 1-1 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 $0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) 34 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) 34 $0018 - $0018 Miscellaneous Peripherals (Device User Guide) 35 $0019 - $0019 VREG3V3 (Voltage Regulator) 35 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) 35 $0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) 35 $001A - $001B Miscellaneous Peripherals (Device User Guide) 35 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, 36 Device User Guide) 36 $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) 36 $001F - $001F INT map 2 of 2 (HCS12 Interrupt) 36 $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug) 36 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) 37 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) 37 $0034 - $003F CRG (Clock and Reset Generator) 37 $0040 - $006F TIM (Timer 16 Bit 8 Channels) 38 $0070 - $007F Reserved 40 $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) 40 $00A0 - $00C7 Reserved 41 $00D0 - $00D7 Reserved 42 $00C8 - $00CF SCI (Asynchronous Serial Interface) 42 $00D8 - $00DF SPI (Serial Peripheral Interface) 42 $00E0 - $00FF PWM (Pulse Width Modulator) 43 $0100 - $010F Flash Control Register 44 $0110 - $013F Reserved 45 $0140 - $017F CAN (Motorola Scalable CAN - MSCAN) 45 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 46 $0180 - $023F Reserved 47
Inc.
$0240 - $027F PIM (Port Interface Module) 47 $0280 - $03FF Reserved space 50 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 2-2 MC9S12C-Family Power and Ground Connection Summary . . . . . . . . . . . . . 64 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 5-2 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 6-1 Device Specific Flash PAGE Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 8-1 Recommended External Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table A-7 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table A-8 Supply Current Characteristics for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 93 Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 94 Table B-1 Voltage Regulator Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table B-2 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table B-3 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table B-4 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table B-5 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table B-6 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table B-7 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table B-8 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table B-9 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table B-10 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table B-11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table B-12 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table B-13 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table C-1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table C-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Inc.
Preface
The Device User Guide provides information about the MC9S12C-Family as well the MC9S12GC-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In an effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. The C-Family and the GC-Family offer an extensive range of package, temperature and speed options. The members of the GC-Family do not feature a CAN module.
Table 0-1 shows a feature overview of the MC9S12C and MC9S12GC Family members. Table 0-2 lists the part number coding based on the package, speed and temperature and preliminary die options for the C-Family. Table 0-3 lists the part number coding based on the package, speed and temperature and preliminary die options for the GC-Family.
Inc.
Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C Package Options FU = 80QFP PB = 52LQFP FA = 48LQFP Speed Options 25 = 25MHz bus 16 = 16MHz bus
MC9S12 C32
C FU
25
Speed Option Package Option Temperature Option Device Title Controller Family
Mask1 set
XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S
Temp.
-40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C
Package
48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP
Speed
16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz
Die Type
C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die
Flash
128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 128K 96K 96K 96K 96K 96K 96K 96K 96K 96K 96K
RAM
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K
I/O2,3
31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31
Mask1 set
XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J
Temp.
-40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C
Package
52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP
Speed
25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Die Type
C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die
Flash
96K 96K 96K 96K 96K 96K 96K 96K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K
RAM
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K
I/O2,3
35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60
Inc.
NOTES: 1. XL09S denotes all minor revisions of L09S maskset XL45J denotes all minor revisions of L45J maskset Maskset dependent errata can be accessed at http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp 2. All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8 channel timer. The GC-Family members do not have the CAN module 3. I/O is the sum of ports able to act as digital input or output.
Mask1 set
XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL09S XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J
Temp.
-40C, 85C -40C, 85C -40C, 85C -40C, 105C -40C, 105C -40C, 105C -40C, 125C -40C, 125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C, 105C -40C, 105C -40C, 105C -40C, 125C -40C, 125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C, 105C -40C, 105C -40C, 105C -40C, 125C -40C, 125C -40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C
Package
48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP
Speed
25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Die Type
C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C128 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die
Flash
128K 128K 128K 128K 128K 128K 128K 128K 128K 96K 96K 96K 96K 96K 96K 96K 96K 96K 64K 64K 64K 64K 64K 64K 64K 64K 64K 32K 32K 32K 32K 32K 32K 32K 32K
RAM
4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 2K 2K 2K 2K 2K 2K 2K 2K
I/O2,3
31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35 60 31 35
MC9S12GC128VFA MC9S12GC128VPB MC9S12GC128VFU MC9S12GC128MFA MC9S12GC128MPB MC9S12GC128MFU MC9S12GC96CFA MC9S12GC96CPB MC9S12GC96CFU MC9S12GC96VFA MC9S12GC96VPB MC9S12GC96VFU MC9S12GC96MFA MC9S12GC96MPB MC9S12GC96MFU MC9S12GC64CFA MC9S12GC64CPB MC9S12GC64CFU MC9S12GC64VFA MC9S12GC64VPB MC9S12GC64VFU MC9S12GC64MFA MC9S12GC64MPB MC9S12GC64MFU MC9S12GC32CFA MC9S12GC32CPB MC9S12GC32CFU MC9S12GC32VFA MC9S12GC32VPB MC9S12GC32VFU MC9S12GC32MFA MC9S12GC32MPB
Mask1 set
XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J XL45J
Temp.
-40C, 125C -40C, 85C -40C, 85C -40C, 85C -40C,105C -40C,105C -40C, 105C -40C,125C -40C,125C -40C, 125C
Package
80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP
Speed
25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Die Type
C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die C32 die
Flash
32K 16K 16K 16K 16K 16K 16K 16K 16K 16K
RAM
2K 1K 1K 1K 1K 1K 1K 1K 1K 1K
I/O2,3
60 31 35 60 31 35 60 31 35 60
NOTES: 1. XL09S denotes all minor revisions of L09S maskset XL45J denotes all minor revisions of L45J maskset Maskset dependent errata can be accessed at http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp 2. All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8 channel timer. The GC-Family members do not have the CAN module 3. I/O is the sum of ports capable to act as digital input or output.
Version
V02 V01 V04 V04 V03 V01 V02 V04 V02 V03 V02 V01 V01 V02 V02 V01 V01 V01 V01
Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block Guide Timer: 16 bit, 8 channel (TIM_16B8C) Block Guide Voltage Regulator (VREG) Block Guide Oscillator (OSC) Block Guide Port Integration Module (PIM_9C32) Block Guide 32Kbyte Flash EEPROM (FTS32K) Block Guide 64Kbyte Flash EEPROM (FTS64K) Block Guide 128Kbyte Flash EEPROM (FTS128K1) Block Guide
NOTES: 1. For the GC16 refer to the 16K flash, for the C32 and GC32 refer to the 32K flash, for the C64 and GC64 the 64K flash, for the C96 the 96K flash and C128 the 128K flash document. 2. Not available on the GC-Family members
Inc.
Terminology
Acronyms and Abbreviations New or invented terms, symbols, and notations
Section 1 Introduction
1.1 Overview
The MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-based Industrial/Automotive network control MCU family. Members of the MC9S12C-Family and the MC9S12GC-Family deliver the power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications. All MC9S12C-Family and MC9S12GC-Family members are comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC). The MC9S12C-Family members also feature a CAN 2.0 A, B software compatible module (MSCAN12). The MC9S12C-Family as well as the MC9S12GC-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family and the MC9S12GC-Family devices are available in 48, 52 and 80 pin QFP packages, with the 80 Pin version pin compatible to the HCS12 A, B and D- Family derivatives.
1.2 Features
16-bit HCS12 CORE HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmers model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing MMC (memory map and interface) INT (interrupt control) BDM (background debug mode) DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer) MEBI: Multiplexed Expansion Bus Interface (available only in 80 pin package version) Up to 12-port bits available for wake up interrupt function with digital filtering 16K or 32KByte Flash EEPROM (erasable in 512-byte sectors) 64K, 96K or 128KByte Flash EEPROM (erasable in 1024-byte sectors)
Inc.
Analog-to-Digital Converters
Available on MC9S12C-Family: One 1M bit per second, CAN 2.0 A, B software compatible module Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function Loop-back for self test operation 8-Channel Timer Each Channel Configurable as either Input Capture or Output Compare Simple PWM Mode Modulo Reset of Timer Counter 16-Bit Pulse Accumulator External Event Counting Gated Time Accumulation Programmable period and duty cycle 8-bit 6-channel or 16-bit 3-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input One asynchronous serial communications interface (SCI) One synchronous serial peripheral interface (SPI) Windowed COP watchdog, Real time interrupt, Clock monitor,
6 PWM channels
Serial interfaces
Operating frequency
Development support
Inc.
Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only) Special Peripheral Mode (Motorola use only) Stop Mode Pseudo Stop Mode Wait Mode
VDDA VSSA VRH VRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PW0 PW1 PW2 PW3 PW4 PW5
VDDA VSSA VRH VRL PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PJ6 PJ7 PS0 PS1 PS2 PS3 PM0 PM1 PM2 PM3 PM4 PM5
DDRAD DDRT Key Int Keypad Interrupt DDRP DDRJ DDRS DDRM
16K, 32K, 64K, 96K, 128K Byte Flash 1K, 2K, 4K Byte RAM
Background MODC Debug12 Module Clock and Reset Generation Module
XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST/VPP
PLL
XIRQ IRQ System R/W Integration LSTRB/TAGLO Module ECLK (SIM) MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS
DDRE
PTE
PWM Module
SCI
RXD TXD
DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
I/O Driver 5V
VDDX VSSX
PLL 2.5V
VDDPLL VSSPLL
A/D Converter 5V
VDDA VSSA
PTAD
Inc.
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size
24 1 1 2 4 16 4 12 48 16 32 40 8 8 8 32 16 48 64 192 64 384
$030 - $033 $034 - $03F $040 - $06F $070 - $07F $080 - $09F $0A0 - $0C7 $0C8 - $0CF $0D0 - $0D7 $0D8 - $0DF $0E0 - $0FF $100 - $10F $110 - $13F $140 - $17F $180 - $23F $240 - $27F $280 - $3FF
NOTES: 1. External memory paging is not supported on this device (6.1.1 PPAGE). 2. Not available on MC9S12GC-Family Devices
1K Register Space PAGE MAP Mappable to any 2K Boundary 16K Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary
$3D
$3E
$7FFF $8000 $8000 16K Page Window 8 * 16K Flash EEPROM Pages
EXT
PPAGE
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
The gure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes
Inc.
1K Register Space PAGE MAP Mappable to any 2K Boundary 16K Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary
$3D
$3E
$7FFF $8000 $8000 16K Page Window 6 * 16K Flash EEPROM Pages
EXT
PPAGE
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
The gure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes
1K Register Space PAGE MAP Mappable to any 2K Boundary 16K Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary
$3D
$3E
$7FFF $8000 $8000 16K Page Window 4 * 16K Flash EEPROM Pages
EXT
PPAGE
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
The gure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes
Inc.
$3800
$3800 $3FFF
$4000
$3E
$8000
EXT
PPAGE
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
The gure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes The flash page $3E is visible at $4000-$7FFF in the memory map if ROMHM=0. In the figure ROMHM=1 removing page $3E from $4000-$7FFF.
$3C00
$3C00 $3FFF
$4000
EXT
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
The gure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0C00 - $0FFF: 1K RAM The 16K ash array page $3F is also visible in the PPAGE window when PPAGE register contents are odd. Flash Erase Sector Size is 512 Bytes
Inc.
$0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
$0010 - $0014
Address $0010 $0011 Address Name INITRM INITRG Name
$0015 - $0016
Address Name ITCR ITEST Read: Write: Read: Write:
$0015 $0016
$0017 - $0017
Address $0017 Name Reserved Read: Write:
$0018 - $0018
Address $0018 Name Reserved Read: Write:
$0019 - $0019
Address $0019 Name VREGCTRL Read: Write:
$001A - $001B
Address $001A $001B Name PARTIDH PARTIDL Read: Write: Read: Write:
Inc.
$001E - $001E
Address $001E Name INTCR Read: Write:
$001F - $001F
Address $001F Name HPRIO Read: Write:
Bit 6
PSEL6
Bit 5
PSEL5
Bit 4
PSEL4
Bit 3
PSEL3
Bit 2
PSEL2
Bit 1
PSEL1
Bit 0
0
$0020 - $002F
Address $0020 $0021 $0022
$0023 $0024 $0025 $0026 $0027
Name DBGC1
-
Bit 6
ARM BF Bit 14 Bit 6 0
Bit 5
TRGSEL CF Bit 13 Bit 5
Bit 4
BEGIN 0 Bit 12 Bit 4
Bit 3
DBGBRK
Bit 2
0
Bit 1
Bit 0
CAPMOD TRG
DBGSC
DBGTBH DBGTBL DBGCNT DBGCCX DBGCCH DBGCCL -
Bit 10 Bit 2
Bit 9 Bit 1
Bit 8 Bit 0
DBGC2
BKPCT0
DBGC3
BKPCT1 DBGCAX BKP0X DBGCAH BKP0H
read BKABEN FULL BDM TAGAB BKCEN TAGC write read BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA write read PAGSEL EXTCMP write
read write Bit 15 14 13 12 11 10
Bit 8
Name
DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
$0030 - $0031
$0032 - $0033
Address $0032 $0033 Name PORTK1 DDRK(1) Read: Write: Read: Write:
NOTES: 1. Only applicable in special emulation-only bond outs, for emulation of extended memory map.
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL
Inc.
$0040 - $006F
Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Bit 6 IOS6
0 FOC6
Bit 5 IOS5
0 FOC5
Bit 4 IOS4
0 FOC4
Bit 3 IOS3
0 FOC3
Bit 2 IOS2
0 FOC2
Bit 1 IOS1
0 FOC1
Bit 0 IOS0
0 FOC0
OC7M7 OC7D7
Bit 15 Bit 7
OC7M6 OC7D6
14 6
OC7M5 OC7D5
13 5
OC7M4 OC7D4
12 4
OC7M3 OC7D3
11 3
OC7M2 OC7D2
10 2
OC7M1 OC7D1
9 1
OC7M0 OC7D0
Bit 8 Bit 0
TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF
Bit 6
14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 PAEN
Bit 5
13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 PAMOD
Bit 4
12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 PEDGE
Bit 3
11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 CLK1
Bit 2
10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 CLK0
Bit 1
9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 PAOVI
Bit 0
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI
$0057 $0058 $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067
0
Bit 15
0
14
0
13
0
12
0
11
0
10
PAOVF
9
PAIF
Bit 8
Bit 7 0 0 0 0
6 0 0 0 0
5 0 0 0 0
4 0 0 0 0
3 0 0 0 0
2 0 0 0 0
1 0 0 0 0
Bit 0 0 0 0 0
Inc.
Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0
$006F
$0070 - $007F
$0070 - $007F Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$0080 - $009F
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
$0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F
$00A0 - $00C7
$00A0 - $00C7 Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
Inc.
Bit 5
0
Bit 4
SBR12
Bit 3
SBR11
Bit 2
SBR10
Bit 1
SBR9
Bit 0
SBR8
SBR3 WAKE TE OR 0 0 R3 T3
$00D0 - $00D7
$00D0 - $00D7 Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$00D8 - $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
$00E6 $00E7 $00E8 $00E9 $00EA $00EB $00EC $00ED $00EE $00EF $00F0 $00F1 $00F2 $00F3 $00F4 $00F5 $00F6
0 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Inc.
Bit 3 3 3 3 3 3 3 3 0 0 Bit 2 2 2 2 2 2 2 2 0 0 Bit 1 1 1 1 1 1 1 1 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0
$00FE $00FF
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 $010A $010B Name FCLKDIV FSEC FTSTMOD FCNFG FPROT
FSTAT
FCMD Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test
$0110 - $013F
Reserved
Read: Write: 0 0 0 0 0 0 0 0
$0110 - $003F
Reserved
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D Name CANCTL0 CANCTL1 CANBTR0 CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CANTARQ CANTAAK CANTBSEL CANIDAC Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Bit 6
RXACT
Bit 5
CSWAI LOOPB
Bit 4
SYNCH
Bit 3
TIME 0
Bit 2
WUPE WUPM
Bit 1
SLPRQ SLPAK
Bit 0
INITRQ INITAK
CLKSRC
LISTEN
0
0
0
0
0
0
0
0
0
0
TXEIE2
ABTRQ2
TXEIE1
ABTRQ1
TXEIE0
ABTRQ0
0
0
0
0
0
0
0
0
0
0
ABTAK2
TX2
ABTAK1
TX1
ABTAK0
TX0
0 0 0
0 0 0
IDAM1 0 0
IDAM0 0 0
0 0 0
IDHIT2 0 0
IDHIT1 0 0
IDHIT0 0 0
Inc.
Bit 5
RXERR5 TXERR5
Bit 4
RXERR4 TXERR4
Bit 3
RXERR3 TXERR3
Bit 2
RXERR2 TXERR2
Bit 1
RXERR1 TXERR1
Bit 0
RXERR0 TXERR0
FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2
NOTES: 1. Not available on the MC9S12GC-Family members. Those memory locations should not be accessed.
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $xxx0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 CANxRDSR0 CANxRDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$xxx1
ID9
ID8
ID7
$xxx2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
$xx10
$xx12
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xx13 $xx14$xx1B
DB7
DB6
DB5
DB4
DB3 DLC3
$0180 - $023F
$0180 - $023F Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$0240 - $027F
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PTS3
PTS2
PTS1
PTS0
Inc.
PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 WOMM2 0 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 0 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 WOMM1 0 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0 WOMM0 0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 0
PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 WOMM3 0 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 0
$0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258 $0259 $025A $025B $025C $025D $025E $025F $0260
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD5 PTIAD5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD4 PTIAD4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD3 PTIAD3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD2 PTIAD2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD1 PTIAD1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTAD0 PTIJ7
$0268 $0269 $026A $026B $026C $026D $026E $026F $0270 $0271 $0272 $0273 $0274 $0275 $0276$027F
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Read: PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 Write:
Read: PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 Write: Read: 0 0 0 0 0 0 0 0 Write:
Inc.
Reserved space
Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID numbers for production mask sets. Table 1-3 Assigned Part ID Numbers
Device MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C96 MC9S12C128 MC9S12GC16 MC9S12GC32 MC9S12GC64 MC9S12GC96 MC9S12GC128 Mask Set Number 1L45J 2L45J 2L09S 2L09S 2L09S 2L45J 2L45J 2L09S 2L09S 2L09S Part ID1 $3300 $3302 $3102 $3102 $3102 $3302 $3302 $3102 $3102 $3102
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to Module Mapping and Control (MMC) Block Guide for further details. Table 1-4 Memory size registers
Device MC9S12GC16 MC9S12C32, MC9S12GC32 Register name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 Value $00 $80 $00 $80
Inc.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PW4 PP5/KWP5/PW5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMCTL PS3 PS2 PS1/TXD PS0/RXD VSSA VRL PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12C-Family MC9S12GC-Family
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PP4/KWP4/PW4
PP5/KWP5/PW5
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM4/MOSI
PM5/SCK 43
52
51
50
49
48
47
46
45
44
42
41
40
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
PW3/KWP3/PP3 PW0/IOC0/PT0
PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB4
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00
MC9S12C-Family MC9S12GC-Family
33 32 31 30 29 28 27
PA2 PA1
PA0
14
15
16
17
18
19
20
21
22
23
24
25
VDDR
RESET
VDDPLL
EXTAL
VSSR
XTAL
XFC
* Signals shown in Bold italic are not available on the 48 Pin Package
XCLKS/PE7
ECLK/PE4
VSSPLL
26
Inc.
PP5/KWP5/PW5
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM4/MOSI
PM5/SCK 40
48
47
46
45
44
43
42
41
39
38
37
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA0 XIRQ/PE0
MC9S12C-Family MC9S12GC-Family
31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22 XTAL
23
VDDR
XFC
RESET
VDDPLL
EXTAL
VSSR
XCLKS/PE7
TEST/VPP IRQ/PE1
ECLK/PE4
VSSPLL
24
Description
Background debug, mode pin, tag signal high Port E I/O pin, access, clock select Port E I/O pin and pipe status Port E I/O pin and pipe status Port E I/O pin, bus clock output Port E I/O pin, low strobe, tag signal low Port E I/O pin, R/W in expanded modes Port E input, external interrupt pin Port E input, non-maskable interrupt pin
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR PUCR PUCR PUCR Mode Dep1 Mode Dep(1) Mode Dep(1) Up Up
PA[2:1]
PA[0] PB[7:5] PB[4] PB[3:0] PAD[7:0] PP[7] PP[6] PP[5]
ADDR[10:9/ DATA[10:9]
ADDR[8]/ DATA[8] ADDR[7:5]/ DATA[7:5] ADDR[4]/ DATA[4] ADDR[3:0]/ DATA[3:0] AN[7:0] KWP[7] KWP[6] KWP[5]
ROMCTL PW5
VDDX
VDDX VDDX VDDX VDDX VDDA VDDX VDDX VDDX
PUCR
PUCR PUCR PUCR PUCR
PERAD/P Disabled Port AD I/O pins and ATD inputs PSAD PERP/ PPSP PERP/ PPSP PERP/ PPSP Disabled Port P I/O Pins and keypad wake-up Disabled Port P I/O Pins, keypad wake-up and ROMON enable.
PP[4:3]
KWP[4:3]
PW[4:3]
VDDX
PERP/ PPSP
Inc.
Description
Disabled Port P I/O Pins, keypad wake-up, PWM outputs Disabled Port J I/O Pins and keypad wake-up Up Up Up Up Up Up Up Up Up Port M I/O Pin and SPI SCK signal Port M I/O Pin and SPI MOSI signal Port M I/O Pin and SPI SS signal Port M I/O Pin and SPI MISO signal Port M I/O Pin and CAN transmit signal2 Port M I/O Pin and CAN receive signal2 Port S I/O Pins Port S I/O Pin and SCI transmit signal Port S I/O Pin and SCI receive signal
Disabled Port T I/O Pins shared with timer (TIM) Disabled Port T I/O Pins shared with timer and PWM
NOTES: 1. The PortE output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. E.g. in special test mode RDWE=LSTRE=1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to S12_MEBI user guide for PEAR register details. 2. CAN functionality is not available on the MC9S12GC-Family members
CP
Inc.
2.3.5 BKGD / TAGHI / MODC Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when the state of this pin is latched to the MODC bit.
EXTAL CDC * MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC C1 Crystal or ceramic resonator
EXTAL
C1
MCU RS* RB
XTAL
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturers data.
EXTAL
MCU
XTAL
not connected
Freescale Device User Guide 9S12C128DGV1/D V01.10Semiconductor, 2.3.9 PE6 / MODB / IPIPE1 Port E I/O Pin 6
Inc.
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1}. This pin is an input with a pull-down device which is only active when RESET is low. PE[6] is not available in the 48 / 52 pin package versions.
2.3.12 PE3 / LSTRB Port E I/O Pin [3] / Low-Byte Strobe (LSTRB)
In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register. This signal is used in write operations. Therefore external low byte writes will not be possible until this function is enabled. This pin is also used as TAGLO in Special Expanded modes and is multiplexed with the LSTRB function. This pin is not available in the 48 / 52 pin package versions.
Freescale Semiconductor, Inc. Device User Guide 9S12C128DGV1/D V01.10 2.3.14 PE1 / IRQ Port E input Pin [1] / Maskable Interrupt Pin
The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code register. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ Port E input Pin [0] / Non Maskable Interrupt Pin
The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
Inc.
Freescale Semiconductor, Inc. Device User Guide 9S12C128DGV1/D V01.10 2.3.27 PS[3:2] Port S I/O Pins [3:2]
PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin package versions.
PS0 is a general purpose input or output pin and the receive pin, RXD, of Serial Communication Interface (SCI).
2.4.2 VDDR, VSSR Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for the internal voltage regulator. Connecting VDDR to ground disables the internal voltage regulator.
Inc.
2.4.4 VDDA, VSSA Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter.
Nominal Voltage
2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 2.5 V 0V
Description
Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. In the 48 and 52 LQFP packages VDD2 and VSS2 are not available. External power and ground, supply to internal voltage regulator.
External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltage low for the ATD converter. In the 48 and 52 LQFP packages VRL is bonded to VSSA. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.
NOTE:All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.
Flash RAM TIM ATD EXTAL PIM SCI CRG bus clock oscillator clock XTAL VREG TPM SPI MSCAN Not on 9S12GC
Inc.
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection
BKGD = MODC
0
PE6 = MODB
0
PE5 = MODA
0
PP6 = ROMCTL
X 0 1 X 0 1 X 0 1 X 0 1
ROMON Bit
1 1 0 0 1 0 1 0 1 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conicts (must not be used) Normal Expanded Wide, BDM allowed
0 1 1 0 0 1 1
1 0 1 0 1 0 1
0 0 1 1 1 1
For further explanation on the modes refer to the S12_MEBI block guide.
Description
Colpitts Oscillator selected Pierce Oscillator/external clock selected
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: Protection of the contents of FLASH, Operation in single-chip mode, Operation from external memory with internal FLASH disabled.
The user must be reminded that part of the security must lie with the users code. An extreme example would be users code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the users program. An example
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be blocked.
Inc.
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption reduction the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9
Interrupt Source
External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) Clock Monitor fail reset COP failure reset Unimplemented instruction trap
CCR Mask
None None None None
Local Enable
None COPCTL (CME, FCME) COP rate select None
SWI XIRQ IRQ Real Time Interrupt Standard Timer channel 0 Standard Timer channel 1 Standard Timer channel 2 Standard Timer channel 3 Standard Timer channel 4 Standard Timer channel 5 Standard Timer channel 6 Standard Timer channel 7 Standard Timer overow Pulse accumulator A overow Pulse accumulator input edge SPI SCI
None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved
None None INTCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TMSK2 (TOI) PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) PIEP (PIEP7-6)
$F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6
ATD Port J
$D2 $CE
I-Bit I-Bit Reserved I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved
PLLCR (LOCKIE) PLLCR (SCMIE) FCNFG (CCIE, CBEIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) PIEP (PIEP7-0) PWMSDN(PWMIE) CTRL0 (LVIE)
$C6 $C4 $B8 $B6 $B4 $B2 $B0 $8E $8C $8A
Reserved
5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. When a reset occurs, MCU registers and control bits are
Inc.
changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
Priority
1 1 1 2 3
Source
CRG Module RESET pin VREG Module CRG Module CRG Module
Vector
$FFFE, $FFFF $FFFE, $FFFF $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB
NOTE:
For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
PAGE
3F 3E 3F 3C 3D 3E 3F 3A 3B
MC9S12C64 MC9S12GC64
MC9S12C96 MC9S12GC96
3C 3D 3E 3F 38 39 3A
MC9S12C128 MC9S12GC128
3B 3C 3D 3E 3F
Inc.
To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE should not be changed by software.
7.1.1 VREGEN
VREGEN is connected internally to VDDR.
Purpose
VDD1 lter capapcitor VDD2 lter capacitor (80 QFP only) VDDA lter capacitor VDDR lter capacitor VDDPLL lter capacitor VDDX lter capacitor OSC load capacitor
Type
ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value
220nF, 470nF1 220nF 100nF >=100nF 100nF >=100nF
See PLL specication chapter OSC load capacitor PLL loop lter capacitor See PLL specication chapter C10 C11 R1 R2 / RB R3 / RS Q1 PLL loop lter capacitor DC cutoff capacitor PLL loop lter resistor PLL loop lter resistor Pierce mode only PLL loop lter resistor Quartz Colpitts mode only, if recommended by quartz manufacturer See PLL Specication chapter
C9
NOTES: 1. In 48LQFP and 52LQFP package versions, VDD2 is not available. Thus 470nF must be connected to VDD1.
Inc.
VDDX
C6 VSSX
VSSA
C3
VSSR C4 C5
VDDR
C8
C7
C11
Q1 VSSPLL VDDPLL
C9 R1
C10
VDDX
C6 VSSX VSSA
C3
VDDA
VDD1 C1 VSS1
C9 R1
C10
75
Inc.
C6
VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1
VSS2
C2 VDD2
VSSR
C4 C5
VDDR
C8
Q1
C7
C11
C9
R1
C10
VSSPLL VDDPLL
VDDX
C6 VSSX VSSA
C3
VDDA VDD1
C1 VSS1
VSSR C4 VDDR
Q1
R3
C5
C8
R2
C7
C10
R1
C9
VSSPLL VDDPLL
77
Inc.
VDDX
C6 VSSX VSSA
C3
VDDA VDD1
C1 VSS1
VSSR C4 VDDR
Q1
R3
C5
C8
R2
C7
C10
R1
C9
VSSPLL VDDPLL
VDDX
C6
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1
C2
VSS1 VDD2
VSSPLL
VSSR C4 C5 VDDR
R2 Q1 C8 C7 R3
C10
R1
C9
VSSPLL VDDPLL
79
Inc.
9.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS Port E I/O Pin 7).
Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module. Consult the SPI Block User Guide for information about the Synchronous Serial Communications Interface module.
Inc.
NOTE:
This supplement contains the most accurate electrical information for the MC9S12C-Family microcontrollers available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
NOTE:
P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
Inc.
VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. pull-up and pull-down resistors may be disabled permanently. A.1.3.2 Analog Reference This class is made up by the two VRH and VRL pins. In 48 and 52 pin package versions the VRL pad is bonded to the VSSA pin. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only.
Freescale Semiconductor, Inc. Device User Guide 9S12C128DGV1/D V01.10 A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage1 PLL Supply Voltage (1) Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 2 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL3 Instantaneous Maximum Current Single pin limit for TEST4 Operating Temperature Range (packaged) Operating Temperature Range (junction) Storage Temperature Range
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I
D
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 40 40 65
Max
6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 125 140 155
Unit
V V V V V V V V V mA mA mA C C C
IDL IDT T
A
TJ Tstg
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 3. These pins are internally clamped to VSSPLL and VDDPLL 4. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications.
Freescale Device User Guide 9S12C128DGV1/D V01.10Semiconductor, A.1.6 ESD Protection and Latch-up Immunity
Inc.
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance
Description
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5 7.5
Unit
Ohm pF
Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit
Ohm pF
V V
C
C C C C
Rating
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at 125C positive negative Latch-up Current at 27C positive negative
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
ILAT
mA
Symbol
VDD5 VDD VDDPLL VDDX VSSX fbus2 T
J
Min
2.97 2.375 2.35 -0.1 -0.1 0.25 -40
Typ
5 2.5 2.5 0 0 -
Max
5.5 2.75 2.75 0.1 0.1 25 140
Unit
V V V V V MHz C
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The operating conditions apply when this regulator is disabled and the device is powered from an external source. Using an external regulator, with the internal voltage regulator disabled, an external LVR must be provided. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation.
Two cases with internal voltage regulator enabled and disabled must be considered:
Inc.
Which is the sum of all output currents on I/O ports associated with VDDX and VDDM. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
V DD5 V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i
respectively
C
T T T T T T T T T T T T T T T
Rating
Thermal Resistance LQFP48, single layer PCB2 Thermal Resistance LQFP48, double sided PCB with 2 internal planes3 Junction to Board LQFP48 Junction to Case LQFP48 Junction to Package Top LQFP48 Thermal Resistance LQFP52, single sided PCB Thermal Resistance LQFP52, double sided PCB with 2 internal planes Junction to Board LQFP52 Junction to Case LQFP52 Junction to Package Top LQFP52 Thermal Resistance QFP 80, single sided PCB Thermal Resistance QFP 80, double sided PCB with 2 internal planes Junction to Board QFP80 Junction to Case QFP80 Junction to Package Top QFP80
Symbol
JA JA JB JC JT JA JA JB JC JT JA JA JB JC JT
Min
-
Typ
-
Max
69 53 30 20 4
Unit
o
C/W C/W
oC/W o o o o
65 49 31 17 3
7 8 9 10 11 12 13 14 15
52 42 28 18 4
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
Inc.
Conditions are 4.5< VDDX <5.5V Termperature from -40C to +140C, unless otherwise noted
Num
1
C
P T Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
P T
Input Leakage Current (pins in high ohmic input mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = 2mA Output High Voltage (pins in output mode) Full Drive IOH = 10mA Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA Output Low Voltage (pins in output mode) Full Drive IOL = +10mA Internal Pull Up Device Current, tested at V Max.
IL
in
5 6 7 8
C P C P
OH
0.8 0.8
V V V V A A A A pF mA s s
VOH VOL V
OL
-130
10
-10
11
130
12 13 14
C D T
10
2.5 25 3
Input Capacitance Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port P, J Interrupt Input Pulse ltered3 Port P, J Interrupt Input Pulse passed3
-2.5 -25
15 16
P P
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
Num
1
C
P T Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
P T
Input Leakage Current (pins in high ohmic input mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = 0.75mA Output High Voltage (pins in output mode) Full Drive IOH = 4mA Output Low Voltage (pins in output mode) Partial Drive IOL = +0.9mA Output Low Voltage (pins in output mode) Full Drive IOL = +4.75mA Internal Pull Up Device Current, tested at V Max.
IL
in
OH
OH
OL
0.4
OL
0.4
V A A A A pF mA s s
60
10
Internal Pull Up Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at V Min.
IH
-6
11
60
12 11 12
C D T
2.5 25 3
Input Capacitance Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port P, J Interrupt Input Pulse ltered3 Port P, J Interrupt Input Pulse passed3
-2.5 -25
13 14
P P
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
Inc.
This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
C
P P P C C P C P C P C P C C C C C C P C P C P C P
Rating
Run Supply Current Single Chip Wait Supply current All modules enabled VDDR<4.9V, only RTI enabled(2) VDDR>4.9V, only RTI enabled Pseudo Stop Current (RTI and COP disabled)(2)(3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Pseudo Stop Current (RTI and COP enabled)2 3 -40C 27C 85C 105C 125C Stop Current (3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
Symbol
IDD5
Min
Typ
Max
35 30 8
Unit
mA
IDDW
3.5 2.5 340 360 500 550 590 720 780 1100 540 700 750 880 1300 10 20 100 140 170 300 350 520
mA
IDDPS1
IDDPS1
IDDS(1)
NOTES: 1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is carried out at 100C although the Temperature specification is 85C. Similarly for "v" and "M" options the temperature used in test lies 15C above the temperature option specification. 2. PLL off 3. At those low power dissipation levels TJ = TA can be assumed
Inc.
C
P P P C C P C P C P C P C C C C C C P C P C P C P
Rating
Run Supply Current Single Chip, Wait Supply current All modules enabled VDDR<4.9V, only RTI enabled(2) VDDR>4.9V, only RTI enabled Pseudo Stop Current (RTI and COP disabled)(2)(3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Pseudo Stop Current (RTI and COP enabled)2 3 -40C 27C 85C 105C 125C Stop Current (3) -40C 27C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
Symbol
IDD5
Min
Typ
Max
45 33 8
Unit
mA
IDDW
2.5 3.5 190 200 300 400 450 600 650 1000 370 500 590 780 1200 12 25 130 160 200 350 400 600
mA
IDDPS1
IDDPS1
IDDS(1)
NOTES: 1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is carried out at 100C although the Temperature specification is 85C. Similarly for "v" and "M" options the temperature used in test lies 15C above the temperature option specification. 2. PLL off 3. At those low power dissipation levels TJ = TA can be assumed
C
P P
Characteristic
Input Voltages Output Voltage Core Full Performance Mode Low Voltage Interrupt1 Assert Level C32, GC32 Assert Level C64, C96,C128 GC64, GC128 Deassert Level C32, GC32 Deassert Level C64, C96, C128 GC64, GC128 Low Voltage Reset2,3 Assert Level C32, GC32 Assert Level C64, C96, C128 GC64, GC128 Power-on Reset4 Assert Level Deassert Level
Symbol
VVDDR, A VDD
Min
2.97
Typical
Max
5.5
Unit
V
2.375
2.5
2.75
V V V V
VLVRA
2.25 2.25
2.3 2.35
VPORA VPORD
0.97
2.05
V V
NOTES: 1. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 2. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure B-1) 3. Digital functionality is guaranteed in the range between VDD(min) and VLVRA(min). 4. Monitors VDD. Active in all modes.
Inc.
t
LVI
LVI enabled
POR
LVR
Freescale Semiconductor, Inc. Device User Guide 9S12C128DGV1/D V01.10 B.3.2 Capacitive Loads
The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required. Table B-2 Voltage Regulator - Capacitive Loads
Num
1 2
Characteristic
VDD external capacitive load VDDPLL external capacitive load
Symbol
CDDext CDDPLLext
Min
400 90
Typical
440 220
Max
12000 5000
Unit
nF nF
Inc.
The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table B-3 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%
Num
1 2 3 4
C
Reference Potential D C D D
Rating
Low High Differential Reference Voltage1 ATD Clock Frequency ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK Recovery Time (VDDA=5.0 Volts) Reference Supply current
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV10 TCONV10 tREC IREF
Typ
5.0
5 6
D P
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
Inc.
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped
Num C
Reference Potential 1 2 3 D
Rating
Low High
Typ
C Differential Reference Voltage D ATD Clock Frequency ATD 10-Bit Conversion Period D
3.3
Clock Cycles1 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles(1) Conv, Time at 2.0MHz ATD Clock fATDCLK
6 7
NOTES: 1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
Num
1 2 3 4 5
C
C T C C C
Rating
Max input Source Resistance Total Input Capacitance Non Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 15
Unit
K pF mA A/A A/A
-2.5
Freescale Device User Guide 9S12C128DGV1/D V01.10Semiconductor, B.4.4 ATD accuracy (5V Range)
Inc.
Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-6 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
C
P P P P P P P P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
5
Max
Unit
mV
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error1 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1)
1 2 2.5
4 5 6 7 8
NOTES: 1. These values include quantization error which is inherently 1/2 count for any A/D converter.
C
P P P P P P P P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
3.25
Max
Unit
mV
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1) Error1
1.5 3.5 5
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
INL ( n ) =
i=1
Inc.
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC
$FF
10-Bit Resolution
$3F4 $3F3
$FD
3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328
Vin mV
NOTE:
Figure B-2 shows only definitions, for specification values refer to Table B-6.
8-Bit Resolution
The minimum program and erase times shown in Table B-8 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz. B.5.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
Inc.
This is independent of sector size. The setup times can be ignored for this operation.
Num
1 2 3 4 5 6 6 7 8 9 9
C
D D D P D D D P P D D
Rating
External Oscillator Clock Bus frequency for Programming or Erase Operations Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word Flash Burst Programming Time for 32 Word row Flash Burst Programming Time for 64 Word row Sector Erase Time Mass Erase Time Blank Check Time Flash per block Blank Check Time Flash per block
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tbrpgm tera tmass t check t check
Min
0.5 1 150 462 20.42 678.42 1331.22 204 1004 115 118
Typ
Max
501
Unit
MHz MHz
kHz s s s s ms ms
7t cyc (7)t cyc
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus . Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP . 5. Minimum time, if first word in the array is not blank (512 byte sector size). 6. Maximum time to complete check on an erased block (512 byte sector size) 7. Where tcyc is the system bus clock period. 8. Minimum time, if first word in the array is not blank (1024 byte sector size) 9. Maximum time to complete check on an erased block (1024 byte sector size).
Freescale Semiconductor, Inc. Device User Guide 9S12C128DGV1/D V01.10 B.5.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed.
NOTE:
All values shown in Table B-9 are target values and subject to further extensive characterization. Table B-9 NVM Reliability Characteristics
Num
C
C C
Rating
Data Retention at an average junction temperature of TJavg = 85C Flash number of Program/Erase cycles
Symbol
tNVMRET nFLPE
Min
15 10,000
Typ
Max
Unit
Years Cycles
11 2
Inc.
B.6.1 Startup
Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide. Table B-10 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
T T D D D D POR release level POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
Min
Typ
Max
2.07
Unit
V V tosc
1 2 3 4 5 6
Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, IRQ edge-sensitive mode Wait recovery startup time
nosc ns tcyc
B.6.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. B.6.1.2 LVR The release level VLVRR and the assert level VLVRA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. B.6.1.3 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set.
Inc.
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. B.6.1.5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. B.6.1.6 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. In Pseudo Stop Mode the voltage regulator is switched to reduced performance mode to reduce power consumption. The returning out of pseudo stop to full perfomance takes tvup. The controller can be woken up by internal or external interrupts.After twrs in Wait or tvup+twrs in Pseudo Stop the CPU starts fetching the interrupt vector.
B.6.2 Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
Num
1a 1b 2 3 4
C
C C P C D P P D D D D D C P T
Rating
Crystal oscillator range (Colpitts) Crystal oscillator range (Pierce) 1(4) Startup Current Oscillator start-up time (Colpitts) Clock Quality check time-out Clock Monitor Failure Assert Frequency External square wave input frequency 4 External square wave pulse width low External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance (EXTAL, XTAL pins) DC Operating Bias in Colpitts Conguration on EXTAL Pin EXTAL Pin Input High Voltage4 EXTAL Pin Input High Voltage4 EXTAL Pin Input Low Voltage4 EXTAL Pin Input Low Voltage4 EXTAL Pin Input Hysteresis4
Symbol
fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS VIH,EXTAL VIH,EXTAL VIl,EXTAL VIl,EXTAL VHYS,EXTAL
Min
0.5 0.5 100
Typ
Max
16 40
Unit
MHz MHz A
ms s KHz MHz ns ns
5 6 7 8 9 10 11 12 13
ns ns pF V V V V V mV
14
P T
15
NOTES: 1. Depending on the crystal a damping series resistor might be necessary 2. fosc = 4MHz, C = 22pF. 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. Only valid if Pierce Oscillator/external clock selected (XCLKS =0 during reset)
Inc.
Cp VDDPLL Cs fosc fref 1 refdv+1 fcmp R Phase K Detector Loop Divider 1 synr+1
XFC Pin
VCO KV fvco
1 2
Figure B-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table B-12. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 f vco ) ---------------------K 1 1V ( 60 50 ) ---------------------- 100
KV = K1 e
= 100 e
= -90.48MHz/V
K = i ch K V
ich is the current in tracking mode.
= 316.7Hz/
The loop bandwidth fC should be chosen to fulfill the Gardners stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- ;( = 0.9 ) - f C < ------------4 10 10 2 + 1 + fC < 25kHz
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz:
2 n fC R = ---------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K
The capacitance Cs can now be calculated as:
C s 20 C p C s 10
Cp = 470pF
B.6.3.2 Jitter Information The basic functionality of the PLL is shown in Figure B-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-4.
Inc.
N-1
Figure B-4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
j1 J ( N ) = ------- + j2 N
J(N)
10
20
Num C
1 2 3 4
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 50 4 1.5 2.5 8
Unit
MHz MHz %1 %(1) %(1) %(1) ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
5 6 7 8 9 10 11 12 13 14 15
C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay (2) D PLLON Tracking mode stabilization delay (2) D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter t parameter 1(2) C Jitter t parameter 2(2)
% %
NOTES: 1. % deviation from target frequency 2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
Inc.
B.7 MSCAN
Table B-13 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Symbol
tWUP tWUP
Min
Typ
Max
2
P MSCAN Wake-up dominant pulse ltered P MSCAN Wake-up dominant pulse pass
Inc.
B.8 SPI
Value
full drive mode 50 (20% / 80%) VDDX
Unit
pF V
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 10 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
12
13
12
13
Figure C-1 SPI Master Timing (CPHA=0) In Figure C-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Inc.
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) MSB IN2 6 BIT 6 . . . 1 11 MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN 4 12 13 12 13 3
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure C-2 SPI Master Timing (CPHA=1) In Table C-2 the timing characteristics for master mode are listed. Table C-2 SPI Master Mode Timing Characteristics
Num
1 1 2 3 4 5 6 9 10 11 12 13
C
P P D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid after SCK Edge Data Valid after SS fall (CPHA=0) Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi tvsck tvss tho tr trfo
Min
1/2048 2 8 8 20
Typ
1/2 1/2 1/2
Max
1/2 2048 30 15 8 8
Unit
fbus tbus tsck tsck tsck ns ns ns ns ns ns ns
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 10 7 MISO (OUTPUT) see note 5 MOSI (INPUT) NOTE: Not defined! MSB IN SLAVE MSB 6 BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 4 4 12 13 8 11 11 SEE NOTE 12 13 3
Figure C-3 SPI Slave Timing (CPHA=0) In Figure C-4 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
Inc.
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) see note 7 MOSI (INPUT) NOTE: Not defined! SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 12 13 12 13 3
Figure C-4 SPI Slave Timing (CPHA=1) In Table C-3 the timing characteristics for slave mode are listed. Table C-3 SPI Slave Mode Timing Characteristics
Num
1 1 2 3 4 5 6 7 8 9 10 11 12 13
C
D P D D D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho tr trfo
Min
DC 4 4 4 4 8 8 20
Typ
Max
1/4 20 22 30 + tbus
1
Unit
fbus tbus tbus tbus tbus ns ns ns ns ns ns ns ns ns
30 + tbus 1 8 8
3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 16
10 data
11
14 data
13
17 R/W PE2
18
19
20 LSTRB PE3
21
22
23 NOACC PE7
24
25
27
28
29
Inc.
Num
1 2 3 4 5 6 7
C
P P D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating
Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high1 Address delay time Address valid time to E rise (PWELtAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEHtDDW) Address access time(1) (tcyctADtDSR) E high access time(1) (PWEHtDSR) Read/write delay time Read/write valid time to E rise (PWELtRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWELtLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWELtLSD) NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWELtP0D) IPIPO[1:0] delay time(1) (PWEH-tP1V) IPIPO[1:0] valid time to E fall
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V tP1D tP1V
Min
0 40 19 19
Typ
Max
25.0
Unit
MHz ns ns ns
8 11 2 7 2 13 0 7 2 12 19 6 7 14 2 7 14 2 7 14 2 2 11 2 11 25 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
Num
1 2 3 4 5 6 7
C
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating
Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high1 Address delay time Address valid time to E rise (PWELtAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEHtDDW) Address access time(1) E high access time(1) (PWEHtDSR) Read/write delay time Read/write valid time to E rise (PWELtRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWELtLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWELtLSD) NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWELtP0D) IPIPO[1:0] delay time(1) IPIPO[1:0] valid time to E fall
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V tP1D tP1V
Min
0 62.5 30 30
Typ
Max
16.0
Unit
MHz ns ns ns
16 16 2 7 2 15 0 15 2 15 29 15 14 16 2 14 16 2 14 16 2 2 16 2 11 25 14
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
Inc.
Inc.
B B P
H A-B
V 0.05 D
C A-B
-A-
-B-
0.20
0.20
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-D0.20
M
A H A-B S
0.05 A-B J
S
C A-B
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM PLANE
-H-
K W X DETAIL C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
52 1
40 39
C L AB G
3X
-L-
B1
13 27 14 26
V1
PLATING
J D T L-M
A1 S1 A S
-N0.13 (0.005)
M
C -H-TSEATING PLANE
4X
2
0.10 (0.004) T
4X
3
VIEW AA
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
SECTION AB-AB
0.05 (0.002)
1
C2
2X R
R1
0.25 (0.010)
GAGE PLANE
K C1 E VIEW AA Z
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0 7 --0 12 REF 12 REF
INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0 7 --0 12 REF 12 REF
Inc.
0.200 AB T-U Z 9 A1
48 37
DETAIL Y
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 1. CONTROLLING DIMENSION: MILLIMETER. 2. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 3. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 7. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 8. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 7 12 REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M
TOP & BOTTOM
R
GAUGE PLANE
C F D 0.080
M
AC T-U Z H W DETAIL AD AA K L
SECTION AE-AE
0.250
Signals shown in Bold are available only in the 112 Pin Package. Pins marked "NC" are not connected
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 NC NC NC NC XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST NC NC NC NC LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
VRH VDDA NC PAD07/AN07 NC PAD06/AN06 NC PAD05/AN05 NC PAD04/AN04 NC PAD03/AN03 NC PAD02/AN02 NC PAD01/AN01 NC PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Inc.
PK2-PK0 provide the expanded address XADDR[16:14] for the external bus. Refer to the S12 Core user guide for detailed information about external address page access.
Power Domain
VDDX
Description
The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs.
The reset state of PUPKE in the PUCR register of the S12_CORE is "1" enabling the internal pullup resistors at PortK[2:0]. In this reset state the pull-up resistors provide a defined state and prevent a floating input, thereby preventing unneccesary current consumption at the input stage.
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
VIEW Y
108X
X X=L, M OR N
VIEW Y B L M B1 V1 V
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R2 0.25
GAGE PLANE
R1
(K) E
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no. 841B)
Inc.
Inc.