For tbe tollowlng oynamlc RAM cell, C

8L
= 0.1pl ano C
C
= 20fl. Tbe cell ls
connecteo to a sense ampller tbat requlres a mlnlmum reaoout voltage ot 40m\. You
may assume tbat tbe blt llne ls pre-cbargeo to \
uu
/2 ourlng tbe reaolng process, tbat
tbe cell contalns a zero,
n
C
ox
= 0.3mA/\
2
, \
t
= 1\ ano \
uu
= 5\. Flno tbe access
translstor's W/L ratlo neeoeo to reao tbe cell's oata ln 1ps.
WL
BL
C
C
Tuesday, November 20, 12
INEL4207 Ex. 3a - Solutions - May 3, 2012
1. (40 points) For the following dynamic RAM cell, C
BL
= 0.1pF and C
C
= 20fF. The cell is
connected to a sense amplier that requires a minimum readout voltage of 40mV . You may
assume that the bit line is pre-charged to V
DD
/2 during the reading process, that the cell
contains a zero,
n
C
ox
= 0.3mA/V
2
, V
t
= 1V and V
DD
= 5V . Find the access transistors
W/L ratio needed to read the cells data in 1ps. (40 points)
WL
BL
C
C
ANSWER:
i
ave
= C
V
t
= 0.1pF
40mV
1ps
= 4mA
C
BL
v
BL
= C
C
v
C
v
C
=
100fF
20fF
40mV = 0.2V
At point 1, v
C
= 0, v
DS
= 2.5V and v
GS
V
t
= 5V 1V = 4V > v
DS
, so
i
1
= (0.15mA)(W/L)

2(4)2.5 2.5
2

= 2.0625mA

W
L

At point 2, v
C
= 0.2V = v
S
, v
DS
= 2.5V .04V 0.2V = 2.26V , and v
GS
V
t
= 5V
0.2V 1V = 3.8V , so
i
2
= (0.15mA)(W/L)

2(3.8)2.26 2.26
2

= 1.81mA

W
L

and
i
ave
= 4mA =
2.0625mA+ 1.81mA
2

W
L

W
L
= 2.1
2. The following diagram sketches a dial-slope ADC. At t = 0, capacitor C is discharged, s
1
opens and s
2
is connected to v
A
, an analog input voltage in the range of 0V to 5V . At
t = T
1
, s
2
is switched to V
REF
= 5V .
(a) (20 points) Find R and C so that the conversion time remains below 0.1ms if v
peak
=
10V .
(b) (10 points) Find the clock frequency if a 10-bit resolution is required.
timer/counter
enable
clear
CLK
N output bits
clock
control
logic

+
v
A
V
REF
R
C
s
1
s
2
up/down
v
peak
T
1
T
1
+T
2
t
v
O
v
O
V
REF
> 0
v
A
< 0
Tuesday, November 20, 12
Tbe tollowlng RS-latcb ls epecteo to be capable ot operatlng at 1CHz 1/
PHL
.
Use tbe average current metboo to estlmate tbe W/L ratlo ot M
5
ano M
6
. H|NT:
Pulllng oown \
Q
to \
uu
/2 wlll cause \
Q
to go up to \
uu
/2 ano tbe state wlll cbange
oue to regeneratlon. Tbe clrcult parameters are:
n
C
ox
= 4
p
C
ox
= 0.3mA/\
2
, \
tn
=
\
tp
= 0.5\ ano \
uu
= 1.8\. Tbe lnverter MOSFLTs bave (W/L)
p
= 4(W/L)
n
= 6/1.
Tbe total capacltance between eacb ot Q ano Q

ano grouno ls 10pF.

V
DD
M
1
M
3
M
2
M
4
M
5
M
6
Q
Q
S R
Tuesday, November 20, 12
INEL4207 Ex. 3b - Solutions - May 3, 2012
1. (30 points) The following RS-latch is expected to be capable of operating at 1GHz 1/
PHL
.
Use the average current method to estimate the W/L ratio of M
5
and M
6
. HINT: Pulling
down V
Q
to V
DD
/2 will cause V
Q
to go up to V
DD
/2 and the state will change due to
regeneration. The circuit parameters are:
n
C
ox
= 4
p
C
ox
= 0.3mA/V
2
, V
tn
= V
tp
= 0.5V
and V
DD
= 1.8V . The inverter MOSFETs have (W/L)
p
= 4(W/L)
n
= 6/1. The total
capacitance between each of Q and Q

and ground is 10pF .

V
DD
M
1
M
3
M
2
M
4
M
5
M
6
Q
Q
S R
ANSWER: Consider the node Q. For point 1, when v
Q
= V
DD
, M
4
is not conducting current
because v
SD,4
= 0, and the current discharging the capacitor is
i
1
= 0.15mA

W
L

(1.8V 0.5V )
2
= (253.5A)

W
L

At point 2, v
Q
= V
DD
/2, and both M
4
and M
6
have current. Both transistors are in triode
region and
i
M4
=
1
2
0.3mA
4
(6/1)

2(1.8V 0.5V )0.9V (0.9V )

2

= 344.25A
i
M6
= 0.15mA

W
L

2(1.8V 0.5V )0.9V (0.9V )

2

= (229.5A)

W
L

Thus,
i
2
= i
M6
i
M4
= (229.5A)

W
L

344.25A
and
i
ave
=
1
2
(i
1
+i
2
) = (241.5A)

W
L

172.125A = 10pF
0.9V
1ns
= 9mA
W
L
=
9000A+ 172.125A

241.5A
38
2. (30 points) The following diagram sketches an ADC. Prior to t = 0, capacitor C is discharged
and the counter is erased by the control signal. At t = 0, s
1
opens and the counter is allowed
to count. The analog input voltage, v
A
, is in the range of 0V to 5V . If V
DC
= 10V . Find
R and C so that the conversion time remains below 0.1ms and v
peak
= 10V .
Tuesday, November 20, 12