CSCE 488

An Introduction to FPGA and SOPC Development Board

(Adapted from material developed by Yong Wang & Stefan Hass)

Yuyan Xue

Outline
What are Programmable Logic Devices? Architecture and Examples Why FPGA? Vendors and Device Series Development on Altera Devices Summary

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Programmable Logic Devices

Programmable Logic Devices

Programmable digital integrated circuit Desired functionality is implemented by configuring on-chip logic blocks and interconnections (compared with ASIC) Developers only care about the logic design but not the internal hard-wire connection ( softwarelize the hardware design)

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ASIC Vs. Programmable Logic Device

ASIC (Application Specific Integrated Circuit)
Longer design cycle and costlier ECO (Engineering Change order) Faster performance Lower cost if produced in high volume >10,000 chips Energy saving

Programmable Logic Device

Shorter design cycle and cheaper ECO Longer delay Higher cost per chip Good for medium to low volume products More power consumption
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Type of Programmable Logic Devices

PLD (Programmable Logic Device) CPLD (Complex Programmable Logic Device) FPGA (Field Programmable Gate Array)

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Architecture and Examples

PLD - Sum of Products

Programmable AND array followed by fixed fan-in OR gates
A B C Programmable switch or fuse Product Terms
f1 = A B C + A B C

f2 = A B + A B C

AND plane

any logical function can be written in SOP (Sum of Products) form => any function can be implemented by AND gates generating products which feed to an OR gate that sums them up
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PLD - Macrocell
Can implement combinational or sequential logic
Select A B C Enable

f1
Flip-flop MUX D Q

Clock

AND plane

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CPLD Structure
Integration of several PLD blocks with a programmable interconnect on a single chip
I/O Block Block I/O I/O Block Block I/O I/O Block Block I/O

PLD PLD Block Block

PLD PLD Block Block

Interconnection Interconnection Matrix Matrix

I/O Block Block I/O

PLD PLD Block Block

PLD PLD Block Block

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CPLD Example - Altera MAX7000

EPM7000 Series Block Diagram

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CPLD Example - Altera MAX7000

EPM7000 Series Device Macrocell

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FPGA - Generic Structure

FPGA building blocks:
Programmable logic blocks Implement combinatorial and sequential logic Programmable interconnect Wires to connect inputs, outputs and different logic blocks Programmable I/O blocks Special logic blocks at the periphery of device for external connections
Logic block Interconnection switches

I/O

I/O

I/O

I/O

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FPGA Basic Logic Element

LUT(Look Up Table) to implement combinatorial logic Register for sequential circuits Additional logic (not shown):
Carry logic for arithmetic functions Expansion logic for functions requiring more than 4 inputs
Select

Out A B C D

LUT LUT
Clock

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Look-Up Tables (LUT)

Look-up table with N-inputs can be used to implement any combinatorial function of N inputs LUT is programmed with the truth-table
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z 0 1 1 1 0 1 1 1 0 1 1 1 0 0 0

A B C D

LUT LUT

LUT implementation
A B Z C D

Truth-table
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Gate implementation
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Other FPGA Building Blocks

Clock distribution Embedded memory blocks Special purpose blocks:
DSP blocks:
Hardware multipliers, adders and registers

Embedded microprocessors/microcontrollers High-speed serial transceivers

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Special Features
Clock management
PLL,DLL Eliminate clock skew between external clock input and on-chip clock Low-skew global clock distribution network

Support for various interface standards High-speed serial I/Os Embedded processor cores DSP blocks
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Configuration Storage Elements

SRAM Logical configuration is controlled by the state of SRAM bits FPGA needs to be configured at power-on by another separated ROM Flash Logical configuration is implemented by floating-gate transistors that can be turned off by injecting charge onto its gate. FPGA itself holds the program reprogrammable, even in-circuit

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Example: Altera Stratix Series

Why FPGA?
handle dense logic and memory elements offering very high logic capacity Easy to revise the logic design Lower cost and shorter development cycle Complete integrated design environment (IDE) Easy to learn and use

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FPGA Vendors
Altera Xilinx
Virtex-II/Virtex-4: Feature-packed high-performance SRAM-based FPGA Spartan 3: low-cost feature reduced version CoolRunner: CPLDs

Actel Lattice QuickLogic

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Introduction to Altera Devices

Programmable Logic Families High & Medium Density FPGAs Stratix II, Stratix, APEX II, APEX 20K, & FLEX 10K Low-Cost FPGAs Cyclone & ACEX 1K CPLDs MAX 7000 & MAX 3000 Embedded Processor Solutions Nios, ExcaliburT Configuration Devices EPC

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Nios: The processor in software

a user-configurable, 16-bit instruction set architecture (ISA), general-purpose RISC embedded processor designers can use the SOPC (system-on-aprogrammable-chip) Builder system development tool to very easily create custom processor-based systems
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Development on Altera Devices

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What is available?
Altera Stratix Nios Development Board Altera UP2 Development Board

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Altera Stratix Nios Development Board

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Altera Stratix Nios Development Board

Stratix EP1S10F780C6
10,570 Logic Elements 920 Kb on-chip memory

Provide hardware platform for developing embedded system

Comes pre-programmed with a 32-bit Nios processor reference design

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Altera Stratix Nios Development Board

8 MB of flash Memory,1MB of static RAM, 16MB of SDRAM On-board Ethernet MAC/PHY device Compact Flash connector hearder Two RS-232 DB9 serial ports 50MHz oscillator and zero-skew clock distribution circuitry Four push-button switches Dual 7-segment LED display
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Altera UP2 Development Board

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Altera UP2 Development Board

EPF10K70RC240-4 device EPM7128SLC-7 device One RS-232 serial port Four push-button switches Dual 7-segment LED display 25.175MHz oscillator
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FPGA Design Flow

Design Specification Design Entry Simulation Synthesis Place & Route Simulation Program device & test

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FPGA Design Flow

Design Specification

Design Entry/RTL Coding

Behavioral or Structural Description of Design

RTL Simulation
Functional Simulation Verify Logic Model & Data Flow (No Timing Delays)

LE
MEM I/O

Synthesis
Translate Design into Device Specific Primitives

Place & Route

Map Primitives to Specific Locations inside Target devices

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FPGA Design Flow

tclk

Timing Analysis
- Verify whether Performance Specifications Were Met - Static Timing Analysis

Gate Level Simulation

- Timing Simulation - Verify whether Design Will Work in Target Device

Program & Test

-Download Design Program to the device -& Test Device on Board

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Design Entry Methods

Text-based
VHDL(Very High Speed Integrated Circuit Hardware Description Language) Verilog HDL

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Block Diagram
Contents of a block can be any type of design unit

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State Diagram
Bubble diagram
States Conditions Transitions Outputs

Useful for developing control modules

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Program Devices
Once we verify our design, it should be downloaded to the FPGA devices Designs can be downloaded through parallel port in PC to the JTAG connector on board using download cables Designs can also be downloaded via the Internet to a target device

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Introduction to Altera Design Software

Software & Development Tools:
Quartus II
Stratix II, Stratix, Stratix GX, Cyclone, APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices FLEX 10K/A/E, ACEX 1K, FLEX 6000, MAX 7000S/AE/B, MAX 3000A Devices

Quartus II Web Edition

Free Version Not All Features & Devices Included

MAX+PLUS II
All FLEX, ACEX, & MAX Devices

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Quartus II Development System

Fully-Integrated Design Tool Multiple Design Entry Methods Logic Synthesis Place & Route Simulation Timing & Power Analysis Device Programming SignalTap II & SignalProbe Debug Tools
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Quartus II Operating Environment

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Main Toolbar & Modes

Execution Controls Window & new file buttons Compiler Report Simulation Controls Floorplans

Project Navigator CSCE488-2005 41

Summary
Prerequisite
Electronics and circuits Digital logic design VHDL

FPGA
Combine technologies in hardware & software Benefits

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