Assembly Language Coding (ALC) Part 2

IBM Mainframe Assembler Language Coding
Load Halfword
LH
R7,NEGBYTS
Reg 7 before: 00 00 00 C4
NEGBYTS before: FF F1
Reg 7 after: FF FF FF F1
NEGBYTS after: FF F1
69

Store Fullword The contents of the register specified as operand one are copied to the location designated by operand two.
ST
R7,FIELDA
Reg 7 before: 00 01 22 31
FIELDA before: 00 00 00 00
Reg 7 after: 00 01 22 31
FIELDA after: 00 01 22 31
70

Store Halfword The right-most two bytes of the register specified as operand one are copied to the location designated by operand two.
STH
R5,FIELDB
Reg 5 before: 10 FF FF E4
FIELDB before: 00 00
Reg 5 after: 10 FF FF E4
FIELDB after: FF E4
71
72

EXERCISE #3 PROGRAM 3. Input: rate dd.cc (decimal point implied). hours hh.t (decimal point implied). name. Message: b@hhtddccname+ name is max of 15 characters. hh = whole hours worked. t = tenths of hours worked. dd = pay whole dollars. cc = pay cents. Process: calculate gross pay. Input and output numbers are character format. Arithmetic is in binary format. Output: name gross pay - 2 decimal places rounded. Name is first 15 positions starting @ position 1. Gross salary starts in 3rd position after name. Gross salary has no editing characters ($ , .).
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74

Literals Avoid the need for separate DC statements. Use "=" instead of a "DC". e.g. L 3,=F'100'
Address constant literals allow for multiple literals of different types in one statement. e.g. MVC REPORT(6),=AL3(C'DAY',X'F3F1F0')
75

LTORG - Begin Literal Pool Use the LTORG instruction so that the assembler can collect and organize literals into a literal pool to be printed at the bottom of the program. Be sure to code the LTORG at the end of the program just before the FINIS. Examples:
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT 000398 316 LTORG 000398 0000033E00000341 317 =A(TT2,TT3,TT4) 0003A0 00000350 0003A4 C1D3D3F1F2F3 318 =AL3(C'ALL',X'F1F2F3') 0003AA D7D7 319 =C'PP' 0003AC 5C 320 =P'5' 0003AD C1D3D3 321 =AL3(C'ALL') 0003B0 C1D3D3 322 =C'ALL' 323 FINIS 324 END
76

Load Multiple Registers INITFLDS DC DC DC DC F'1' F'2' F'3' F'4'
LM
R4,R7,INITFLDS
Reg 4 before: 00 00 00 00
Reg 4 after: 00 00 00 01
Reg 5 before: 00 88 12 FF
Reg 5 after: 00 00 00 02
Reg 6 before: 00 AB CD 00
Reg 6 after: 00 00 00 03
Reg 7 before: 00 FF 01 00
Reg 7 after: 00 00 00 04
77

Store Multiple L L L STM R2,=F'1' R3,=F'2' R4,=F'3' R2,R4,SAVEREGS
Before: 00 00 00 00
After: 00 00 00 01
SAVEREGS
SAVEREGS
Before: 00 88 12 F0
After: 00 00 00 02
SAVEREGS+4
SAVEREGS+4
Before: F1 FE 82 17
After: 00 00 00 03
SAVEREGS+8
SAVEREGS+8
78

Define Constant - Character Data CONST1 DC CONST1 C'ABC'
C1 C2 C3
CONST2 DC CONST2
CL3'NE'
D5 C5 40
CONST3 DC CONST3
CL3'ABCD'
C1 C2 C3
CONST4 DC CONST4
3C'5'
F5 F5 F5
CONST5 DC CONST5
2CL2'ABC'
C1 C2 C1 C2
79

Define Constant - Character Data To have one apostrophe and one ampersand character to appear, you must code two of them in the define constant instruction.
APOSTR
DC APOSTR
C'''' 7D
AMPERS
DC AMPERS
C'&&' 50
ANB
DC ANB
C'A&&B' C1 50 C2
ASNBS
DC ASNBS
C'A''S && B''S' C1 7D E2 40 50 40 C2 7D E2
80

Define Constant - Binary Data BINAR1 DC B'101' 0000 0101
BINAR1
BINAR2
DC
B'1111000001' 0000 0011 1100 0001
BINAR2
BINAR3
DC
2B'101' 0000 0101 0000 0101
BINAR3
BINAR4
DC
BL1'111100001' 1110 0001
BINAR4
81

Define Constant - Hexadecimal Data HEX1 HEX1 DC X'123' 01 23
HEX2 HEX2
DC
2X'B' 0B 0B
HEX3 HEX3
DC
XL2'ABCDE' BC DE
HEX4 HEX4
DC
2X'A1C2' A1 C2 A1 C2
HEX5 HEX5
DC
XL4'C12' 00 00 0C 12
82

Insert Character
The leftmost byte at the address specified in operand 2 is placed in the rightmost byte of the register specified in operand 1.
IC
R7,FIELDC
Reg 7 before: FF FF FF E4
FIELDC before: 11 22 33 44
Reg 7 after: FF FF FF 11
FIELDC after: 11 22 33 44
83

Store Character The right-most byte of the register specified as operand one is copied to the location designated by operand two.
STC
R5,FIELDF+2
Before: 10
Reg 5
FF
FF
E4
F1
F2
C1 C2
FIELDF
After: 10
Reg 5
FF
FF
E4
F1
F2 E4 C2
FIELDF
84

Insert Characters Under Mask
ICM R1,M3,D2(B2)
The Insert Characters Under Mask copies N bytes (N <= 4) into a register. The number of bytes copied and their relative positions in the register are specified in the second operand of the instruction, the "mask". The number of bytes that are inserted is equal to the number of 1's in the mask. The relative position of the bytes in the register is determined by the relative position of 1's in the mask, left-to-right, one-to-one.
ICM
R4,B'1100',SAVE
Before
AB 01 8C 00
REG 4
09 FF E9 86
SAVE
After
09 FF 8C 00
REG 4
09 FF E9 86
SAVE
85

Store Characters Under Mask
STCM R1,M3,D2(B2)
The Store Characters Under Mask copies N bytes (N <= 4) from a register into memory. The number of bytes copied and their relative positions in the register are specified in the second operand of the instruction, the "mask". The number of bytes that are stored is equal to the number of 1's in the mask. The relative position of the bytes in the register is determined by the relative position of 1's in the mask, left-to-right, one-to-one.
STCM
R4,X'A',SAVE
Before
01 23 AB CD
REG 4
E1 E2 E3 E4
SAVE
After
01 23 AB CD
REG 4
01 AB E3 E4
SAVE
86

Equates Replace numbers with symbolic names. Replace addresses with symbolic names. Compute expressions whose values are unknown or difficult to calculate. Provide an easy means of changing an assembly-time constant. Equate generates no bytes in the object module. Examples:
REG15 EQU 15
EQ1 EQU INPUT EQ2 EQU INPUT+82 * NUMERIC TABLE STARTS HERE TABLE DC F'1' DC F'2' DC F'3' DC F'4' DC F'5' TBLEN EQU *-TABLE NMBRITMS EQU (*-TABLE)/4 (OR) NMBRITMS EQU TBLEN/4
last updated 12/29/99
87

Move Immediate Instruction
MVI
The Move Immediate copies one byte of data from the I2 field to the location designated by the 1st operand. The I2 data is assembled into byte one of the instruction.
MVI D1(B1),I2
88

Move Immediate Example VAL1 MVI DC C'ABCDE'
VAL1,C'*'
VAL1 before: A B C D E
VAL1 after: * B C D E
MVI
VAL1+3,C'*'
VAL1 before: * B C D E
VAL1 after: * B C * E
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90

EXERCISE #4 PROGRAM 4. Input: rate dd.cc (actual decimal point). hours hh.t (actual decimal point). name. Message: b@hh.tdd.ccname+ name is max of 15 characters. hh = whole hours worked. t = tenths of hours worked. dd = pay whole dollars. cc = pay cents. Process: calculate gross pay. Input and output are character format. Arithmetic is in binary format (use literals). Output: name gross pay daily pay average.
NAME: NNNNNNNNNNNNNNN PAY: DDDDCC DAILY: DDDDCC
Name is first 15 positions starting @ position 1. Salary figures have no editing characters ($ , .). Report Header = GROSS PAY REPORT followed by a blank line. 2 spaces before PAY and DAILY.
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Branching Branch instructions are used in re-directing the flow of the program. BAL BALR BAS BASR BC BCR BCT BCTR BXLE BXH Branch and Link Branch and Link Register Branch and Save Branch and Save Register Branch on Condition Branch on Condition Register Branch on Count Branch on Count Register Branch on Index Low or Equal Branch on Index High
93

The Condition Code The Condition Code is a value represented by two bits within the Program Status Word (PSW), bits 18 and 19. The Condition Code is set to 0, 1, 2, or 3 depending on the result obtained in executing certain instructions. The Condition Code reflects such conditions as zero, nonzero, 1st operand high, operands equal, 1st operand low, and overflow. Once set, the Condition Code remains unchanged until modified by an instruction that causes a different value to be set. Condition Codes After arithmetic instructions: 00 - result was 0 01 - result was < 0 (negative) 10 - result was > 0 (positive) 11 - overflow situation After compare instructions: 00 - operands equal 01 - first operand low 10 - first operand high
94

Branch on Condition There are two varieties of 'branch on condition' instructions: BC and BCR. The format of the BC instruction is:
BC M1,D2(X2,B2)
The first operand always specifies a mask value. The second operand is a memory address to be branched to if the condition is met. e.g. BC
8,FOUND
The format of the BCR instruction is:
BCR
M1,R2
As in the BC, the first operand of the BCR is always a mask value. The second operand is used quite differently however. The second operand is a register that must have been loaded with the branch-to address prior to executing the BCR. If the condition is met, branching will occur to the specified address in the R2 operand. Refer to the Enterprise Systems Architecture/390 Reference Summary for condition codes and their corresponding mask values.
95

Branch on Condition S BCR R1,FULL 2,R7
This code checks for CC = 2 (0010) and branches to the address in register 7 if the condition is true.
A BC BC
R1,FULL 8,ZERO 4,MINUS
This code checks for condition of zero or negative and branches accordingly. Positive condition results in fall-thru.
C BC
R1,FLDA 12,ALOEQ
This code checks for 2 settings at once - low and equal, and branches accordingly.
96

Branch on Condition - No Operation (NOP)
A "no-operation" is an instruction that, when executed, does not cause any action to be taken by the hardware except the normal incrementing of the location counter, e.g. a branch instruction that will never branch. LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT 00002E 4700 810C 00112 48 NOP TADF Above, the next sequential instruction would be executed. This is called a "no-operation". It can be used for various purposes. Example: CKLIST
NOP OI . . CONTINUE CKLIST+1,X'F0' Code in this area will be executed only once and will be branched around in succeeding executions.
Thou Shalt NOT!!!

CONTINUE EQU *
(Fact be know, you could not get the code above to run on the TPF system because of Protect Keys.)
97

Branch on Index Low or Equal BXLE
Index Register
R1,R3,D2(B2)
Branch address
Increment Register
When a BXLE instruction is executed, three things occur during the iteration of the loop: 1. Incrementing the index register. 2. Counting the number of iterations of the loop. 3. Testing to see whether the loop should be repeated. An increment is added to the first operand and the sum is compared with a comparand (the limit register). Subsequently, the sum is placed in the first operand location. When the sum is low or equal, the instruction address in the current PSW is replaced by the branch address (the second operand is used as the branch address). The first operand and the increment are in the registers specified by R1 and R3. The comparand register number is odd and is either one larger than R3 or equal to R3. The branch address is computed before the addition and comparison.
98

Branch on Index Low or Equal Object: to add the corresponding numbers of Table A to Table B and place the sums in corresponding elements of Table C. Using 3 Registers
LM EQU L A ST BXLE . DS DS DS R3,R5,=F'0,4,16' R3 = Index Reg. * R4 = Incr. Reg. R0,TABA(R3) R5 = Limit Reg. R0,TABB(R3) R0,TABC(R3) R3,R4,MORE 5F 5F 5F
MORE
TABA TABB TABC
Using 2 Registers
LM EQU L A ST BXLE . DS DS DS R4,R5,=F'-12,4' * R0,TABA+12(R4) R0,TABB+12(R4) R0,TABC+12(R4) R4,R5,MORE 5F 5F 5F R4 = Index Reg. R5 = Incr. & Limit
MORE
TABA TABB TABC
99

Branch on Index High - BXH Works in the same manner as the BXLE but checks for index high rather than low or equal. Object: to add the corresponding numbers of Table A to Table B and place the sums in corresponding elements of Table C. Using 3 Registers
LM R3,R5,=F'0,-4,-20' EQU * L A ST BXH . . . DS DS DS R0,TABA+16(R3) R0,TABB+16(R3) R0,TABC+16(R3) R3,R4,MORE R3 = Index R4 = Incr. R5 = Limit
MORE *
TABA TABB TABC
5F 5F 5F
100

Load and Test Register
The second operand is placed unchanged in the first operand location, and the sign and magnitude of the second operand is used to determine and set the condition code (refer to the Principles of Operation for more details).
Condition code settings: 0 - the result is zero 1 - the result is less than zero 2 - the result is greater than zero 3 - not used
LTR
R4,R2
Reg 4 before: 00 81 34 77
Reg 2 before: 00 00 12 11
Reg 4 after: 00 00 12 11
Reg 2 after: 00 00 12 11
In this case, the condition code is set to 2. Note: when the R1 and R2 fields designate the same register the operation is simply a test with no data movement.
101

Load Negative Register
The twos complement of the absolute value of the second operand is placed in the first operand location. Negative numbers remain unchanged. Zero remains unchanged.
LNR
R4,R2
Reg 4 before: 00 81 34 77
Reg 2 before: 00 00 12 11
Reg 4 after: FF FF ED EF
Reg 2 after: 00 00 12 11
102

Load Positive Register
The absolute value of the second operand is placed in the first operand location. Positive numbers remain unchanged. Zero remains unchanged.
LPR
R4,R2
Reg 4 before: 00 00 00 00
Reg 2 before: FF FF AB AB
Reg 4 after: 00 00 54 55
Reg 2 after: FF FF AB AB
103

Load Complement Register
The twos complement of the second operand is placed in the first operand location. Zero remains unchanged.
LCR
R4,R2
Reg 4 before: 00 00 00 04
Reg 2 before: 00 00 54 55
Reg 4 after: FF FF AB AB
Reg 2 after: 00 00 54 55
104

Algebraic Compare Instructions To compare two integers algebraically, one of them must be in a register while the other can be in a register or at a memory location. The operands are compared as signed 32-bit binary integers and all the rules of algebra apply. Compare Registers - CR Compare Fullword - C Compare Halfword - CH
105

Compare Registers
CR
R3,R4
00
REG 3
00
00
0A
00
REG 4
00
00
C8
CC = 1
CR
R4,R5
00
REG 4
00
00
C8
FF
REG 5
FF
FF
FF
CC = 2
106

Compare Fullword
R3,STORAGE
00
REG 3
80
59
34
00
00
FF
F9
STORAGE
CC = ?
107

Compare Halfword AMT1 AMT2 L CH DC DC F'6' H'-6'
R3,AMT1 R3,AMT2
CC = ?
108

EXERCISE #5 PROGRAM 5. Input: rate dd.cc (actual decimal point). hours hh.t (actual decimal point). name. Message: b@hh.tdd.ccname+ name is max of 15 characters. hh = whole hours worked. t = tenths of hours worked. dd = pay whole dollars. cc = pay cents. Process: calculate gross pay. Input and output are character format. Arithmetic is in binary format (literals optional). Hours > 40 = 1.5 x standard rate (included in gross). Output: name gross pay overtime.
NAME: NNNNNNNNNNNNNNN PAY: DDDDCC OVERTIME: DDDDCC
Name is first 15 positions starting @ position 1. Salary figures have no editing characters ($ , .). Report Header = GROSS PAY REPORT centered. and followed by blank line. 2 spaces before PAY and OVERTIME.
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110

Integer Logical Compare Instructions To compare two integers logicically, one of them must be in a register while the other can be in a register or at a memory location. The operands are compared as unsigned 32-bit binary integers. Compare Logical Registers - CLR Compare Logical Fullword - CL Compare Logical under Mask - CLM
111

Compare Logical Compares the contents of a register and the contents of a memory location.
CL R3,SAVE
00
SAVE
00
00
01
FF
REG 3
FF
FF
FE
CC = 2
1st operand high
112

Compare Logical Registers
CLR R3,R4
00
REG 3
00
C1
C2
00
REG 4
00 D1 D2
CC = 1
1st operand low
113

Compare Logical Characters Under Mask
CLM R1,M3,D2(B2)
The Compare Logical Characters Under Mask compares two N-byte strings (N <= 4), the first string is in the register designated by the first operand. The second string is in the memory location designated by the second operand.
CLM
R5,B'0001',=X'00'
00 C3 FF D5
REG 5
00
Memory
CC = 2
114

Bit String Logical Compare Instructions In comparing two byte strings of equal length, the comparison starts at the left-most (high order) end of each string and proceeds byte by byte to the right, comparing the bytes from corresponding positions until one of two situations occur: 1. Either two bytes (one from each string) are found to be unequal, or 2. the strings are exhausted and all pairs of bytes are found to be equal. The result of the compare is returned in the condition code.
115

CLI - Compare Logical Immediate Compares two 1 byte strings. The first string is in the memory location designated by the first operand. The second string is in the immediate data field of the instruction itself.
C4
FIELD
C2
C6
C4
CLI CLI CLI CLI
FIELD,C'D' FIELD+1,C'D' FIELD+2,C'D' FIELD+3,C'D'
CC CC CC CC
= = = =
0 1 2 0
116

CLC - Compare Logical Characters Compares two 'N byte' strings where N <= 256. The first string is in the memory location designated by the first operand. The second string is in the memory location designated by the second operand.
FLDA FLDB FLDC CLC CLC CLC
DC DC DC
C'JOHNSON' C'JOHNSEN' C'JOHNSUN' CC = ? CC = ? CC = ?
FLDA,FLDB FLDB,FLDC FLDC,FLDA
117

Shift Instructions
SLDA, SLDL, SLA, SLL, SRDA, SRDL, SRA, SRL
General Rules: 1. All shift instructions have an RS format. 2. The 2nd operand address is not used to address data. Instead, the low order 6 bits of the address computed are used to determine the shift value (number of bits to be shifted). 3. Bits 12-15 of the object code are not used. Algebraic shifts: 1. First operand is treated as a 31 or 63 bit integer. 2. The sign bit will not change. 3. The condition code is set after execution. Logical shifts: 1. First operand is treated as a 32 or 64 bit integer. 2. The sign bit can change, no inspection is made. 3. The condition code is not affected by the instruction.
118

SLA - Shift Left Algebraic
SLA
R5,8(R0)
Before 00 7F 0A 72
REG 5
After 7F 0A 72 00
REG 5
119

SRA - Shift Right Algebraic
SRA
R5,0(R4)
Before 80 64 E6 00
REG 5
00 00 00 0C
REG 4
After FF F8 06 4E
REG 5
00 00 00 0C
REG 4
120

SLDA - Shift Left Double Algebraic
SLDA R4,8(R6)
Before
00 00 B6 E8
REG 4
BE E8 01 00
REG 5
00 00 00 08
REG 6
After
36 E8 BE E8
REG 4
01 00 00 00
REG 5
00 00 00 08
REG 6
The 63 numeric bits of the even-odd register pair are shifted to the left, leaving the sign bit unchanged. Because a significant bit is shifted out of bit position 1 of register 4, overflow is indicated by setting condition code to 3.
121

SRDA - Shift Right Double Algebraic
SRDA R4,4(R6)
Before
80 00 C8 B4
REG 4
FF FF FF FF
REG 5
00 00 00 08
REG 6
After
FF F8 00 0C
REG 4
8B 4F FF FF
REG 5
00 00 00 08
REG 6
122

SLL - Shift Left Logical
SLL R5,8(R4)
Before 00 00 0A BC
REG 5
00 00 00 04
REG 4
After 00 AB C0 00
REG 5
00 00 00 04
REG 4
123

SRL - Shift Right Logical
SRL R5,8(R4)
Before 00 AB C0 00
REG 5
00 00 00 04
REG 4
After 00 00 0A BC
REG 5
00 00 00 04
REG 4
124

SLDL - Shift Left Double Logical
SLDL R4,8(R6)
Before
00 00 B6 E8
REG 4
BE E8 01 00
REG 5
00 00 00 08
REG 6
After
B6 E8 BE E8
REG 4
01 00 00 00
REG 5
00 00 00 08
REG 6
125

SRDL - Shift Right Double Logical
SRDL R4,4(R6)
Before
80 00 C8 B4
REG 4
FF FF FF FF
REG 5
00 00 00 08
REG 6
After
00 08 00 0C
REG 4
8B 4F FF FF
REG 5
00 00 00 08
REG 6
126

Extended Mnemonics In order to make checking condition codes a little easier, instructions called extended mnemonics have been developed. These instructions actually cause a BC instruction to be executed but you do not have to specify the mask field value. The name implies the usage. e.g. BE is equal to BC 8,FOUND FOUND
After compare instructions (A:B) BH BL BE BNH BNL BNE or or or or or or BHR BLR BER BNHR BNLR BNER Branch on A High Branch on A Low Branch on A Equal B Branch on A Not High Branch on A Not Low Branch on A Not Equal B
127

Extended Mnemonics After arithmetic instructions BP BM BZ BO BNP BNM BNZ BNO or or or or or or or or BPR BMR BZR BOR BNPR BNMR BNZR BNOR Branch on Plus Branch on Minus Branch on Zero Branch on Overflow Branch on Not Plus Branch on Not Minus Branch on Not Zero Branch on No Overflow
After the TM (Test Under Mask) instruction BO BZ BM BNO BNZ BNM or or or or or or BOR BZR BMR BNOR BNZR BNMR Branch if Ones Branch if Zeros Branch if Mixed Branch if Not Ones Branch if Not Zeros Branch if Not Mixed
128

Define Constant - Address Constant - "A" Type Gives the address of the desired symbol as a binary integer. Represents addresses internal to the program. Constant is enclosed in parentheses rather than apostrophes. The address appears in a four byte field. FORMAT: label DC A(symbol)
ADDR1 ADDR2 STMT 452 453 SOURCE STATEMENT LIT2 DC LIT3 DC
LOC OBJECT CODE 000485 C4C1E8 CL3'DAY' 000488 D4E2D7 CL3'MSP' 00048B 00 00048C 00000485
454
ADDRESS DC A(LIT2)
129

Define Constant - Address Constant - "V" Type This is an external address constant; e.g. it reserves space in the program for an address outside the program in which it resides. It is normally used to refer symbolically to the entry point of another program to allow for "calling" or passing control to that program. A value of zero is assembled into the space reserved for the V-type constant; the correct relocated value of the address is inserted into this space by the linkage editor before your program is loaded. FORMAT:
LOC 000485 000488 00048B 00048C 000490
label
DC
V(PROG2)
STMT SOURCE STATEMENT DC CL3'DAY' DC CL3'MSP' DC A(LIT2)
OBJECT CODE C4C1E8 D4E2D7 00 00000485 00000000
ADDR1 ADDR2
452 LIT2 453 LIT3 454 ADDRESS
455 PROGADDR DC V(PROG2)
130

Assembly Language Coding (ALC) Part 2

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Assembly Language Coding (ALC) Part 2

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IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

C'A''S && B''S' C1 7D E2 40 50 40 C2 7D E2

IBM Mainframe Assembler Language Coding

B'1111000001' 0000 0011 1100 0001

2B'101' 0000 0101 0000 0101

BL1'111100001' 1110 0001

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

last updated 12/29/99

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

The format of the BCR instruction is:

last updated 12/29/99

IBM Mainframe Assembler Language Coding

R1,FULL 8,ZERO 4,MINUS

IBM Mainframe Assembler Language Coding

Thou Shalt NOT!!!

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

TABA TABB TABC

TABA TABB TABC

IBM Mainframe Assembler Language Coding

TABA TABB TABC

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

1st operand high

IBM Mainframe Assembler Language Coding

1st operand low

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

CLI CLI CLI CLI