Serial Flash Controll

Serial Flash controller Generic IP block functional specication
Preliminary Data
Owner Name E-mail Division Site Sanjeev Varshney/Parul Agarwal Information classified Confidential - Do not copy (See last page for obligations) sanjeev.varshney@st.com parul.agarwal@st.com HED HVD R&D Greater Noida
Abstract
This document describes the functionality of the Serial Flash controller in detail. The Serial Flash controller is used to interface with the standard SPI protocol-based Serial Flash devices.
Key words
Quad, FSM, CS, DI, DO, Hold, WP, dual output, SPI
Revision history
Date Revision Author Modication description Updated spec for the new read mode (for improving performance of read accesses up to 40 Mbits/sec). Some general quality related changes. Added section on changing the SPI mode and added a bit in the SPI_MODE_SELECT register to facilitate the mode-change sequence. Updated with respect to the review comments received from G. Mathew. Added section on the Dual output mode support and corresponding pin changes. Open points: write and erase support.
20-Dec-2005
1.0
Sanjeev Varshney
13-Feb-2006
1.1
Deboleena Minz/Sanjeev Varshney
25-Oct-2007
1.2
Parul Agarwal/Sanjeev Varshney
June 2011
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/77
www.st.com
Serial Flash controller functional specification
Date
Revision
Author
Modication description Updated the quad mode and write/erase support (fast sequence mode). Reorganized the document. Updated for integration guidelines. Reorganized the document in new format, more aligned to new spirit template. Open points/future enhancements: - separate clock input for the Serial Flash controller (today it is same as the EMISS system clock). - Macronix memories latest mode, that is, quad DDR mode 75 Mbits /sec) to be dened. Updated document with drivers team feedback and aligned with validation application note. Updated the description of the SPI_CLK_DIV, SPI_FAST_SEQ_FLASH_STA_DATA and SPI_STATUS_WR_TIME registers. Updated the SPI_CONFIG_DATA register with footnote. Added detail in the Section 4.1.9: Fast sequence boot mode. Added independent SPI clock details. Ported in latest spirit based template and incorporated feedbacks received from different people like Linux team, Validation team, verication team. Updated by documentation team for documentation style guide adherence. Updated to add 32 bit address serial ash support. Register description SPI_FAST_SEQ_ADD_CFG is updated. Updated to add the reset state of pads to z Note added in the spi_fast_seq_data register
15-May-2008
1.3
Sanjeev Varshney/Parul Agarwal
06-Jul-2009
2.0
Parul Agarwal
07-Jul-2009
2.1
Parul Agarwal
31-Jul-2009
2.2
Parul Agarwal
17-Jun-2010
3.0
Parul Agarwal
14-Sep-2010
3.1
Shilpi Jain
24-Mar-2011 16-May-2011 21-June-2011
3.2 3.3 3.4
Parul Agarwal Parul Agarwal Parul Agarwal
2/77
Rev B
Information classified Confidential - Do not copy (See last page for obligations)
Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 Referenced documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IP block name and features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 2.2 IP block name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 IP block context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 3.1.2 3.1.3 Pad connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Comms integration guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supported opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 3.3
Hardware interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed functional specication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Normal functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Modes supported by the Serial Flash controller . . . . . . . . . . . . . . . . . . 14 Architecture of Serial Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Commands supported by different modes of the controller . . . . . . . . . . 16 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Fast read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Dual output (x2) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contiguous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Fast sequence mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fast sequence mode functioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single-page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Single-page read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Single-page write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Multiple-page sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read multiple page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Multiple-page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Chip select bit functioning for DATA phase in single- and multiple-page sequences 29
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Contents 4.1.9
Serial Flash controller functional specification Fast sequence boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Boot flow from system prospective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fast sequence boot mode flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Registers required for the fast sequence boot mode . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.10 Changing modes of Serial Flash controller . . . . . . . . . . . . . . . . . . . . . . 33
Fast sequence mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.2 4.3 4.4 4.5
Error conditions and error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5.1 4.5.2 Memory requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interrupt behavior and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.6
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.6.1 4.6.2 Hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1 5.2 5.3 Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Generated clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 External hardware interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Routers and interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1 7.2 Local interconnect (routers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Point-to-point connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 9
Pin group list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1 Address blocks and sub-blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.1 9.1.2 Summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Rev B
Contents
10
Software driver interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.1 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.1.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11
Patents and licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Appendix A Serial Flash controller requirements . . . . . . . . . . . . . . . . . . . . . . . . 72

A.1 Performance calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
A.1.1 A.1.2 A.1.3 A.1.4 Contiguous mode versus normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 72 Dual output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Fast sequence mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Performance comparison at a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Information classified Confidential - Do not copy (See last page for obligations) Assumptions made for the above calculations . . . . . . . . . . . . . . . . . . . . . . . . . . .72
A.2
Flashes supported by the Serial Flash controller . . . . . . . . . . . . . . . . . . . 73
Rev B
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Introduction
Introduction
This document describes the Serial Flash controller module housed inside the EMI subsystem (EMISS). The EMISS has a separate serial bus to interface with the Serial Flash devices. The Serial Flash controller is designed to communicate with the Serial Flash devices.
1.1
Referenced documents

1.2
Glossary
FSM T2 Quad EMISS CS DI DO Hold WP I/P O/P BIDI SPI Contig mode NA Fast sequence mode STBus Type 2 Quadruple mode of Serial Flash EMI subsystem Chip select of Serial Flash Data in port of Serial Flash Data out port of Serial Flash Hold pin of Serial Flash Write protect pin of Serial Flash Input Output Bidirectional Serial peripheral interface Contiguous mode Not applicable
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Rev B
Atmel Serial Flash memory, AT25F4096 datasheet Atmel Serial Flash memory, AT25FS040 datasheet ST Serial Flash memory, M25P40 datasheet SST Serial Flash memory, SST25LF020A datasheet Winbond Flash memory, W25x10 datasheet Macronix Flash datasheet, MX25L1635D SST Serial Flash datasheet, S71359 Winbond Serial Flash datasheet, W25X10_20_40_80b Winbond Quad Serial Flash memory, W25Q80_16_32b
IP block name and features list
2
2.1
IP block name and features list

IP block name
Table 1.
Vendor st.com
SPIRIT identication of serial_ash_controller

Library C6 Name serial_ash_controller Version 3.0
2.2
Features list
The main features of the Serial Flash controller are: Serial Flash boot support: x1 and x2 boot support using the legacy mode x1, x2, x4 boot support using the fast sequence boot mode
Fast sequence mode features: Read, write and erase support x1, x2 and x4 support for different operations Flexibility to support any available device size Programmable engine to support various Serial Flash devices Variable size data transfer support Capability to support 32 bit address Serial Flash devices Pacing signal support to communicate with FDMA/CPU for large data transfers Support for unaligned access Support for mode 0 (CPOL=0, CPHA=0) of the SPI protocol Flexibility to operate serial bus on various frequencies with different system clocks using the programmable clock division ratio Software write protect (WP) supported
Note:
x1, x2 and x4 refer to the data pad conguration of the Serial Flash. For more details, refer to Section 3.1.1: Pad connections.
Rev B
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System overview
3
3.1
System overview
IP block context
The Serial Flash controller is integrated within the EMI subsystem (EMISS). The Figure 1 shows the EMISS in a SoC context. However, the IP can also be delivered as a stand-alone. The Serial Flash controller provides seamless interface to the Serial Flash device using the SPI protocol. The Serial Flash controller is accessible to system initiators through the Type2 interface of the EMISS. The main function of the Serial Flash controller is to take the STBus requests coming from the interconnect side and convert them into serial access (SPI protocol) to communicate with the Serial Flash devices.
Figure 1.
EMISS system view
CPU Serial bus IC EMISS Padlogic Parallel bus FDMA
SoC
The Figure 2 shows the system-level view of the Serial Flash controller embedded inside the EMISS. Figure 2. Serial Flash controller inside EMISS
CS FDMA SPI_CLOCK EMI DI Type2 IC RGV EMI buffer Router Serial Flash controller Padlogic DO HOLD Serial Flash
CPU
NAND
WP
EMISS
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Rev B
System overview
3.1.1
Pad connections
A typical Serial Flash can have different data bus widths in different congurations. For example in: x1 pad conguration: CS; SPI_CLOCK; and unidirectional DI and DO pads are used x2 pad conguration (dual output - legacy mode) CS; SPI_CLOCK; one unidirectional DI pad; and one bidirectional data pad DO are used x2 pad conguration (dual I/O - fast sequence mode) CS; SPI_CLOCK; and two bidirectional data pads DI and DO are used x4 pad conguration CS; SPI_CLOCK; and four bidirectional data pads DI, DO, HOLD and WRITE PROTECT are used These different congurations (x1, x2, x4) of Serial Flash decides the pad requirement at the SoC level. The Serial Flash controller generates six enable signals corresponding to six SPI pads. These enable signals are used to control the pad direction for all modes of the Serial Flash controller. The enables generated by the serial ash controller drives all the spi pads in input mode during reset. This is done to avoid driving the pads during reset. All the pads can be tristated at SoC level on reset for the serial ash to power on and off safely. As soon as the reset is deasserted and clock arrives the pads are put in their respective required modes. The Table 2 gives the values of the enable signals generated by the Serial Flash controller after the reset is over. Table 2.
Enables SPI_DATA_IN_ENB SPI_DATA_OUT_EN SPI_HOLD_ENB SPI_WR_PROTECT_ENB SPI_CLK_ENB SPI_CS_ENB
Polarity of enables
Value after reset Pad direction is over 0 1 1 1 1 1 Input mode Output mode Output mode Output mode Output mode Output mode
The pad requirements for different type of congurations are given in the following table:
Rev B
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System overview Table 3.

Pads x1
Pad requirements for different Serial Flash congurations

SPI_NOT_CS Output pad SPI_CLOCK SPI_DATA_IN Output pad Output pad Input pad Input pad Bidirectional pad Bidirectional pad SPI_DATA_OUT HOLD Output pad WRITE PROTECT (WP)
x2 (dual output legacy mode/FSM Output pad mode) x2 (dual I/O - fast sequence mode) x4 Output pad Output pad
Output pad Output pad
Can either be tied appropriately at the top Bidirectional pad level, or the Serial Flash controller enable signals can be used to drive Bidirectional pad inactive value 1. Bidirectional pad Bidirectional pad Bidirectional pad
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Rev B
System overview
The Figure 3, Figure 4 and Figure 6 show the pad connections for x1, x2 and x4 congurations of the Flash, respectively. Figure 3. x1 pad connection
SPI_NOT_CS SPI_CLOCK
CS SPI_CLOCK
CS CLOCK
Serial Flash controller
SPI_DATA_OUT
DO
DI
Serial Flash
SPI_DATA_IN
DI Padlogic
DO
Figure 4.
x2 pad connection (dual output mode)
SPI_CS_ENB SPI_NOT_CS CS
CS
SPI_CLK_ENB SPI_CLOCK
Serial Flash controller SPI_DATA_OUT_EN SPI_DATA_OUT SPI_DBL_DATA_IN DO DI
SPI_CLOCK
CLOCK
Serial Flash
SPI_DATA_IN
DI
DO
Padlogic
Rev B
11/77
System overview Figure 5.
Serial Flash controller functional specification x2 pad connection (dual I/O mode)
SPI_CS_ENB SPI_NOT_CS CS CS
SPI_CLK_ENB SPI_CLOCK SPI_CLOCK CLOCK
SPI_DATA_OUT_EN Serial Flash controller SPI_DATA_OUT SPI_DBL_DATA_IN DO DI
Serial Flash Information classified Confidential - Do not copy (See last page for obligations)
SPI_DATA_IN_ENB SPI_DATA_OUT_QUAD SPI_DATA_IN DI DO
Padlogic (SoC boundary)
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Rev B
Serial Flash controller functional specification Figure 6. x4 pad connection
System overview
SPI_CS_ENB SPI_NOT_CS SPI_CLK_ENB SPI_CLOCK SPI_CLOCK CLOCK CS CS
SPI_DATA_OUT_EN SPI_DATA_OUT Serial Flash controller SPI_DATA_IN_ENB SPI_DATA_OUT_QUAD SPI_DATA_IN DI DO Serial Flash SPI_DBL_DATA_IN DO DI
SPI_HOLD_ENB SPI_HOLD_OUT SPI_HOLD_IN HOLD HOLD
SPI_WR_PROTECT_ENB SPI_WR_PROTECT_OUT SPI_WR_PROTECT_IN WP WP
Padlogic (SoC boundary)
3.1.2
Comms integration guidelines

Typically, in previous SoCs, the serial bus was shared between the comms subsystem and the Serial Flash controller for different Serial Flash operations (mainly for write and erase). This sharing has to be handled at the SoC level, and is outside the scope of the Serial Flash controller. The Figure 7 shows the example glue logic required at the SoC level for managing the comms and the legacy mode of the Serial Flash controller. A system conguration register bit should be used for this purpose. For booting from Serial Flash, this bit must assign the serial bus to the Serial Flash controller, by default. After booting, the software can drive the value of this bit as required, that is, the software programs the value of this register accordingly while doing transactions from the Serial Flash controller or comms.
Rev B
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System overview Figure 7.
Serial Flash controller legacy mode and comms multiplexing logic
COMMS subsystem
COMMS_DATA_IN COMMS_CLOCK COMMS_DATA_OUT SPI_NOT_CS Padlogic /Gluue SPI_CLOCK SPI_DATA_OUT
SPI_NOT_CS SPI_CLOCK STBus EMI buffer SPI_DATA_OUT Serial Flash controller
SPI_DATA_IN
SPI_DATA_IN
EMISS
System conguration register bit
3.1.3
Supported opcodes
The different opcodes supported by different modes of the Serial Flash controller are provided in the following table: Table 4.
Modes
Opcodes supported in different modes

Boot requests FIFO requests Conguration requests LD 4 ST 4 LD 4 ST 4 LD 4 ST 4
Legacy modes Fast sequence mode
LD 4/8/16/32 N/A
N/A LD 4/8/16/32 ST 4/8/16/32 N/A
Fast sequence boot mode LD4/8/16/32
Note:
Accessing opcodes other than those mentioned above generate error conditions by setting the INIT_R_OPC signal as high.
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Rev B
System overview
3.2
Hardware interfaces
The Serial Flash controller has one Type 2 RGV target interfacing with EMI buffer through router. This interface is utilized by the CPU for booting and programming the Serial Flash controller registers to congure the IP in the required mode. The Serial Flash controller provides two DREQs (SPI_DATA_DREQ and SPI_SEQ_DREQ) to interface with FDMA/HOST. The DREQs communicate the status of the Serial Flash controller. Use the SPI_DATA_DREQ signal to move the data in and out of the FIFO. Use the SPI_SEQ_DREQ signal to program the sequence registers. Connect the SPI_DATA_DREQ and SPI_SEQ_DREQ signals with ILC to manage interrupts to the HOST. For more details, refer to Section 4.5.2: Interrupt behavior and requirements. The Figure 8 shows an example connection of DREQs with the CPU and FDMA.
Figure 8.
Serial Flash controller dreq connection
CS SPI_CLOCK FDMA EMI buffer Router SPI controller Padlogic DI DO HOLD WP Quad Serial Flash
IC CPU
EMISS
SPI_SEQ_DREQ ILC3 SPI_DATA_DREQ
3.3
Functional components
Not applicable.
Rev B
15/77
Detailed functional specification
4
4.1
4.1.1
Detailed functional specication

Normal functional behavior
Modes supported by the Serial Flash controller
The Serial Flash controller can work in the following modes: legacy modes fast sequence mode (FSM) fast sequence boot mode
After reset, the Serial Flash controller is ready to boot in the legacy normal mode. There are three legacy modes: normal mode fast read mode
dual output mode
The contiguous mode is present in addition to the three legacy modes. This is a performance enhancement mode, which can be combined with any of the three legacy modes. For more details, refer to Section 4.1.7: Contiguous mode. The Figure 9 illustrates the modes of the Serial Flash controller. These modes are described in detail in later sections. Figure 9. Serial Flash controller modes
Serial Flash controller modes
Legacy modes (read only)
Fast sequence mode (read, write and erase)
Fast sequence boot mode (read only)
Normal mode
Fast read mode
Dual output mode
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Rev B
4.1.2
Architecture of Serial Flash controller

The Serial Flash controller can be broadly divided into ve blocks: STBus interface clock divider main controller fast-sequence controller padlogic conguration block
Figure 10. Serial Flash controller architecture

Conguration block
Clock divider
SPI_CLOCK
Interconnect
STBus (RGV) interface Padlogic Main controller SPI data and enable pins to padlogic
MODE_SPI_CLK_DIV
Fast-sequence controller
The STBus interface receives STBus requests and manages responses to the interconnect. It triggers state machines of the main controller block or the fast-sequence controller block to initiate SPI transactions. The STBus interface block also recognizes conguration requests and forwards these requests to the conguration block. The conguration block handles the incoming conguration requests from the interconnect side. This block provides the read/write functionality for all the conguration registers. The main controller block is responsible for the functioning of legacy modes. The Serial Flash controller has a congurable clock divider to tune the EMISS clock for Serial Flash devices. This divider is congured through a static signal MODE_SPI_CLK_DIV<7:0> after reset, and can be programmed afterwards through the SPI_CLK_DIV register. The static signal MODE_SPI_CLK_DIV<7:0> provided at the top level of the Serial Flash controller gives exibility to different SoCs to choose any division ratio for boot. It is mandatory to tie these pins at the SoC integration level with a minimum value of divide by 8 to allow booting from slow serial devices. After booting, the SPI_CLK_DIV register can be
Rev B
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programmed to dynamically change the frequency. The clock division ratio for this register ranges from divide by 2 to 256 in steps of 2, that is 2, 4, 6, 8,......, 254 and 256. The fast-sequence controller block is responsible for handling the fast sequence mode operations. It decodes the instructions written in the fast-sequence registers and executes them sequentially. It also has a state machine to generate control signals for the fast sequence mode. This block has a FIFO embedded inside to store data. While performing Flash writes, the data to be written to the Flash is stored in this FIFO. Similarly, during Flash read operations, the data read from the Flash is stored in this FIFO. The padlogic block is responsible to re-time incoming and outgoing data signals to ease timing closure. This block also generates information regarding the stalling of the Flash interface by keeping track of the FIFO status. This block also manages serial to parallel conversion and vice-versa.
4.1.3
Commands supported by different modes of the controller

The different commands supported by different modes of the Serial Flash controller are summarized in the following table: Table 5.
Commands Write enable Write disable Normal read(03h) Fast read (0Bh) Dual output read (3Bh) Dual I/O read (fast) Quad data read Quad I/O read (fast) Page program Dual data page program Quad page program Quad page program (fast) Enable quad I/O Disable quad I/O Read status register Write status register
Modes and features supported by the Serial Flash controller

Normal mode No No Yes No No No No No No No No No No No No No Fast read mode No No No Yes No No No No No No No No No No No No No No No Dual output mode No No No No Yes No No No No No No No No No No No No No No Fast sequence mode Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Fast sequence boot mode Yes No Yes Yes Yes Yes Yes Yes No No No No Yes No Yes Yes No No No
Subsector/sector/page erase No Chip erase Block erase No No
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Rev B
4.1.4
Normal mode
By default, the Serial Flash controller is in the normal mode. This mode supports read access to the Serial Flash. This mode supports command (03h) of Serial Flash devices. Although the opcodes supported are higher than 4 bytes, the granularity of one SPI transaction is only 4 bytes. That is, the Serial Flash controller breaks opcodes greater than 4 bytes into 4 bytes access, aligned at the 4 bytes boundary. Due to this, the Serial Flash controller consumes 64 SPI_CLOCK cycles (32 cycles for opcode and address) for fetching every 4 bytes of data from the Flash. For better efciency, this mode can be combined with contiguous mode. For more details, refer to Section 4.1.7: Contiguous mode.
4.1.5
Fast read mode

Some Serial Flash devices support the fast read mode, that is, operations at higher frequencies. The command (0Bh) for the fast read mode is different when compared to the normal mode. This opcode allows reads at bit rates up to 50 MHz. The FAST_READ bit of the SPI_MODE_SELECT register needs to be set to congure the fast read mode. After selecting the fast read mode, the clock divider value can be adjusted to provide higher frequency of operation as dened by the Serial Flash. This mode is benecial in case of Serial Flash devices where the fast read mode runs at a higher frequency when compared to the normal mode. For better efciency, this mode can be combined with contiguous mode. For more details, refer to Section 4.1.7: Contiguous mode. For further details on the fast read mode, refer to the Serial Flash datasheet.
4.1.6
Dual output (x2) mode

The dual output uses a different instruction (3Bh). The data is output on the DI and DO pins by the Flash. This mode doubles the data transfer rate as compared to the normal mode. The execution of the dual output mode is as follows: instruction 3Bh (8 bits) address of the required location (24 bits) dummy bits (8 bits to provide the additional set-up time to memory) data output by the Flash on the DI and DO pins alternatively at the falling edge of the SPI_CLOCK Program the DUAL_OUTPUT_MODE bit of the SPI_MODE_SELECT register to congure the Serial Flash controller in the dual output mode. The Figure 11 shows the command and address given by the Serial Flash controller and data returned by the Serial Flash. Congure the Serial Flash controller in the dual output mode with the contiguous read mode in high-speed applications where the data needs to be quickly downloaded from Flash.
Rev B
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Figure 11. Dual output read mode instruction sequence
SPI_CLOCK
CS
8 bits
24 bits
8 bits
DI switches to output
DI Instruction Address Dummy bits
DO
7 5 Dual output instruction sequence
3 1
Data output from Flash
4.1.7
Contiguous mode
The contiguous mode is the performance enhancement mode. When enabled, it improves the performance of the Serial Flash controller for back-to-back contiguous accesses made to Flash memory locations. To congure the IP in the contiguous mode, program the CONTIG_MODE bit of the SPI_MODE_SELECT register. The contiguous mode is not a stand-alone mode. It must be selected in conjunction with any of the legacy modes. The possible congurations of the legacy modes with the contiguous mode are given in the SPI_MODE_SELECT register. In this mode, if contiguous and back-to-back requests are made to the Serial Flash controller, it performs the complete read access simultaneously, thereby, saving on the command and address cycles for multiple requests. As a result there is no additional overhead of address and command cycles for every four data bytes. The contiguous mode reads are benecial only when STBus asserts back-to-back contiguous Flash read requests to the Serial Flash controller. In case a non-contiguous read or register access is made in between contiguous reads, the Serial Flash controller restarts a new SPI sequence, that is command, address and data read cycles are asserted once again. The Serial Flash controller treats the STBus requests as back-to-back when the next STBus request arrives within 8 SPI_CLOCK cycles. Requests are contiguous when consecutive STBus transaction addresses are 4 bytes apart, that is, address of the nth transaction = address of (n-1) transaction + 4.
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Rev B
The example waveforms of the contiguous and normal modes are given in the following gure: Figure 12. Normal and contiguous mode waveform comparison
CLOCK
INIT_REQ SPI_CLOCK
SPI_NOT_CS OPC[8] SPI_VALIDNEXTCYCLE
64 SPI clock cycles
64 SPI clock cycles
ADDR[24]
DATA[32]
OPC[8]
ADDR[24]
DATA[32]
INIT_R_DATA
xxxxh
abcd
wxyz
Normal mode read
CLOCK
INIT_REQ
SPI_CLOCK
INIT_ADDR(31:2) 000h OPC[8] ADDR[24]
001h
002h
003h
SPI_NOT_CS
DATA[32+32+.......until back-to-back contiguous request arrive]
SPI_VALIDNEXTCYCLE INIT_R_DATA xxxxh abcd wxyz 1234
Normal mode with contiguous mode read
The reads from non-contiguous locations with the CONTIG_MODE bit set is slower as compared to the normal mode. This is because the Serial Flash controller always pre-fetches 1 byte of data from the Serial Flash for every STBus request. This extra byte fetched is discarded as it is not required. This impacts the performance in case of noncontiguous requests. Thus, it is recommended to use normal mode when reading from the non-contiguous locations.
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INIT_ADDR(31:2) 000h
001h
002h
4.1.8
Fast sequence mode

The fast sequence mode offers a exible, software programmable engine, which may be used to perform different Serial Flash operations including read, write and erase. It also has the capability to perform x1, x2 and x4 Serial Flash congurations. The fast sequence mode has the exibility to support variable size data transfers and various available device sizes. It also supports pacing signals to communicate with FDMA/HOST for large data transfers. The fast sequence mode has a set of instructions and operands to execute different Serial Flash operations. Software can program any intended sequence in a set of registers using these instructions and operands. However, the software should always program correct sequences as per the Serial Flashes supported by the Serial Flash controller. In case the software programs any incorrect or invalid sequence, the Serial Flash controller does not execute the events correctly.
Fast sequence mode functioning

The fast sequence mode enables the Serial Flash controller to execute multiple command/address/data sequences simultaneously based on the conguration of sequence registers. The Serial Flash controller executes the instructions programmed in the fast sequence mode registers one-by-one. Once the complete sequence of instructions is over, the SPI_SEQ_DREQ signal is asserted and the SPI_FAST_SEQ_STA register is updated. The software reads this information and programs a new sequence. The software must program a new sequence only when the Serial Flash controller has completed the previous sequence as indicated by the SPI_FAST_SEQ_STA register. Ensure that correct address, command and instruction sequences are programmed in the sequence registers so that the correct operation is performed on the Serial Flash. The example of programming sequence registers is provided in the later sections. The fast sequence mode is selected by setting the FAST_SEQ_MODE bit of the SPI_MODE_SELECT register. Other fast sequence mode registers such as command, address and sequence registers must also be written as required. The operation starts when the START_SEQ_BIT of the SPI_FAST_SEQ_CFG register is written. The SPI_FAST_SEQ_STA register reects that the sequence execution is in progress and sets the FAST_SEQ_STA bit to 1. Note: The Serial Flash controller does not check the status of the serial device before issuing any sequence to the device. This should be managed and looked upon by the CPU/HOST before programming any sequence in the Serial Flash controller. For example, if any read sequence is programmed and executed during the time when the serial device is busy in executing the erase/write command then the read command issued by the Serial Flash controller would be ignored by the Flash. Hence, it is mandatory for the CPU/HOST to check the status of the Flash before programming the Serial Flash controller.
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Rev B
The fast sequence mode operation is based on the contents of the fast-sequence registers. The complete instruction set is enlisted in the following table: Table 6. Instruction set of the fast sequence mode
Instruction CMD 1 CMD 2 CMD 3 CMD 4 CMD 5 ADD 1 ADD 2 Comment Shifts the command written in the SPI_FAST_SEQ_OPC1 register to the Flash. Shifts the command written in the SPI_FAST_SEQ_OPC2 register to the Flash. Information classified Confidential - Do not copy (See last page for obligations) Shifts the command written in the SPI_FAST_SEQ_OPC3 register to the Flash. Shifts the command written in the SPI_FAST_SEQ_OPC4 register to the Flash. Shifts the command written in the SPI_FAST_SEQ_OPC5 register to the Flash. Shifts the address written in the SPI_FAST_SEQ_ADD1 register to the Flash. Shifts the address written in the SPI_FAST_SEQ_ADD2 register to the Flash. Reads/writes the DATA_BYTE1 bit written in the SPI_FAST_SEQ_FLASH_STA_DATA register to the Flash. Reads the DATA_BYTE2 bit written in the SPI_FAST_SEQ_FLASH_STA_DATA register to the Flash. Writes the DATA_BYTE1 and DATA_BYTE2 bits written in the SPI_FAST_SEQ_FLASH_STA_DATA register to the Flash. MODE DUMMY DATA_WR DATA_RD WAIT JUMP_TO_BOOT JUMP_TO_RPT STOP Shifts the data written in the SPI_MODE_BITS register to the Flash. Shifts the data written in the SPI_DUMMY_BITS register to the Flash. Writes the data to the Flash. Reads the data from the Flash. Waits for the time written in the SPI_PROGRAM_ERASE_TIME register. Jumps to the operations written in the SPI_QUAD_BOOT_READ_SEQ1 register. Jumps to the operations written in the SPI_REPEAT_SEQ1 register. Last instruction to end the sequence.
Sequence Operand bits 0001 0010 0001 0011 0100 0101 0001 0010 0010 0001 (Read status register 1) or (Write status register 1) 0011
0010 STATUS_REG_DATA (Read status register 2) 0011 (Write status register 1 and 2)
0100 0101
XXXX XXXX 0001
0110 0010 0111 XXXX 0001 1000 0010 1111 STOP
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The fast sequence mode is broadly classied into two types depending upon the data transfer size: single-page sequence multiple-page sequence The page size of a typical Serial Flash is equal to 256 bytes. Use the single-page sequence for transferring data of size less than or equal to one Serial Flash page. Use the multiplepage sequence for transferring data of size greater than one Serial Flash page. Only one type of operation can be performed at a time. The different types of permitted operations are: erase read write write status register Do not club the read and write operations in one sequence because the FIFO for the data is same for read and write. The read status register can be clubbed with the read and write sequences, but the write status register has to be an exclusive sequence.
Single-page sequence
Single-page read sequence
The single-page read sequence is meant for reading data less than or equal to 256 bytes from the Serial Flash. The execution of events in case of the single-page read sequence is: The software programs read operation sequence in the sequence registers. The software starts the sequence by writing the START_SEQ_BIT bit of the SPI_FAST_SEQ_CFG register. The Serial Flash controller generates the SPI transaction on serial bus. On receiving appropriate command and address, the Flash starts returning data to the Serial Flash controller. The Serial Flash controller stores the data received from the Flash in the internal FIFO. The Serial Flash controller asserts the SPI_DATA_DREQ signal when 256 bytes are written to the FIFO (SPI_DATA_DREQ must be programmed for half FIFO in case of single-page transfers). FDMA/CPU reads the data from the FIFO on receiving the SPI_SEQ_DREQ and SPI_DATA_DREQ signals. Note: In case of Flash read, the FDMA/CPU reads data from the FIFO. In case of Flash write, the FDMA/CPU writes data in the FIFO. Using single-page sequences, the Serial Flash controller performs the x1, x2 and x4 read/write operations and erase operations. Note: The Serial Flash controller asserts the SPI_DATA_DREQ signal when 256 bytes of data is read from the Flash and stored in the FIFO. However, the system has the exibility to poll the SPI_FAST_SEQ_STA register to determine the data available in the FIFO. In this case, it is not mandatory to program the SPI_DATA_DREQ settings. For transferring less than 256 bytes of data, the HOST/CPU can poll the SPI_FAST_SEQ_STA register and no settings of SPI_DATA_DREQ are required. This is particularly useful in cases when DREQ signals are not connected, and also helps in debugging.
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Rev B
The dataow of the single-page read sequence is given in Figure 13. Figure 13. Data ow for single-page sequence
(1) FDMA/CPU initiates sequence conguration.
(2) Controller initiates the SPI transaction.
(5) Half FIFO SPI_DATA_DREQ asserted by the controller. FDMA/CPU
(3) Flash starts returning data to the controller. Serial Flash (4) Data received from the Flash = 256 bytes. SPI transaction terminated by the controller.
FIFO
SPI_CLOCK
CS de-asserted after after 256 bytes data transfer.
CSn
DATA_OUT
OPC + ADDR
DATA_IN
Data = 256 bytes
Single-page write sequence

The single-page write sequence is meant for writing data less than or equal to 256 bytes on the Serial Flash. The execution of events in case of the single-page write sequence is: The software programs the write operation sequence in the sequence registers. The Serial Flash controller asserts the SPI_DATA_DREQ signal to indicate that the FIFO is empty. The software writes the data required to be written to the Flash in the FIFO. The software starts the sequence by writing the START_SEQ_BIT bit of the SPI_FAST_SEQ_CFG register. The Serial Flash controller generates the SPI transaction on serial bus. On receiving appropriate command, address and data, the Flash enters into the write cycle state. The Serial Flash controller enters into wait state for the time programmed in the SPI_PROGRAM_ERASE_TIME register. The Serial Flash controller generates the SPI_SEQ_DREQ signal when the wait time is over. On receiving the SPI_SEQ_DREQ signal, the FDMA/CPU can program another sequence in the sequence registers.
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(6) FDMA/CPU fetches data from the FIFO after its turn around time.
Detailed functional specification Note:
In case of Flash read, the FDMA/CPU reads data from the FIFO. In case of Flash write, the FDMA/CPU writes data in the FIFO. Using the single-page sequences, the Serial Flash controller performs the x1, x2 and x4 read/write operations and erase operations.
Multiple-page sequences
Multiple-page sequences are used to support transfer size greater than 256 bytes. In this mode, the software programs the required data transfer size in the SPI_FAST_SEQ_TRANS_SIZE register. To execute the multiple-page sequence, program the following two set of registers: SPI_FAST_SEQn registers for the initialization sequence SPI_REPEAT_SEQ1 and SPI_REPEAT_SEQ2 registers for the repeat sequence It is mandatory to program both the set of registers (initialization and repeat sequence registers) for multiple-page operations.
Read multiple page

The Serial Flash controller starts the execution of instructions as programmed in the fastsequence registers, and asserts the SPI_DATA_DREQ signal after 256 bytes/512 bytes of data is read from the Flash. This dreq assertion is dependent on the programming of the DATA_DREQ_HALF_NOT_FULL bit in the SPI_FAST_SEQ_CFG register. The CPU/FDMA can read the data from the FIFO once the SPI_DATA_DREQ has been asserted. If the CPU/FDMA fails to retrieve data by the time FIFO is full (512 bytes), the Serial Flash controller terminates the current transaction on the Serial Flash interface. The Serial Flash controller keeps track of the address sent to the Serial Flash. It calculates the new address by incrementing the last address sent to the Serial Flash. Any one of the address registers SPI_FAST_SEQ_ADD1 and SPI_FAST_SEQ_ADD2 can be used for sending the address in FSM mode. This calculation is done for the register chosen in the sequence registers (depending upon the operand). When the FDMA retrieves data from the FIFO, the Serial Flash controller issues a new transaction using the repeat sequence registers for reading from the next memory location. The Serial Flash controller stores the subsequent data in the FIFO and asserts the SPI_DATA_DREQ signal as programmed. The Serial Flash controller breaks the multiple-page transaction into many SPI transactions depending upon the trafc on both the interfaces. After the chip select is de-asserted, the Serial Flash controller repeats the sequence written in the repeat sequence registers. In the read multiple-page sequences, the Serial Flash controller stalls both interfaces (STBus interface and serial interface). For the STBus interface, it stops giving grant to FIFO read requests in case the FIFO is empty. For the SPI interface, it terminates the SPI transactions on serial bus by de-asserting the chip select, in case the FIFO full condition arrives.
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Rev B
The Figure 14 shows a typical example of Serial Flash controller, FDMA/CPU and Serial Flash. The coordination between these components starts from the moment when the FDMA/CPU congures the Serial Flash controller for multiple-page sequence until the time when the FIFO is full and the Serial Flash controller stalls the serial interface by terminating the SPI transaction. The Figure 15 shows the continuation of events after the FIFO is full and the FDMA continues reading data from the FIFO. Figure 14. Events until the FIFO is full in multiple-page read sequence
(7) FIFO full: SPI transaction terminated by the controller.
(1) FDMA/CPU initiates sequence conguration.
(2) Controller initiates the SPI transaction.
(4) Half FIFO SPI_DATA_DREQ asserted by the controller. FDMA/CPU (5) FDMA/CPU fetches data from the FIFO after its turn around time. FIFO
(3) Flash starts returning data to the controller.
Serial Flash
(6) Flash continues returning data to the controller.
SPI_CLOCK
CS de-assertion managed by the controller.
CSn
DATA_OUT
OPC + ADDR
DATA_IN
Data
Rev B
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Figure 15. Events after the FIFO is full in multiple-page read sequence
(9) FDMA/CPU continues fetching data from the FIFO.
(8) Flash transaction stalled.
FDMA/CPU
(10) FIFO available: new SPI Serial Flash transaction started by the controller.
FIFO Serial Flash controller
SPI_CLOCK CS assertion managed by the controller. New address calculated and provided by the controller DATA_OUT OPC + ADDR
CSn
DATA_IN
Data
See Table 7 and Table 8 for an example of programming the registers for multiple-page read (quad mode). Table 7.
Instruction
Multiple-page read (quad mode) initialization sequence

Register Comment Write the write enable command opcode, number of SPI_CLOCK cycles and number of pads required to shift out the command to the Flash, and set the chip select de-assert (CS_DEASSERT) bit. Write the write status register command opcode, number of SPI_CLOCK cycles and Program the SPI_FAST_SEQ1 number of pads required to shift out the register. command to the Flash. Write the data to be written to the status register. Set the chip select de-assertion bit (CS_DEASSERT) and number of pads required. Jump to the repeat sequence register. Sequence register
CMD 1
SPI_FAST_SEQ_OPC1
CMD 2
SPI_FAST_SEQ_OPC2
SPI_FAST_SEQ_FLASH STATUS_REG_DATA _STA_DATA JUMP SPI_REPEAT_SEQ1
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Rev B
Table 8.
Instruction
Multiple-page read (quad read) repeat sequence

Register Comment Write the read command, number of SPI_CLOCK cycles and number of pads required to shift out the command to the Flash. Sequence Register
CMD 3
SPI_FAST_SEQ_OPC3
ADD 1
MODE
SPI_MODE_BITS
Write the mode bits information in the SPI_MODE_BITS register. Write the dummy bits to be written to the Flash. Write the number of SPI_CLOCK cycles and number of pads required to shift out the dummy bits to the Flash. Read the data from the Flash. End operation. Program the SPI_REPEAT_SEQ2 register.
DUMMY
SPI_DUMMY_BITS
DATA STOP
SPI_FAST_SEQ_DATAn
Multiple-page write
The multiple-page write operation is similar to the multiple-page read operation. The Serial Flash controller rst executes the SPI_FAST_SEQn registers until it encounters a JUMP instruction. By executing the SPI_FAST_SEQn registers sequence, it initializes the memory into the desired mode. After reaching the JUMP instruction, it starts executing the repeat sequence registers. For example in a typical Flash, the Serial Flash controller issues the write command, address and one page data to the Flash (Flash cannot write more than a page at a time). After the FIFO data has been transferred to the Flash, FIFO gets empty and the SPI_DATA_DREQ signal is asserted by the Serial Flash controller so that the FDMA/CPU writes the consecutive data in the SPI_FAST_SEQ_DATAn registers. After the data is shifted to the Flash, the Serial Flash controller de-asserts the chip select and executes the WAIT instruction. In this instruction, the Serial Flash controller waits for the pre-programmed wait counter to complete until the memory completes its page program time. In the write multiple page sequences, the Serial Flash controller stalls both the interfaces (STBus interface and serial interface). For the STBus interface, it stops giving grant to FIFO write requests in case the FIFO is full. For the SPI interface, it terminates the SPI transactions on serial bus by driving the chip select low, in case the FIFO_EMPTY condition arrives. When the data for the consecutive pages is again written in FIFO, the Serial Flash controller repeats the repeat sequence. This time the address sent to the Serial Flash is calculated and incremented by the Serial Flash controller itself. The Serial Flash controller keeps on repeating the repeat sequence until the data written in the Flash is equal to the transfer size programmed in the SPI_FAST_SEQ_TRANS_SIZE register. Once the transfer size is done, the STOP instruction is served and the Serial Flash controller is ready again to receive new sequences of operation from the CPU/FDMA.
Rev B
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Write the starting address of the page, number of SPI_CLOCK cycles and number SPI_FAST_SEQ_ADD1 of pads required to shift out the address to Program the SPI_FAST_SEQ_ADD_CFG the Flash. Also, set the chip select SPI_REPEAT_SEQ1 de-assertion register. (CS_DEASSERT_FOR_ADD1) bit.
See Table 9 and Table 10 for an example of programming the registers for multiple-page write (quad mode in winbond Flash). Table 9.
Instruction
Multiple-page write initialization sequence (Winbond quad Flash)

Register Comment Write the write enable command opcode, number of SPI_CLOCK cycles and number of pads required to shift out the command to the Flash and set the chip select de-assert (CS_DEASSERT) bit. Write the write status register command opcode, number of SPI_CLOCK cycles and number of pads required to shift out the command to the Flash. Program the SPI_FAST_SEQ1 register. Sequence register
CMD 1
SPI_FAST_SEQ_OPC1
Write the data to be written to the status SPI_FAST_SEQ_FLASH register. Set the chip select de-assertion STATUS_REG_DATA _STA_DATA bit (CS_DEASSERT) and number of pads required. JUMP SPI_REPEAT_SEQ1 Jump to the repeat sequence register.
Table 10.
Instruction
Multiple-page write repeat sequence (Winbond quad Flash)

Register Comment Write the write enable command, number of SPI_CLOCK cycles and number of pads required to shift out the command to the Flash. Also, set the chip select de-assertion (CS_DEASSERT) bit. Write the page program command, number of SPI_CLOCK cycles and number of pads required to shift out the command to the Flash. Write the starting address of the page, number of SPI_CLOCK cycles and number of pads required to shift out the address to the Flash. Also, set the chip select de-assertion (CS_DEASSERT_FOR_ADD1) bit. Program the SPI_REPEAT_SEQ1 register. Sequence register
CMD 3
SPI_FAST_SEQ_OPC3
CMD 4
SPI_FAST_SEQ_OPC4
ADD 1
SPI_FAST_SEQ_ADD1 SPI_FAST_SEQ_ADD_ CFG
DATA_WR WAIT STOP
SPI_FAST_SEQ_DATAn Write the data to be written to the Flash. SPI_PROGRAM_ERAS E_TIME Wait for counter to complete the Flash page program time. End operation. Program the SPI_REPEAT_SEQ2 register.
Note:
As mentioned in the single page write sequence, the software has to rst write the sequence, and then write one page data in the FIFO and nally write the START_SEQ_BIT bit of the SPI_FAST_SEQ_CFG register.
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Rev B
CMD 2
SPI_FAST_SEQ_OPC2
Chip select bit functioning for DATA phase in single- and multiple-page sequences
The Serial Flash controller offers exibility to congure opcode phase, address phase, mode phase, data phase and dummy phase as per Serial Flash requirements. The exibility to assert/de-assert CS after each of them has been provided to make them independent and also to support changing protocols of different Serial Flashes. However, the last phase of a sequence should always have the conguration to de-assert CS after the last phase is over. Note: One particular transaction is the sequence of events happening during one CS assertion. The purpose of this CS de-assert bit is to cater to future read/write protocol of Serial Flash devices in which there can be some requirement to send some other instruction bits after the DATA read/write phase is complete. For example, executing the following read operation on Serial Flash requires CS conguration to be 0 during the DATA phase: Opcode -> Address -> Dummy bits -> Data read -> Mode bits For the above sequence, the data CS de-assertion bit must be congured to 0 so that the CS remains asserted after the DATA phase as Mode bits are required to be send to the Flash device for completing the sequence. In this case, it is mandatory to congure the CS_DEASSERT bit of the SPI_MODE_BITS register to 1 so that the CS gets de-asserted after the mode phase is over. However, if the CS is programmed to remain asserted after the last phase of the transaction is over, though the Serial Flash controller would not de-assert the CS itself, but it will go into a hang state and the sequence would not get over. As a result, the CPU/FDMA would not be able to program the next sequence and the Serial Flash controller would not start with another sequence and the IP would require a reset. This bit does not provide the exibility to keep CS asserted in between one multiple-page data transfer. The Serial Flash controller manages the CS assertion and de-assertion across the multiple-page data transfer. Figure 16. CS asserted after data phase is over
CSn
CLOCK
DATA_OUT
Opcode
Address
Dummy
Mode
DATA_IN
Data
Rev B
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4.1.9
Fast sequence boot mode

The fast sequence boot mode is designed to support x1, x2 and x4 booting. The advantage of fast sequence boot mode is that any Serial Flash read command can be used for booting through Serial Flash. To bring the Serial Flash controller in the fast sequence boot mode, the HOST has to congure the SPI_MODE_SELECT register and program the fast sequence boot mode registers. This programming must be included in the boot code. The fast sequence boot mode also supports unaligned access requests, that is, the addresses of the requests are not aligned with the opcodes issued.
Boot ow from system prospective

The system follows certain steps to boot in the fast sequence boot mode. These steps are illustrated in the following gure: Figure 17. Booting from Serial Flash
CPU starts booting in the legacy mode.
CPU enables the CACHE.
CPU executes the cached instruction to wait for 100 SPI_CLOCK cycles.
CPU programs the SPI_MODE_SELECT register to bring the Serial Flash controller in the fast sequence boot mode.
CPU programs the SPI_FAST_SEQ_CFG register.
Serial Flash Controller initializes the Serial Flash in the required mode.
CPU can now continue booting from the Serial Flash.
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Rev B
Serial Flash controller functional specification Note:
The Serial Flash controller does not check the status of the serial device before issuing any sequence to the device. This should be managed and looked upon by the CPU/HOST before programming any sequence in the Serial Flash controller. For example, if any read sequence is programmed and executed during the time when the serial device is busy in executing the erase/write command then the read command issued by the Serial Flash controller would be ignored by the Flash. Hence, it is mandatory for the CPU/HOST to check the status of the Flash before programming the Serial Flash controller.
Fast sequence boot mode ow

The Serial Flash controller starts the boot sequence as programmed in the fast sequence mode registers. This is done in two phases. In the rst phase, the Serial Flash controller executes the boot initialization sequence written in the SPI_QUAD_BOOT_SEQ_INITn registers after the software/CPU writes the SPI_FAST_SEQ_CFG register. When the Serial Flash controller encounters a JUMP instruction in the SPI_QUAD_BOOT_SEQ_INITn registers, it starts the execution of sequences in the SPI_QUAD_BOOT_READ_SEQn registers. In the second phase, the SPI_QUAD_BOOT_READ_SEQn registers are executed as soon as the CPU asserts a DATA read request to the Serial Flash controller. After receiving the data read request, the Serial Flash controller executes the read sequence opcode from the respective registers. The address issued to the Flash is the address given by the CPU in the read request. The fast sequence boot mode can also be used to boot in the x1 and x2 pad congurations of the Serial Flash by initializing the SPI_QUAD_BOOT_SEQ_INITn registers using the JUMP command and programming the required read sequence in the QUAD_BOOT_READ_SEQ_REGn registers. The example waveform sequence for the fast sequence boot mode is shown in Figure 18. Figure 18. Waveforms for fast sequence boot mode
STBus CLOCK
SPI_CLOCK CSn
DATA_OUT
Initialization of the Flash
(OPC, address sent by the controller)
To bring Flash in required mode DATA_IN
Boot requests serviced to fetch data from Flash Data returned by the Flash
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Registers required for the fast sequence boot mode

Write the SPI_MODE_SELECT register to congure the Serial Flash controller in fast sequence boot mode. Once the Serial Flash controller is in the fast sequence boot mode, write the following registers for the fast sequence boot mode operation: Table 11.
Register SPI_FAST_SEQ_OPCn SPI_FAST_SEQ_ADD_CFG SPI_MODE_BITS SPI_DUMMY_BITS SPI_FAST_SEQ_FLASH_STA_DATA SPI_FAST_SEQ_CFG SPI_QUAD_BOOT_SEQ_INIT1 and SPI_QUAD_BOOT_SEQ_INIT2
Fast sequence boot mode registers

Comment These registers contain the opcodes and their conguration required for reading the Flash in the boot mode. This register contains the address conguration required for sending the address to the Flash in the boot mode. This register contains the mode bytes required by the Flash. This register contains the dummy bytes required by the Flash. This register contains the status register data required by the Flash. This register contains the quad conguration information required by the Serial Flash controller. These registers contain the initialization sequence required by the Serial Flash controller to bring the Flash in the quad mode. Information classified Confidential - Do not copy (See last page for obligations)
SPI_QUAD_BOOT_READ_SEQ1 and These registers contain the quad read command sequence required by the SPI_QUAD_BOOT_READ_SEQ2 Flash.
An example of programming the registers for the fast sequence boot mode in x4 conguration is given in the following table: Table 12.
Instruction
Boot initialization sequence for x4 conguration

Register Comment Write the write enable command opcode, number of SPI_CLK cycles and number of pads required to shift out the command to the Flash. Also, set the CS de-assert (CS_DEASSERT) bit. Write the write status register command opcode, number of SPI_CLK cycles and number of pads required to shift out the command to the Flash. Set the CS de-assert (CS_DEASSERT) bit. Sequence register
CMD 1
SPI_FAST_SEQ_OPC1
CMD 2
SPI_FAST_SEQ_OPC2
Program the SPI_QUAD_BOOT _SEQ_INIT1 register.
Write the data to be written to the status STATUS_REG_ SPI_FAST_SEQ_FLASH register. Set the CS de-assert DATA _STA_DATA (CS_DEASSERT) bit, number of bytes eld and other required information. JUMP Jump to the SPI_QUAD_BOOT_READ_SEQn register operation.
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Rev B
Table 13.
Instruction CMD 3
Boot read sequence for x4 conguration

Register SPI_FAST_SEQ_OPC3 Comment Write read command, number of SPI_CLK cycles and number of pads required to shift out the command to the Flash. Sequence register
ADDR1
Write the number of SPI_CLOCK cycles SPI_FAST_SEQ_ADD1 and number of pads required to shift out the SPI_FAST_SEQ_ADD_CFG address to the Flash. Write the mode bits to be written to the Flash. Write the number of SPI_CLK cycles and number of pads required to shift out the mode bits to the Flash. Write the dummy bits to be written to the Flash. Write the number of SPI_CLK cycles and number of pads required to shift out the dummy bits to the Flash. Read the data from the Flash. End sequence. Program the SPI_QUAD_BOOT_R EAD_SEQ2 register. Program the SPI_QUAD_BOOT_R EAD_SEQ1 register. Information classified Confidential - Do not copy (See last page for obligations)
MODE
SPI_MODE_BITS
DUMMY
SPI_DUMMY_BITS
DATA_RD STOP
4.1.10
Changing modes of Serial Flash controller

Legacy modes
If the HOST wants to change the mode of the Serial Flash controller during the boot, it has to wait for sufcient time (100 SPI_CLOCK cycles) after the last STBus transaction has completed. Then the HOST can safely write into the SPI_MODE_SELECT register to change the mode of the Serial Flash controller. Alternatively, after boot is over, the mode can be changed by the software by rst reading the SPI_STATUS_MODE_CHANGE register, and then appropriately writing into the SPI_MODE_SELECT register.
Fast sequence mode

The mode must be changed after the SPI_SEQ_DREQ signal is asserted (SPI_SEQ_DREQ = 1), that is, the last sequence execution is completed. The SPI_STATUS_MODE_CHANGE register has no signicance in the fast sequence mode.
4.2
Error conditions and error handling

The Serial Flash controller sets the init_r_opc signal for illegal opcodes (other than those mentioned in Figure 7: Serial Flash controller legacy mode and comms multiplexing logic). Also, the behavior of the Serial Flash controller is indeterministic in case any illegal sequence is programmed in any of the conguration registers.
Rev B
35/77
4.3
Power saving modes

Not applicable.
4.4
Debug modes
Not applicable.
4.5
4.5.1
System requirements
Memory requirements
The conguration space allocated to the Serial Flash controller is from 0x2000 to 0x2FFF, that is, 4 Kbytes. At present, the Serial Flash controller uses only 0x2000 to 0x2500. Rest of the memory space is reserved. The Figure 19 shows in detail the memory requirement of the Serial Flash controller. For more information, refer to Chapter 9: Registers.
36/77
Rev B
Figure 19. Memory map of the Serial Flash controller

0x000 Normal mode registers 0x028 Reserved 0x100 SPI_FAST_SEQ_TRANS_SIZE register 0x104, 0x108 SPI_FAST_SEQ_ADDn registers SPI_FAST_SEQ_ADD_CFG register 0x110 to 0x120 0x124 SPI_MODE_BITS register Fast sequence program and status registers 0x128 SPI_DUMMY_BITS register 0x12C SPI_FAST_SEQ_FLASH_STA_DATA register 0x130 to 0x13C 4 KB SPI_FAST_SEQn registers (n = 1 to 4) 0x140 SPI_FAST_SEQ_CFG register 0x144 SPI_FAST_SEQ_STA register 0x0FFF SPI_QUAD_BOOT_SEQ_INITn registers (n = 1 to 2) 0x150, 0x154 SPI_QUAD_BOOT_READ_SEQn registers (n = 1 to 2) 0x158 SPI_PROGRAM_ERASE_TIME 0x15C, 0x160 SPI_REPEAT_SEQn registers (n = 1 to 2) SPI_STATUS_WR_TIME register 0x168 to 0x2FC Fast sequence data registers Reserved 0x300 to 0x4FF Fast sequence data FIFO (512 bytes) 0x148, 0x14C 0x10C
0x0000
0x164
0x500 Reserved
0xFFF
Rev B
37/77
SPI_FAST_SEQ_OPCn registers
4.5.2
Interrupt behavior and requirements

The Serial Flash controller has no interrupts. However, it has two DREQs available (SPI_SEQ_DREQ and SPI_DATA_DREQ) to communicate the status of the Serial Flash controller to FDMA. These DREQs can also be connected with the interrupt-level controller (ILC) to manage interrupts to the HOST. In that case, the HOST clears these interrupts with the help of ILC. The Serial Flash controller does not clear these interrupts at the IP level. The Figure 8 shows the DREQs connection with FDMA and its usage as interrupts by the CPU.
4.6
Initialization
Not applicable.
4.6.1
Hard reset
Hard reset (rst_n) is provided to reset the Serial Flash controller. It is active low. After hard reset, the IP is in the default normal boot mode.
4.6.2
Soft reset
Soft reset is available in the Serial Flash controller for resetting the fast sequence mode registers and ushing the FIFO contents. For more details, refer to Chapter 9: Registers. The soft reset is not applicable to legacy modes, that is, the IP remains in the fast sequence mode after the soft reset is applied. The IP does not go to the default normal boot mode after the soft reset is applied.
38/77
Rev B
Clocking
Clocking
The Serial Flash controller operates at 100 MHz. This clock is same as the EMISS clock. The Serial Flash devices are clocked through the Serial Flash controller using SPI_CLOCK. This SPI_CLOCK is generated inside the Serial Flash controller by dividing the EMISS clock as dened by the clock division ratio in the SPI_CLK_DIV register. Depending upon the type of Flash used by the system, SPI_CLOCK can be managed by programming the suitable clock division ratio.
5.1
Frequencies
Table 14.
Clock name Min CLOCK SPI_CLOCK 0 0 Typical 100 MHz 50 MHz Max 100 MHz 50 MHz
Example clock names and frequencies

Clock frequencies
5.2
Clock relationships
The SPI_CLOCK and CLOCK are synchronous clocks.
5.3
Generated clocks
The SPI_CLOCK is a generated clock. It is generated by the clock divider inside the Serial Flash controller. The clock divider runs on the EMISS clock and the division ratio is controlled by the SPI_CLK_DIV register. After reset, the mode pin (MODE_SPI_CLK_DIV) decides the division ratio. This mode pin is brought at the top so that the desired frequency can be achieved at the SoC for booting. The generated SPI_CLOCK is used to clock the external Flash. It is also used by the Serial Flash controller to clock the incoming and outgoing data to the external Flash.
Rev B
39/77
Bus interfaces
Bus interfaces
Table 15.
Bus type T2-RGV
SPIRIT bus types for serial_ash_controller

Vendor st.com Library STBus Name T2-RGV Version 1.0
Table 16.
SPIRIT bus interfaces of serial_ash_controller

Bus type T2-RGV Role TARGET Address block name Information classified Confidential - Do not copy (See last page for obligations) programming_and_data_transfer_bus
Bus interface type2
6.1
External hardware interfaces

Not applicable.
40/77
Rev B
Routers and interconnections
Routers and interconnections

Not applicable.
7.1
Local interconnect (routers)

Not applicable.
7.2
Point-to-point connections
Information classified Confidential - Do not copy (See last page for obligations) Rev B 41/77
Not applicable.
Pin group list
8
Table 17.
Signal name rst_n clock
Pin group list

Port list for serial_ash_controller
I/O I I N/A clock clock early early clock clock clock Timing Clock clock Description Active low reset Global clock running at 100 MHz maximum This mode pin is used to select the SPI frequency during boot 0: Set for ATMEL 1: Set the default to ST Flash STBus request SPI grant SPI response request This signal indicates that the SPI cycle will nish in the next cycle. It is always the case when init_valid = init_validnextcycle delayed by one cycle. This signal may be useful for the memory controllers that need this information to change the arbitration. For example, if the Serial Flash controller needs the read data bus in the next cycle, it may change the arbitration for a read to internal SRAM, which also needs the bus in that cycle. STBus end of packet (EOP) SPI response EOP Address to be accessed from STBus Data from STBus Response data from IP Opcode describing operation presented to the Serial Flash controller Response opcode: 0: Success, 1: Fail It is used to indicate an access to SPI conguration registers rather than to an external bank Information classified Confidential - Do not copy (See last page for obligations) Static inputs System Logical grouping
mode_spi_clk_div<7:0> I stnotatmel init_req init_gnt init_valid I I O O
spi_validnextcycle
early
clock
init_eop init_r_eop init_addr<31:2> init_data<31:0> init_r_data<31:0> init_opc<7:0>
I O I I O I
early
clock clock
STBus buffer and router interface
early early late early
clock clock clock clock
init_r_opc
clock
spi_cfgnotdat
early
clock
42/77
Rev B
Serial Flash controller functional specification Table 17.

Signal name
Pin group list
Port list for serial_ash_controller (continued)

I/O Timing Clock Description 0: Do not take control of shared pads with comms subsystem. 1: Takes control of pad shared with comms subsystem and releases it only when response corresponding to all requests have been received. (Currently, this pin is tied at EMISS level itself). Chip select for Serial Flash Clock to Serial Flash Serial data to Serial Flash Input data from Serial Flash Input port for serial data in when congured in the dual output read mode One of the output data port for the quad data mode Hold input from Serial Flash Hold output for Serial Flash Write protect input for Serial Flash Write protect output for Serial Flash Enable to put the spi_clock pad in input mode during reset Enable to put the spi_not_cs pad in input mode during reset Enable for deciding the polarity of the bidirectional port at the top level Padlogic for the dual output read mode interface (to top glue for Enable for spi_data_in the multiplexing bidirectional pad Comms-SPI Hold enable required for the HOLD with Flash-SPI) pad Write protect enable required for the WP pad This signal is used to take the control of the pads Information classified Confidential - Do not copy (See last page for obligations) Logical grouping
spi_buff_bank
clock
System
spi_not_cs spi_clock spi_data_out spi_data_in spi_dbl_data_in
O O O I I
early
spi_clock spi_clock
early early early
spi_clock spi_clock spi_clock
Pad interface
spi_data_out_quad spi_hold_in spi_hold_out spi_wr_protect_in spi_wr_protect_out spi_clk_enb spi_cs_enb
O I O I O O O
spi_clock spi_clock spi_clock spi_clock spi_clock clock clock
spi_data_out_en
early
clock
spi_data_in_enb spi_hold_enb spi_wr_protect_enb spibootnotcomms
O O O O
clock clock clock clock
Rev B
43/77
Pin group list Table 17.

Signal name spi_seq_dreq
Port list for serial_ash_controller (continued)

I/O O Timing Clock clock Description Dreq generated to indicate the end of the programmed sequence Dreq generated to indicate that the Pacing signals FDMA/CPU must read the data from for the fast the FIFO if it is a read operation or sequence mode write the data into the FIFO if it is a multiple-page write operation Logical grouping
spi_data_dreq
clock
tst_scanenable tst_scanin<n:0> tst_scanout<n:0> tst_scanmode tst_gclkenable
I I O I I
early
clock Information classified Confidential - Do not copy (See last page for obligations) clock clock Test
early early
clock clock
44/77
Rev B
Registers
9
9.1
Registers
Address blocks and sub-blocks
The conguration space available to the Serial Flash controller is 4 Kbytes from 0x02000 to 0x02FFF. All programming registers are accessible through the Type 2 port. Table 18. SPIRIT address block programming_and_data_transfer_bus
Size 4K Address block SPI Description SPI programming registers Information classified Confidential - Do not copy (See last page for obligations)
Base address 0x2000
9.1.1
Table 19.
Summary table
Register summary table
Description Clock division register Contiguous mode, fast read mode, dual output mode, fast sequence mode and fast sequence boot mode selection. Congure the Serial Flash controller for different parameters of the Serial Flash supported Single-bit status register reecting when mode of SPI (in the SPI_MODE_SELECT register) can be changed Total number of bits to be read/written from/to the Flash Starting address of the memory location of the Flash to be read or written Address conguration information required for shifting the address in the Flash Opcodes required to be shifted to the Flash along with their conguration High performance mode sequence bits required by some Serial Flash devices for improved performances Dummy bits information required by some Serial Flash devices Data to be read or written from the Flash status register and its conguration required See page 47 page 48
Address offset Register 0x010 0x018 SPI_CLK_DIV SPI_MODE_SELECT
0x020
SPI_CONFIG_DATA
page 49
0x028
SPI_STATUS_MODE_CHANGE
page 50
0x100 0x104 0x108 0x10C 0x110 - 0x120
SPI_FAST_SEQ_TRANS_SIZE SPI_FAST_SEQ_ADD1 SPI_FAST_SEQ_ADD2 SPI_FAST_SEQ_ADD_CFG SPI_FAST_SEQ_OPCn (n = 1 to 5) SPI_MODE_BITS
page 50 page 51 page 51 page 52 page 53
0x124
page 54
0x128
SPI_DUMMY_BITS
page 56
0x12C
SPI_FAST_SEQ_FLASH_STA_DATA
page 57
Rev B
45/77
Registers Table 19. Register summary table (continued)
Address offset Register 0x130 0x134 0x138 0x13C 0x140 SPI_FAST_SEQ1 SPI_FAST_SEQ2 SPI_FAST_SEQ3 SPI_FAST_SEQ4 SPI_FAST_SEQ_CFG
Description
See page 58
Sequence to be programmed by software, which are executed by the Serial Flash controller
page 59 page 60 page 61
Conguration required by the fast sequence and fast sequence boot modes Contains information about the status of the sequence written in the sequence registers Initialization sequence required by the Flash to come in the quad mode Quad read command sequence for reading data in the quad mode Page program/erase time required by the Flash to perform write/erase Repeat sequences required for multiple page read/write operation Status register write time required by the Flash Data to be read or written to the Flash. The maximum size of this FIFO is 512 bytes (two memory pages)
page 62
0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164
SPI_FAST_SEQ_STA SPI_QUAD_BOOT_SEQ_INIT1 SPI_QUAD_BOOT_SEQ_INIT2 SPI_QUAD_BOOT_READ_SEQ1 SPI_QUAD_BOOT_READ_SEQ2 SPI_PROGRAM_ERASE_TIME SPI_REPEAT_SEQ1 SPI_REPEAT_SEQ2 SPI_STATUS_WR_TIME
page 64 page 65 page 66 page 67 page 68 page 69 page 70 page 71 page 72 Information classified Confidential - Do not copy (See last page for obligations)
0x300 - 0x4FF
SPI_FAST_SEQ_DATAn
page 72
46/77
Rev B
Registers
9.1.2
Register descriptions Clock division factor

9 8 7 6 5 4 CLK_DIV_FACTOR 3 2 1 0 RESERVED
SPI_CLK_DIV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED
Address: Type: Reset: Description:
SPIBaseAddress + 0x10 R/W 0x02 Use this register to set the division factor of the EMISS clock received by the Serial Flash controller. By default, it is divided by two. The division ratio can vary from 2 to 256. The 0th bit of this register is tied to 0 to ensure even division factor.
[31:8] RESERVED [7:1] CLK_DIV_FACTOR: Use these bits to set the division factor of the EMISS clock. Values must be in the range from 1 to 127. 1 for division factor 2. 2 for division factor 4. ......... 127 for division factor 256. [0] RESERVED: Tie this bit to 0 to ensure that the division factor is always even. This bit is non-writable.
Rev B
47/77
Registers
SPI_MODE_SELECT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
Mode select
4 FAST_SEQ_BOOT_MODE 3 FAST_SEQ_MODE 2 DUAL_OUTPUT_MODE 1 0
SPIBaseAddress + 0x0018
R/W 0x00 Select the Serial Flash controller mode, such as the contiguous mode, fast read mode, dual output read mode, fast sequence mode and fast sequence boot mode by writing into different bitelds of this register. By default, the Serial Flash controller is in the normal read mode. The possible congurations of the legacy modes with the contiguous mode are given in the following table: Table 20.
Modes
Possible mode congurations

Normal mode Fast read mode Yes Dual output mode Yes Fast sequence Fast sequence mode boot mode No No
Contiguous Yes
The FAST_SEQ_MODE bit must always be set while setting the FAST_SEQ_BOOT_MODE bit to bring the Serial Flash controller in the fast sequence boot mode.
[31:5] RESERVED [4] FAST_SEQ_BOOT_MODE: 0: Normal fast sequence mode. [3] FAST_SEQ_MODE: 0: Normal mode. 1: Fast sequence boot mode. 1: Fast sequence mode.
[2] DUAL_OUTPUT_MODE: Set this bit to run the Serial Flash controller in the dual data mode (0x3B). 0: Normal mode. 1: Dual output mode. [1] FAST_READ: The fast read mode is only supported with STNOTATMEL = 1, that is, for ST memories. 0: Normal mode. 1: Fast read mode. [0] CONTIG_MODE: Performance improved mode. This mode is for throughput improvement. Set this bit in case contiguous reads are required from Serial Flash. 0: Normal mode. 1: Contiguous mode.
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Rev B
CONTIG_MODE
FAST_READ
RESERVED
Registers
SPI_CONFIG_DATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SPI_DATA_HOLD_TIME CS_SETUP_HOLD 9
SPI conguration data

8 7 6 5 4 3 2 1 0
MIN_CS_HIGH
SPIBaseAddress + 0x0020 R/W 0x00A00AA1 SPI conguration data. Program the Serial Flash device for chip select, data setup or hold time using this register. The minimum de-assertion width of the chip select can also be programmed.
[31:24] SPI_DATA_HOLD_TIME: Set the setup time required for the Serial Flash devices supported. Set in terms of EMISS clock. Reset value is 00. Program this parameter as follows: 0x00: Set the hold time as one EMISS clock cycle. 0x01: Set the hold time as two EMISS clock cycles. ............. 0xFF: Set the hold time as 256 EMISS clock cycles. [23:16] CS_SETUP_HOLD: Set the chip select setup/hold time for the Serial Flash with respect to the EMISS clock. The reset value is 0xA0. The chip select setup/hold time is in the range from 1 to 255. Program this parameter as follows: 0x00: Reserved. 0x01: Set the minimum setup/hold time as one EMISS clock cycle. 0x02: Set the minimum setup/hold time as two EMISS clock cycles. [15:4] MIN_CS_HIGH: Set the minimum time required for the chip select to remain high before asserting again. It is in the range from 0 to 4095 cycles. Set in terms of EMISS clock. The reset value is 0x0AA. [3:0] SPI_DEVICE: Set the part number for the Serial Flash. When STNOTATMEL is 1, the reset value is 0x1. Otherwise, the reset value is 0x4. 0x1: ST. 0x4: Atmel. Others: Reserved.
Note: The SPI_DATA_HOLD_TIME bits are now obsolete. The data hold time is managed by the hardware by retiming the data output to the Serial Flash by one EMISS clock cycle. The same is done for the data received from the Serial Flash. This parameter is kept for legacy purposes only. It is no more required to ne tune the data hold time. Note: The CS_SETUP_HOLD time and MIN_CS_HIGH time are though driven by the register values but some extra cycles are added by the controller for internal calculations. Hence, it cannot be observed as a one-to-one mapping of programmable values.
Rev B
SPI_DEVICE
49/77
Registers
SPI_STATUS_MODE_CHANGE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED 9 8
Status mode change

7 6 5 4 3 2 1 0 MODE_CHANGE
SPIBaseAddress + 0x0028 R 0x1 Use this register to see the status for changing the mode of the Serial Flash controller dynamically while it is in the normal mode, contiguous mode, fast read mode and dual output mode. This bit must always be monitored by the software before changing the legacy modes of the Serial Flash controller.
Note: The bit[0] holds no relevance in the fast sequence mode, where mode change must take place after the SPI_SEQ_DREQ signal is asserted.
[31:1] RESERVED [0] MODE_CHANGE: 0: Not ready for dynamic mode change. 1: Can change the mode dynamically.
SPI_FAST_SEQ_TRANS_SIZE
Fast sequence transfer size

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NO_OF_BITS RESERVED
SPIBaseAddress + 0x0100 R/W 0x00 This register contains the total number of bits to be written or read from the Flash. Write this register whenever data is required to be written to or read from the Flash in a sequence. The total number of bits written in this register must always be multiple of 32 bits (4 bytes), since the FIFO width is 32 bits. For example, to write a single 256-bytes Flash page, 0x800 must be written in this register.
[31:30] RESERVED [29:0] NO_OF_BITS: Number of bits to be written to the Flash or number of bits to be read from the Flash in one single sequence.
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Rev B
Registers
SPI_FAST_SEQ_ADD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDRESS
Fast sequence address1

9 8 7 6 5 4 3 2 1 0
SPIBaseAddress + 0x0104 R/W 0x00 This register contains the starting address of the operation required to be executed by the Serial Flash controller in the fast sequence mode. The Serial Flash controller starts sending the address by sending the MSB bit of the address to the Flash.
[31:0] ADDRESS: Starting address of the operation.
SPI_FAST_SEQ_ADD2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDRESS
Fast sequence address2

9 8 7 6 5 4 3 2 1 0
SPIBaseAddress + 0x0108 R/W 0x00 This register contains the starting address of the operation required to be executed by the Serial Flash controller in the fast sequence mode. The Serial Flash controller starts sending the address by sending the MSB bit of the address to the Flash.
[31:0] ADDRESS: Starting address of the operation.
Rev B
51/77
Registers
SPI_FAST_SEQ_ADD_CFG
Fast sequence address conguration

9 8 CS_DEASSERT_FOR_ADD1 7 NO_OF_PADS_FOR_ADD1 6 5 4 3 NO_OF_ADD1_CYCLES 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CS_DEASSERT_FOR_ADD2 NO_OF_PADS_FOR_ADD2 NO_OF_ADD2_CYCLES
ADDR2_32_BIT
SPIBaseAddress + 0x010C R/W 0x00 This register contains the information of the number of SPI_CLOCK cycles required to shift out the address written in the SPI_FAST_SEQ_ADD1 and SPI_FAST_SEQ_ADD2 registers. In case of the fast sequence boot mode, this conguration is required for shifting out the corresponding request address to the boot bank. The SPI_CLOCK cycles depend upon the type of memory and command selected. For example, it may be 24 SPI_CLOCK cycles for quad data read while six SPI_CLOCK cycles for quad I/O read, depending upon the device. It also contains the information whether the present address cycles are continued by some command/data or needs to be terminated by de-asserting the CS (as in the case of ERASE commands). Also, it stores the information that the required address needs to be sent on how many pads (depends upon the device supported and operation done). Write this register either in the fast sequence mode or the fast sequence boot mode of the Serial Flash controller. The bit elds ADDR1_32_BIT & ADDR2_32_BIT are required to congure the controller for supporting 32 bit address ashes. They are set to 1 whenever 32 bit address scheme is required by the serial ash.
[31:26] RESERVED [25] ADDR2_32_BIT:Address2 is 32 bit long. 0:24 bit address 1: 32 bit address [24] CS_DEASSERT_FOR_ADD2: De-assert the chip select. 0: The chip select remains asserted after shifting out the address 2 for sending command/data. 1: De-assert the chip select after shifting out the address 2. [23:22] NO_OF_PADS_FOR_ADD2: Number of pads on which the address 2 needs to be sent to the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved.
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Rev B
ADDR1_32_BIT
RESERVED
RESERVED
Registers
[21:16] NO_OF_ADD2_CYCLES: Address cycles required to shift out the address 2 into the device. [15:10] RESERVED [9] ADDR1_32_BIT:Address1 is 32 bit long. 0:24 bit address 1: 32 bit address [8] CS_DEASSERT_FOR_ADD1: De-assert the chip select. 0: The chip select remains asserted after shifting out the address 1 for sending command/data. 1: De-assert the chip select after shifting out the address 1. [7:6] NO_OF_PADS_FOR_ADD1: Number of pads on which the address 1 needs to be sent to the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved. [5:0] NO_OF_ADD1_CYCLES: Address cycles required to shift out the address 1 into the device.
SPI_FAST_SEQ_OPCn
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NO_OF_SPI_CLK_CYCLES 9
Fast sequence opcode

8 7 6 5 4 3 2 1 0
SPIBaseAddress + 0x0110 + (n - 1) * 0x04 (where n = 1 to 5) R/W 0x0 This register contains the opcodes required to be executed by the Flash. When the fast-sequence operation starts after writing the SPI_FAST_SEQ_CFG register, the SPI retrieves the opcodes from these registers. This register also contains the information about the number of pads and SPI_CLOCK cycles required to shift out this opcode to the Flash.
Rev B
53/77
FLASH_OPCODE
CS_DEASSERT
NO_OF_PADS
RESERVED
Registers
[31:17] RESERVED [16] CS_DEASSERT: De-assert the chip select. 0: The chip select remains asserted after shifting the command for sending command/data. 1: De-assert the chip select after shifting the command. [15:14] NO_OF_PADS: Number of pads on which the command needs to be sent to the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved. Information classified Confidential - Do not copy (See last page for obligations) [13:8] NO_OF_SPI_CLK_CYCLES: Number of SPI_CLOCK cycles required by the Serial Flash controller to shift out the command. [7:0] FLASH_OPCODE: Flash opcode required to be executed by the Flash.
SPI_MODE_BITS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NO_OF_SPI_CLK_CYCLES 9 8 7 6 5 4
Mode bits
3 2 1 0
CS_DEASSERT
NO_OF_PADS
SPIBaseAddress + 0x0124 R/W 0x00 This register contains the mode information required by some Serial Flash devices to perform enhanced quad read/write operations. Also, this register contains the total SPI_CLOCK cycles required to shift out the mode bits to the Flash. It also writes about the number of pads required to shift-out the mode bits and also about the chip select assertion/de-assertion after the mode bits.
[31:25] RESERVED [24] CS_DEASSERT: De-asserts the chip select. 0: The chip select remains asserted after shifting the mode bits for sending command/data. 1: De-assert the chip select after shifting the mode bits. [23:22] NO_OF_PADS: Number of pads on which the mode bits need to be sent to the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved.
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Rev B
MODE_BITS
RESERVED
RESERVED
Registers
[21:16] NO_OF_SPI_CLK_CYCLES: Number of SPI_CLOCK cycles required by the Serial Flash controller to shift-out the mode bits. [15:8] RESERVED [7:0] MODE_BITS: Mode bits required to enhance performance during the quad read/write operations.
Rev B
55/77
Registers
SPI_DUMMY_BITS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NO_OF_SPI_CLK_CYCLES 9 8 7 6 5
Dummy bits
4 3 2 1 0
CS_DEASSERT
NO_OF_PADS
SPIBaseAddress + 0x0128 R/W 0x00 This register contains the dummy bits information as required by some Serial Flash devices to perform enhanced quad read/write operations. Also, this register contains the total SPI_CLOCK cycles required to shift-out the dummy bits to the Flash. It writes about the number of pads required to shift-out the dummy bits and also about the chip select assertion/de-assertion after the dummy bits.
[31:25] RESERVED [24] CS_DEASSERT: De-assert the chip select. 0: The chip select remains asserted after shifting-out the dummy bits for sending command/data. 1: De-assert the chip select after shifting-out the dummy bits for sending command/data. [23:22] NO_OF_PADS: Number of pads on which the dummy bits needs to be sent to the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved. [21:16] NO_OF_SPI_CLK_CYCLES: Number of SPI_CLOCK cycles required by the Serial Flash controller to shift-out the dummy bits. [15:8] RESERVED [7:0] DUMMY_BITS: Dummy bits required to enhance performance during quad read/write operations.
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Rev B
DUMMY_BITS
RESERVED
RESERVED
Registers
SPI_FAST_SEQ_FLASH_STA_DATA
Fast sequence Flash status data

9 8 7 6 5 4 DATA_BYTE1 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STA_RDNOTWR CS_DEASSERT NO_OF_PADS DATA_BYTE2 RESERVED RESERVED
SPIBaseAddress + 0x012C R/W 0x00 This register contains the data required to be written in the status register of the Flash. For example, the status register needs to be written to the Flash to enable or disable modes of the Flash. The chip select assertion or de-assertion is also stated in this register. The bit[21] (STA_RDNOTWR) of this register must be set according to the operation in the sequence registers. Either a read status register or a write status register operation can be performed at a time in one sequence. The read status register cannot be clubbed with any other operation. The read status register has to be a separate sequence always. According to the operand selected while writing the sequence registers, the corresponding data byte can be read or written to the elds [15:8] or/and [7:0] of this register.
[31:22] RESERVED [21] STA_RDNOTWR: Status register read not write. 0: Write status register. 1: Read status register. [20] CS_DEASSERT: De-assert the chip select. 0: The chip select remains asserted after shifting the status register data bits for sending command/data. 1: De-assert the chip select after shifting the status register data bits for sending command/data. [19:18] RESERVED [17:16] NO_OF_PADS: Number of pads on which the status bits needs to be sent to the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved. [15:8] DATA_BYTE2: Second data byte to be written to the Flash. [7:0] DATA_BYTE1: First data byte to be written to the Flash.
Rev B
57/77
Registers
SPI_FAST_SEQ1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SECOND_OPERAND FOURTH_OPERAND THIRD_OPERAND SECOND_INS FOURTH_INS 9 8 7
Fast sequence 1
6 FIRST_OPERAND 5 4 3 2 1 0
THIRD_INS
SPIBaseAddress + 0x0130 R/W

0x00 This register contains the sequence that is required to be executed by the Serial Flash controller. Therefore, this register must be programmed after going through the datasheet of the Flash supported. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] FOURTH_OPERAND: Fourth operand. [27:24] FOURTH_INS: Fourth instruction to be executed by the Flash. [23:20] THIRD_OPERAND: Third operand. [19:16] THIRD_INS: Third instruction to be executed by the Flash. [15:12] SECOND_OPERAND: Second operand. [11:8] SECOND_INS: Second instruction to be executed by the Flash. [7:4] FIRST_OPERAND: First operand for rst instruction. [3:0] FIRST_INS: First instruction to be executed by the Flash. 0001: CMD. 0010: ADD. 0011: STATUS_REG_DATA. 0100: MODE. 0101: DUMMY. 0110: DATA. 0111: WAIT. 1000: JUMP. 1111: STOP.
58/77
Rev B
FIRST_INS
Registers
SPI_FAST_SEQ2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SEVENTH_OPERAND EIGHTH_OPERAND SIXTH_OPERAND SEVENTH_INS 9 8 7
Fast sequence 2
6 FIFTH_OPERAND 5 4 3 2 1 0
EIGHTH_INS
SIXTH_INS
SPIBaseAddress + 0x0134 R/W 0x00 This register contains the subsequent sequence that is required to be executed by the Serial Flash controller after executing the commands written in the SPI_FAST_SEQ1 register. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] EIGHTH_OPERAND: Eighth operand. [27:24] EIGHTH_INS: Eighth instruction to be executed by the Flash. [23:20] SEVENTH_OPERAND: Seventh operand. [19:16] SEVENTH_INS: Seventh instruction to be executed by the Flash. [15:12] SIXTH_OPERAND: Sixth operand. [11:8] SIXTH_INS: Sixth instruction to be executed by the Flash. [7:4] FIFTH_OPERAND: Fifth operand. [3:0] FIFTH_INS: Fifth instruction to be executed by the Flash. 0001: CMD. 0010: ADD. 0011: STATUS_REG_DATA. 0100: MODE. 0101: DUMMY. 0110: DATA. 0111: WAIT. 1000: JUMP. 1111: STOP.
Rev B
FIFTH_INS
59/77
Registers
SPI_FAST_SEQ3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ELEVENTH_OPERAND TWELFTH_OPERAND TENTH_OPERAND ELEVENTH_INS 9 8 7
Fast sequence 3
6 NINTH_OPERAND 5 4 3 2 1 0
TWELFTH_INS
TENTH_INS
SPIBaseAddress + 0x0138 R/W 0x00 This register contains the subsequent sequence that is required to be executed by the Serial Flash controller after executing the commands written in the SPI_FAST_SEQ2 register. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] TWELFTH_OPERAND: Twelfth operand. [27:24] TWELFTH_INS: Twelfth instruction to be executed by the Flash. [23:20] ELEVENTH_OPERAND: Eleventh operand. [19:16] ELEVENTH_INS: Eleventh instruction to be executed by the Flash. [15:12] TENTH_OPERAND: Tenth operand. [11:8] TENTH_INS: Tenth instruction to be executed by the Flash. [7:4] NINTH_OPERAND: Ninth operand. [3:0] NINTH_INS: Ninth instruction to be executed by the Flash. 0001: CMD. 0010: ADD. 0011: STATUS_REG_DATA. 0100: MODE. 0101: DUMMY. 0110: DATA. 0111: WAIT. 1000: JUMP. 1111: STOP.
60/77
Rev B
NINTH_INS
Registers
SPI_FAST_SEQ4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FOURTEENTH_OPERAND SIXTEENTH_OPERAND FIFTEENTH_OPERAND FOURTEENTH_INS 9 8 7
Fast sequence 4
6 THIRTEENTH_OPERAND 5 4 3 2 1 0
SPIBaseAddress + 0x013C
R/W 0x00 This register contains the subsequent sequence that is required to be executed by the Serial Flash controller after executing the commands written in SPI_FAST_SEQ3 register. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode. .
[31:28] SIXTEENTH_OPERAND: Sixteenth operand. [27:24] SIXTEENTH_INS: Sixteenth instruction to be executed by the Flash. [23:20] FIFTEENTH_OPERAND: Fifteenth operand. [19:16] FIFTEENTH_INS: Fifteenth instruction to be executed by the Flash. [15:12] FOURTEENTH_OPERAND: Fourteenth operand. [11:8] FOURTEENTH_INS: Fourteenth instruction to be executed by the Flash. [7:4] THIRTEENTH_OPERAND: Thirteenth operand. [3:0] THIRTEENTH_INS: Thirteenth instruction to be executed by the Flash. 0001: CMD. 0010: ADD. 0011: STATUS_REG_DATA. 0100: MODE. 0101: DUMMY. 0110: DATA. 0111: WAIT. 1000: JUMP. 1111: STOP.
Rev B
THIRTEENTH_INS
SIXTEENTH_INS
FIFTEENTH_INS
61/77
Registers
SPI_FAST_SEQ_CFG
Fast sequence conguration

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA_DREQ_HALF_NOT_FULL
Type: Reset: Description:
R/W 0x00 This register contains the information required by the Serial Flash controller to operate in the fast sequence mode and fast sequence boot mode. This register must be programmed after all the registers required for the fast sequence mode operation are written. Writing 1 into the bit[0] of this register allows the Serial Flash controller to start with the sequence written in the SPI_FAST_SEQ1 register and continues until it encounters a STOP instruction. The CS_DEASSERT bit of this register is used to de-assert the chip select of the Flash as soon as the data transfer is complete. It does not take WAIT or STOP instructions into account. The WAIT instruction is done after data transfer is completed from Serial Flash. This is done to follow the Serial Flash protocol. The Serial Flash controller decides whether the sequence programmed in the sequence registers is a read, write or erase operation using bit[8] and bit[7] of this register. The Serial Flash controller also determines the number of pads and de-assert chip select options for data reading or writing by this register. The soft reset can be applied to the Serial Flash controller by asserting bit[5] of this register. The soft reset bit is not self-clearing. Software needs to assert and de-assert soft reset. The time given for soft reset assertion must take care of the clock division ratio programmed. It must be such that a minimum of ve SPI_CLOCK cycles are provided for proper logic resetting. For performing ERASE operations, ERASE_BIT must be set to 1. Also, erase operation requires RD_NOT_WR bit to be set to 1. The RD_NOT_WR bit should always be cleared to 0 before writing the data to the FIFO. The Serial Flash controller asserts the SPI_DATA_DREQ signal to reect the status of the FIFO for the FDMA to read or write the data from the FIFO. This information is made programmable by writing into bit[18] of this register. By default, the SPI_DATA_DREQ signal is asserted when the FIFO is full, but it can be asserted when the FIFO is half full by writing this bit to 1. For best performance, bit[18] must be set to 1, that is, half FIFO (256 bytes).
62/77
Rev B
Address:
SPIBaseAddress + 0x0140
START_SEQ_BIT
CS_DEASSERT
NO_OF_PADS
RD_NOT_WR
ERASE_BIT
SW_RESET
RESERVED
RESERVED
RESERVED
Registers
[31:19] RESERVED [18] DATA_DREQ_HALF_NOT_FULL: 0: Dreq asserted when FIFO is full or empty (512 bytes). 1: Dreq asserted when FIFO is half-full or half-empty (256 bytes). [17:16] NO_OF_PADS: Number of pads on which the data needs to be sent/received from the device. 00: One pad. 01: Two pads. 11: Four pads. 10: Reserved. [15:9] RESERVED Information classified Confidential - Do not copy (See last page for obligations) [8] ERASE_BIT: Erase operation bit. 0: No erase operation. 1: Perform erase operation. [7] RD_NOT_WR: Read or write operation bit. 0: Write to Serial Flash. 1: Read from Serial Flash. [6] CS_DEASSERT: De-assert the chip select of the Flash after receiving/sending data to the Flash. 0: The chip select remains asserted after sending/receiving the data. 1: De-asserts the chip select after sending/receiving the data. [5] SW_RESET: Soft reset bit. 0: No soft reset. 1: Apply soft reset. [4:1] RESERVED [0] START_SEQ_BIT: Start sequence bit. 0: No operation is started. 1: Start the sequence written in the SPI_FAST_SEQ1 register.
Rev B
63/77
Registers
SPI_FAST_SEQ_STA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED 9
Fast sequence status

8 7 6 5 4 3 2 CURRENT_CMD 1 0
SPIBaseAddress + 0x0144 R/W 0x0 This register reects the current status of the fast sequence mode. It noties about the current command being executed. By default, the FAST_SEQ_STA eld of this register is 0. After the SPI_FAST_SEQ_CFG register is written, the FAST_SEQ_STA bit is set to 1. The FAST_SEQ_STA bit is reset to 0 again when all the commands written in the sequence registers have been executed. The FIFO_STATUS denotes the number of 32-bit words available for reading from or writing to the FIFO.
[31:12] RESERVED [11:5] FIFO_STA: Reect the data locations available in FIFO. [4] FAST_SEQ_STA: 0: Sequence written in the sequence registers is in progress. 1: Sequence execution is completed. [3:0] CURRENT_CMD: The current command being executed is reected here.
64/77
Rev B
FAST_SEQ_STA
FIFO_STA
Registers
SPI_QUAD_BOOT_SEQ_INIT1
FOURTH_OPERAND THIRD_OPERAND
Quad boot sequence initialization 1

9 SECOND_INS 8 7 6 FIRST_OPERAND 5 4 3 2 1 0 SECOND_OPERAND
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FOURTH_INS
THIRD_INS

0x0 This register contains the initialization sequence that is required to be executed by the Serial Flash controller to initialize the Serial Flash in the fast sequence boot mode for booting. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] FOURTH_OPERAND: Fourth operand. [27:24] FOURTH_INS: Fourth instruction to be executed by the Flash. [23:20] THIRD_OPERAND: Third operand. [19:16] THIRD_INS: Third instruction to be executed by the Flash. [15:12] SECOND_OPERAND: Second operand. [11:8] SECOND_INS: Second instruction to be executed by the Flash. [7:4] FIRST_OPERAND: First operand for the rst instruction. [3:0] FIRST_INS: First instruction to be executed by the Flash. 0001: CMD. 0010: ADD. 0011: STATUS_REG_DATA. 0100: MODE. 0101: DUMMY. 0110: DATA. 0111: WAIT. 1000: JUMP. 1111: STOP.
Rev B
FIRST_INS
65/77
Registers
SPI_QUAD_BOOT_SEQ_INIT2
SEVENTH_OPERAND EIGHTH_OPERAND
Quad boot sequence initialization 2

9 8 7 6 FIFTH_OPERAND 5 4 3 2 1 0 SIXTH_OPERAND
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SEVENTH_INS
EIGHTH_INS
SIXTH_INS
SPIBaseAddress + 0x014C R/W

0x0 This register contains the subsequent initialization sequence that is required to be executed by the Serial Flash controller to initialize the Serial Flash in the fast sequence boot mode for booting. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] EIGHTH_OPERAND: Eighth operand. [27:24] EIGHTH_INS: Eighth instruction to be executed by the Flash. [23:20] SEVENTH_OPERAND: Seventh operand. [19:16] SEVENTH_INS: Seventh instruction to be executed by the Flash. [15:12] SIXTH_OPERAND: Sixth operand. [11:8] SIXTH_INS: Sixth instruction to be executed by the Flash. [7:4] FIFTH_OPERAND: Fifth operand. [3:0] FIFTH_INS: Fifth instruction to be executed by the Flash.
66/77
Rev B
FIFTH_INS
Registers
SPI_QUAD_BOOT_READ_SEQ1
SECOND_OPERAND FOURTH_OPERAND THIRD_OPERAND
Quad boot read sequence 1

9 SECOND_INS 8 7 6 FIRST_OPERAND 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FOURTH_INS
THIRD_INS

0x0 This register contains the quad read sequence for reading data during boot in the quad mode. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] FOURTH_OPERAND: Fourth operand. [27:24] FOURTH_INS: Fourth instruction to be executed by the Flash. [23:20] THIRD_OPERAND: Third operand. [19:16] THIRD_INS: Third instruction to be executed by the Flash. [15:12] SECOND_OPERAND: Second operand. [11:8] SECOND_INS: Second instruction to be executed by the Flash. [7:4] FIRST_OPERAND: First operand for the rst instruction. [3:0] FIRST_INS: First instruction to be executed by the Flash.
Rev B
FIRST_INS
67/77
Registers
SPI_QUAD_BOOT_READ_SEQ2
SEVENTH_OPERAND
Quad boot read sequence 2

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EIGHTH_OPERAND SIXTH_OPERAND
FIFTH_OPERAND
SEVENTH_INS
EIGHTH_INS
SIXTH_INS
SPIBaseAddress + 0x0154 R/W 0x0 This register contains the quad read sequence for reading data during boot in the quad mode. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
68/77
Rev B
FIFTH_INS
Registers
SPI_PROGRAM_ERASE_TIME
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Program erase time

7 6 5 4 3 2 1 0
SPIBaseAddress + 0x0158 R/W 0x0

This register contains the page program/erase time required by the Flash. The required parameter must be written in this register by the software. The Serial Flash controller runs a counter based on this value to wait for the page program time/erase time to complete. The Serial Flash controller always initializes the counter with the value programmed in this register whenever it encounters a WAIT instruction in the sequence. The maximum delay that can be supported by this register is 21 ms.
[31:21] RESERVED [20:0] WAIT_TIME: Wait counter value in terms of EMISS clock cycles.
Rev B
WAIT_TIME
RESERVED
69/77
Registers
SPI_REPEAT_SEQ1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SECOND_OPERAND FOURTH_OPERAND THIRD_OPERAND SECOND_INS FOURTH_INS 9 8
Repeat sequence 1
7 6 FIRST_OPERAND 5 4 3 2 1 0
THIRD_INS
SPIBaseAddress + 0x015C R/W

0x0 This register contains the sequence required to be repeated during a multiple-page read/write operation. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
[31:28] FOURTH_OPERAND: Fourth operand. [27:24] FOURTH_INS: Fourth instruction to be executed by the Flash. [23:20] THIRD_OPERAND: Third operand. [19:16] THIRD_INS: Third instruction to be executed by the Flash. [15:12] SECOND_OPERAND: Second operand. [11:8] SECOND_INS: Second instruction to be executed by the Flash. [7:4] FIRST_OPERAND: First operand for the rst instruction. [3:0] FIRST_INS: First instruction to be executed by the Flash. 0001: CMD. 0010: ADD. 0011: STATUS_REG_DATA. 0100: MODE. 0101: DUMMY. 0110: DATA. 0111: WAIT. 1000: JUMP. 1111: STOP.
70/77
Rev B
FIRST_INS
Registers
SPI_REPEAT_SEQ2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SEVENTH_OPERAND EIGHTH_OPERAND SIXTH_OPERAND SEVENTH_INS 9 8
Repeat sequence 1
7 6 FIFTH_OPERAND 5 4 3 2 1 0
EIGHTH_INS
SIXTH_INS

0x0 This register contains the sequence required to be repeated during a multiple-page read/write operation. For more details on issuing instructions, refer to Table 6: Instruction set of the fast sequence mode.
Rev B
FIFTH_INS
71/77
Registers
SPI_STATUS_WR_TIME
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED WAIT_TIME 9 8 7
Status write time

6 5 4 3 2 1 0
SPIBaseAddress + 0x0164 RW 0x0 This register consists of the time required by the Flash to perform the write status register operation. The contents of this register are taken automatically by the Serial Flash controller whenever it encounters the STATUS_REG_DATA instruction in the sequence. The maximum delay that can be supported by this register is 21 ms.
[31:21] RESERVED [20:0] WAIT_TIME: Wait counter value in terms of EMISS clock cycles.
SPI_FAST_SEQ_DATAn
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA 9 8
Fast sequence data

7 6 5 4 3 2 1 0
SPIBaseAddress + 0x0300 + n * 0x04 (where n = 0 to 63) RW 0x0 These registers contain the data to be read from the Flash or the data to be written to the Flash. These registers can store up to 512 bytes of data. If the read from the Flash is being done then these registers store the data returned from the Flash. Therefore, the data can be read afterwards by the CPU or FDMA after the SPI_SEQ_DREQ signal is generated by the Serial Flash controller. If the data is being written to the Flash, the CPU/FDMA must write the required data in these registers once the SPI_DATA_DREQ signal is asserted.
[31:0] DATA: Data read from the Flash or data to be written in the Flash.
Note:
While writing data in the FIFO for a write operation, sufcient time (more then or equal to 10 spi_clocks ) should be provided to the controller to switch between read and write clocks. This requirement arises from the fact that the FIFO is shared between read and write operations. When a read sequence is followed by a write sequence, the fo read clock changes dynamically from stbus clock to spi clock and the fo write clock changes from spi clock to stbus clock. Hence, if a FIFO data write request is received during this period it gets missed. This time can be taken care if the sequence register programming is done during this duration.
72/77
Rev B
Software driver interface
10
10.1
Software driver interface

Command interface
Not applicable.
10.1.1
Commands
Not applicable.
Rev B
73/77
Patents and licenses
11
Patents and licenses

Not applicable.
74/77
Rev B
Serial Flash controller requirements
Appendix A
A.1
A.1.1
Performance calculations
Contiguous mode versus normal mode
In the normal mode, considering that Serial Flash is operating at the SPI_CLOCK frequency of 50 MHz, it takes approximately 700 SPI cycles to read 40 bytes of data. The same amount of contiguous data can be read in the contiguous mode in approximately 360 SPI cycles.
It indicates that if the frequency of SPI_CLOCK is 50 MHz then approximately 44 Mbit/s speed can be achieved with the contiguous mode (50 MHz x 320/360 = 44 Mbit/s). This theoretical improvement in the bandwidth is approximately two times as compared to the normal mode where maximum data rate achievable is approximately 22 Mb/sec at 50 MHz (50 x 320/700). For very long accesses, this data rate would approach to 50 Mbit/s. This is due to the fact that address cycle is shared between many data transfers and thus it becomes negligible.
Assumptions made for the above calculations
The next contiguous request must be received before eight SPI clocks cycles have elapsed from the time the valid next cycle signal is asserted for the performance improvement to be visible. The performance of the Serial Flash controller in the contiguous mode will degrade for non-contiguous request. In case a lot of non-contiguous requests are anticipated then it is advisable to run the Serial Flash controller in the non-contiguous mode (CONTIG_MODE = 0, that is, bit[0] of the SPI_MODE_SELECT register = 0). ATMEL apparently has changed protocol of its Serial Flash memories and ATMEL protocol has now become same as ST Serial-Flash protocol. This, however, can easily be supported by conguring new ATMEL memories with STNOTATMEL = 1. No special changes are made in IP due to new ATMEL memory protocol.
A.1.2
Dual output mode

Assuming the maximum frequency of EMISS as 100 MHz, the maximum speed of the serial clock would be 100 / 2 = 50 MHz. Thus, a maximum read performance of 100 Mbit/s is achieved in the dual output mode.
A.1.3
Fast sequence mode

Assuming the maximum frequency of EMISS as 100 MHz, the maximum speed of the serial clock would be 100 / 2 = 50 MHz. Thus, a maximum read performance of 200 Mbit/s is achieved in the quad I/O mode within a page.
Rev B
75/77
A.1.4
Performance comparison at a glance

The Table 21 gives a quick view of the performance efciency comparison of different Serial Flash controller modes. The throughput has been calculated for fetching 256 bytes data from the Flash and is provided in terms of the SPI_CLOCK cycles.
Table 21.
Performance comparison at a glance

Fast-sequence mode Dual output mode 3584 Normal mode with contiguous mode 2080 Fast read with contiguous mode 2088 Dual output with contiguous mode 1064
Legacy modes Normal mode 4096 Fast read mode 4608
x1
x2
x4
2088
1064
552
The contiguous mode throughput has been calculated keeping in view the best case when the STBus requests are contiguous and back-to-back. The performance would degrade otherwise.
A.2
Flashes supported by the Serial Flash controller

Table 22.
Numonyx M25P40 MP25PXX M45PEXX M25PE40
Parts supported from different manufacturers

WINBOND W25Q80 W25Q16 W25Q32 W25x10 Macronix MX25L1635D SST SST26VF016 SST26VF032 SST25LF020A SST25 Atmel AT25F4096 AT25FS040 AT45DBxxx
76/77
Rev B
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Rev B
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Serial Flash controller Generic IP block functional specication

Deboleena Minz/Sanjeev Varshney

Parul Agarwal/Sanjeev Varshney

Serial Flash controller functional specification

Sanjeev Varshney/Parul Agarwal

24-Mar-2011 16-May-2011 21-June-2011

3.2 3.3 3.4

Parul Agarwal Parul Agarwal Parul Agarwal

Serial Flash controller functional specification

IP block name and features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Hardware interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Detailed functional specication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Fast sequence mode functioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single-page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Serial Flash controller functional specification Fast sequence boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2 4.3 4.4 4.5

Routers and interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Pin group list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Serial Flash controller functional specification

Software driver interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Patents and licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Appendix A Serial Flash controller requirements . . . . . . . . . . . . . . . . . . . . . . . . 72

Flashes supported by the Serial Flash controller . . . . . . . . . . . . . . . . . . . 73

Serial Flash controller functional specification

Serial Flash controller functional specification

IP block name and features list

IP block name and features list

SPIRIT identication of serial_ash_controller

Serial Flash controller functional specification

EMISS system view

CPU Serial bus IC EMISS Padlogic Parallel bus FDMA

Serial Flash controller functional specification

System overview Table 3.

Serial Flash controller functional specification

Pad requirements for different Serial Flash congurations

Output pad Output pad

Serial Flash controller functional specification

Serial Flash controller

x2 pad connection (dual output mode)

System overview Figure 5.

SPI_CLK_ENB SPI_CLOCK SPI_CLOCK CLOCK

SPI_DATA_OUT_EN Serial Flash controller SPI_DATA_OUT SPI_DBL_DATA_IN DO DI

SPI_DATA_IN_ENB SPI_DATA_OUT_QUAD SPI_DATA_IN DI DO

Padlogic (SoC boundary)

Serial Flash controller functional specification Figure 6. x4 pad connection

SPI_CS_ENB SPI_NOT_CS SPI_CLK_ENB SPI_CLOCK SPI_CLOCK CLOCK CS CS

SPI_HOLD_ENB SPI_HOLD_OUT SPI_HOLD_IN HOLD HOLD

SPI_WR_PROTECT_ENB SPI_WR_PROTECT_OUT SPI_WR_PROTECT_IN WP WP

Padlogic (SoC boundary)

Comms integration guidelines

System overview Figure 7.

Serial Flash controller functional specification

Serial Flash controller legacy mode and comms multiplexing logic

COMMS_DATA_IN COMMS_CLOCK COMMS_DATA_OUT SPI_NOT_CS Padlogic /Gluue SPI_CLOCK SPI_DATA_OUT

SPI_NOT_CS SPI_CLOCK STBus EMI buffer SPI_DATA_OUT Serial Flash controller

System conguration register bit

Opcodes supported in different modes

Legacy modes Fast sequence mode

N/A LD 4/8/16/32 ST 4/8/16/32 N/A

Fast sequence boot mode LD4/8/16/32

Serial Flash controller functional specification

Serial Flash controller dreq connection

SPI_SEQ_DREQ ILC3 SPI_DATA_DREQ

Detailed functional specification

Serial Flash controller functional specification