Chapter 1. Digital System Design Automation with Verilog 1 1.1 Digital Design Flow 2 1.1.1 Design entry 3 1.1.

2 Testbench in Verilog 4 1.1.3 Design validation 4 1.1.4 Compilation and synthesis 7 1.1.5 Postsynthesis simulation 10 1.1.6 Timing analysis 10 1.1.7 Hardware generation 10 1.2 Verilog HDL 10 1.2.1 Verilog evolution 11 1.2.2 Verilog attributes 11 1.2.3 The Verilog language 13

Chapter 2. Register Transfer Level Design with Verilog 2.1 RT Level Design 2.1.1 Control/data partitioning 2.1.2 Data part 2.1.3 Control part 2.2 Elements of Verilog 2.2.1 Hardware modules 2.2.2 Primitive instantiations 2.2.3 Assign statements 2.2.4 Condition expression

2.2.5 Procedural blocks 2.2.6 Module instantiations 2.3 Component Description in Verilog 2.3.1 Data components 2.3.2 Controllers 2.4 Testbenches 2.4.1 A simple tester 2.4.2 Tasks and functions

Chapter 3. Verilog Language Concepts 3.1 Characterizing Hardware Languages 3.1.1 Timing 3.1.2 Concurrency 3.1.3 Timing and concurrency example 3.2 Module Basics 3.2.1 Code format 3.2.2 Logic value system 3.2.3 Wires and variables 3.2.4 Modules 3.2.5 Module ports 3.2.6Names 3.2.7 Numbers 3.2.8 Arrays 3.2.9 Verilog operators

3.2.10 Verilog data types 3.2.11 Array indexing 3.3 Verilog Simulation Model 3.3.1 Continuous assignments 3.3.2 Procedural assignments

3.4 Compiler Directives 3.4.1 `timescale 3.4.2 `default-nettype 3.4.3 `include 3.4.4 `define 3.4.5 `ifdef, `else,`endif 3.4.6 `unconnected-drive 3.4.7 `celldefine,`endcelldefine 3.4.8 `resetall

3.5 System Tasks and Functions 3.5.1 Display tasks 3.5.2 File I/O tasks 3.5.3 Timescale tasks 3.5.4 Simulation control tasks 3.5.5 Timing check tasks 3.5.6 PLA modeling tasks 3.5.7 Conversion functions for reals

3.5.8 Other tasks and functions

Chapter 4. Combinational Circuit Description 4.1 Module Wires 4.1.1 Ports 4.1.2 Interconnections 4.1.3 Wire values and timing 4.1.4 A simple testbench 4.2 Gate Level Logic 4.2.1 Gate primitives 4.2.2 User defined primitives 4.2.3 Delay formats 4.2.4 Module parameters 4.3 Hierarchical Structures 4.3.1 Simple hierarchies 4.3.2 Vector declarations 4.3.3 Iterative structures 4.3.4 Module path delay 4.4 Describing Expressions with Assign Statements 4.4.1 Bitwise operators 4.4.2 Concatenation operators 4.4.3 Vector operations 4.4.4 Conditional operation 4.4.5 Arithmetic expressions in assignments

4.4.6 Functions in expressions 4.4.7 Bus structures 4.4.8 Net declaration assignment 4.5 Behavioral Combinational Descriptions 4.5.1 Simple procedural blocks 4.5.2 Timing control 4.5.3 Intra-assignment delay 4.5.4 Blocking and nonblocking assignments 4.5.5 Procedural if-else 4.5.6 Procedural case statement 4.5.7 Procedural for statement 4.5.8 Procedural while loop 4.5.9 A multilevel description 4.6 Combinational Synthesis 4.6.1 Gate level synthesis 4.6.2 Synthesizing continuous assignments 4.6.3 Behavioral synthesis 4.6.4 Mixed synthesis Chapter 5. Sequential Circuit Description 5.1 Sequential Models 5.1.1 Feedback model 5.1.2 Capacitive model 5.1.3 Implicit model 5.2 Basic Memory Components

5.2.1 Gate level primitives 5.2.2 User defined sequential primitives 5.2.3 Memory elements using assignments 5.2.4 Behavioral memory elements 5.2.5 Flip-Flop timing 5.2.6 Memory vectors and arrays 5.3 Functional Registers 5.3.1 Shift registers 5.3.2 Counters 5.3.3 LFSR and MISR 5.3.4 Stacks and queues 5.4 State Machine Coding 5.4.1 Moore machines 5.4.2 Mealy machines 5.4.3 Huffman coding style 5.4.4 A more modular style 5.4.5 A ROM based controller 5.5 Sequential Synthesis 5.5.1 Latch models 5.5.2 Flip-flop models 5.5.3 Memory initialization 5.5.4 General sequential circuit synthesis Chapter 6. Component Test and Verification 6.1 Testbench

6.1.1 Combinational circuit testing 6.1.2 Sequential circuit testing 6.2 Testbench Techniques 6.2.1 Test data 6.2.2 Simulation control 6.2.3 Limiting data sets 6.2.4 Applying synchronized data 6.2.5 Synchronized display of results 6.2.6 An interactive testbench 6.2.7 Random time intervals 6.2.8 Buffered data application 6.3 Design Verification 6.4 Assertion Verification 6.4.1 Assertion verification benefits 6.4.2 Open verification library 6.4.3 Using assertion monitors 6.4.4 Assertion templates 6.5 Text Based Testbenches Chapter 7. Detailed Modeling 7.1 Switch Level Modeling 7.1.1 Switch level primitives 7.1.2 The basic switch 7.1.3 CMOS gates 7.1.4 Pass gate logic

7.1.5 Switch level memory elements 7.2 Strength Modeling 7.2.1 Strength values 7.2.2 Strength used in resolution 7.2.3 Strength reduction

Chapter 8. RT Level Design and Test 8.1 Sequential Multiplier 8.1.1 Shift-and-add multiplication process 8.1.2 Sequential multiplier design 8.1.3 Multiplier testing 8.2 von Neumann Computer Model 8.2.1 Processor and memory model 8.2.2 Processor model specification 8.2.3 Designing the adding CPU 8.2.4 Design of datapath 8.2.5 Control part design 8.2.6 Adding CPU Verilog description 8.2.7 Testing adding CPU 8.3 CPU Design and Test 8.3.1 Details of processor functionality 8.3.2 SAYEH datapath 8.3.3 SAYEH Verilog description 8.3.4 SAYEH top-level testbench

8.3.5 Sorting test program 8.3.6 SAYEH hardware realization