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A Simple Snubber Conguration for Three-Level GTO Inverters

Jeong-Hyoun Sung, Student Member, IEEE, and Kwanghee Nam, Member, IEEE
Abstract A simple snubber conguration for three-level gate turn-off thyristor (GTO) inverters is proposed. The proposed snubber has a single resistor per arm for stored energy dissipation, while the conventional RLD/RCD snubber contains six. This implies that the proposed snubber needs only one chopper circuit per arm for snubber energy recovery. This helps reduce the size, cost, and number of components. Besides the single resistor, the proposed snubber requires two less diodes per arm than the RLD/RCD snubber. Furthermore, the proposed snubber resolves the voltage imbalance problem between inner and outer GTOs without additional components. We have analyzed the proposed circuits and proven its performance through simulations and experiments. Index Terms Energy recovery circuit, snubber circuit, threelevel GTO inverter.

I. INTRODUCTION N HIGH-POWER systems, such as a steel mill drive, gate turn-off thyristors (GTOs) are widely used. Due to the high-power rating (6 kV, 6 kA) and the turn-off capability, GTOs are much more attractive than conventional thyristors for sophisticated applications. GTOs, however, require a snubber circuit which limits the current and voltage rising rate at the time of turning on and off, respectively. When turning on must be restricted below a a GTO, the current rising rate specied value to prevent an excessive initial current loading. also When turning off a GTO, the voltage rising rate must be restricted below a specied value to avoid a sudden heat pulse generation and to prevent retriggering by an internal capacitance. A number of snubber congurations have been proposed for two-level GTO voltage source inverters [1][3]: the RLD/RCD snubber, Undeland snubber, and McMurray snubber [1], [2]. The Undeland and McMurray snubbers are modied from the RLD/RCD snubber, minimizing the number of snubber circuit components. Specically, they have a single resistor per arm for energy dissipation. This is particularly useful in constructing an energy recovery circuit. Holtz has investigated an energy recovery circuit for the McMurray snubber that did not employ a chopper [3]. The three-level inverter, often called a neutral point clamped (NPC) inverter, is suitable for high-voltage applications since it guarantees equal voltage sharing between serially connected

power devices. Furthermore, the three-level conguration contributes to reducing voltage harmonics [4][8]. For the three-level system, the RLD/RCD snubber could be constructed as shown in Fig. 1(a), but is impractical for energy recovery, since it requires six discharging resistors in separate locations on each arm. Furthermore, such a snubber would cause a voltage imbalance between serially connected GTOs or turns off, since the middle snubber when either do not nd their discharging paths due to capacitors This the blocking action of the clamping diodes imbalance imposes higher voltage stress on the inner GTOs and may lead to a destruction of inner GTOs. Okayama et al. [6] proposed a snubber circuit which is able to locate energy recovery choppers at points of xed voltage, such as at the dc-link side or the neutral point. Hence, the chopper bank capacitors can be connected in parallel among arms yielding a suitable structure for energy recovery. It also has some noticeable characteristics such as a guaranteed voltage balancing mechanism between serially connected GTOs and a reduced capacitance of turn-off snubbers. However, it has more components, compared with the RLD/RCD snubber. On the other hand, Suh et al. extended the Undeland snubber to the three-level system with overvoltage clamping capability. This paper presents a new and efcient snubber conguration for three-level GTO inverters. The proposed snubber conguration can be regarded as an extension of the McMurray snubber [1] to the three-level system. Advantages of the proposed scheme are: 1) small number of parts; 2) suitable structure for snubber energy recovery; 3) secondorder current dynamics in the period of the snubber capacitor discharging; and 4) no voltage imbalance between serially connected GTOs. We have analyzed the proposed circuit, and proven its performance through simulations and experiments. II. NEW SNUBBER CONFIGURATION FOR THREE-LEVEL GTO ARM A. Structure The RLD/RCD snubber and the proposed snubber circuits for a single arm appear in Fig. 1. The proposed snubber circuit ), two seincludes four shunt capacitors ( ), four diodes ( ), ries inductors ( and a single resistor ( ). Table I compares the number of components for the RLD/RCD snubber and the proposed snubber. The proposed snubber includes a single resistor, while the RLD/RCD snubber has six resistors. When a need to construct an energy recovery system occurs, the advantage

Manuscript received July 10, 1997; revised July 17, 1998. Recommended by Associate Editor, L. Xu. The authors are with the Department of Electrical Engineering, POSTECH University, Pohang 790-784, Korea. Publisher Item Identier S 0885-8993(99)01825-6.

08858993/99$10.00 1999 IEEE

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(a) Fig. 1. Snubber circuits for a three-level GTO arm: (a) RLD/RCD snubber and (b) proposed snubber.

(b)

TABLE I THE NUMBER OF SNUBBER CIRCUIT COMPONENTS

of the proposed snubber is quite clear in the number of chopper circuits, i.e., the proposed snubber requires one chopper circuit, while the RLD/RCD snubber requires at least four. Furthermore, the proposed snubber has two less diodes. We and for symmetry. We also choose let B. Overview of the Basic Principle Before the detailed analysis, we will briey describe the and are basic functions of the proposed snubber. If is completely discharged and is charged turned on, in the steady state. When begins to turn off to ows out, a commutation path is in case load current and Finally, the current path is made made through so that is charged to through the clamping diode and discharged to zero. and is Furthermore, since the common node of and through connected to the common node of , the capacitors in the lower part are also disand to zero and , respectively. charged from Therefore, all capacitors participate in determining the voltage growth rate of a switch. Due to the symmetry of the circuit, the same logic applies in determining the voltage growth rates and Specically, if is small, the voltage of , growth rate is determined by the sum i.e., (1) where and and are the voltages over , respectively. We can see from

(1) that the required capacitance of the proposed circuit is less than half of the capacitance of the RLD/RCD snubber. However, the voltage rating of and must be two times larger than that of the RLD/RCD snubber. In the McMurray snubber [1], [9], the same thing happens. Thus, the proposed snubber can be looked upon as an extended version of the McMurray snubber to the three-level case. Another characteristic feature of this snubber is the location of the inductors. They are located between the serially connected GTOs, rather than on the dc-link sides. In this McMurray-type snubber, an inductor cannot reside on the dclink side because the stored eld energy cannot be dissipated. Furthermore, we cannot place an inductor at the load terminal because the inductors cannot play any role in limiting the and If we put inductors between current rising rates of serially connected GTOs as shown in Fig. 1(b), we can circumvent the above-mentioned problems. An advantage of in the blocking stage is not affected such location is that by the turning off process of Since an inductor is absent on the dc-link side in the proposed snubber circuit, we can obtain, from the Kirchconstant, hoffs voltage law, that and denote voltages over and , where respectively. Therefore, we obtain (2) For the same reason, we obtain (3) Equations (2) and (3) play the crucial role in simplifying the circuit analysis which follows. and are shown in the discharging paths Inductors and , but not in the discharging paths of and of Hence, the capacitance of and needs to be and , to prevent a large chosen small, compared with are turning on. We choose the current loading when and to be one tenth of and , capacitance of , but i.e., we let

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(a) Fig. 2. Commutation paths during the transition from

(b)
S0

(c) to
S1 :

(d)

(a) Initial state. (b) Step 1. (c) Step 2. (d) Step 3.

TABLE II THREE SWITCHING STATES

cannot be eliminated. If and imbalance between off. III. ANALYSIS

OF

do not exist, then the voltage takes place when is turning

(a)

(b)

SWITCHING SEQUENCES

All possible switching states of the three-level inverter are listed in Table II. Due to the symmetry, it is sufcient to consider only a complete cycle of commutation assuming that the load current is owing out. We have not considered the direct transition of states from to , or from to , since they are unnecessary. We is constant during the whole assume that load current commutation process and thus model it by a current source [9]. A. Commutation from to

(c) Fig. 3. Equivalent circuits during the transition from

S0

to

S1 :

In this commutation, is turned off, and after a dead time, is turned on. Commutation sequences and the equivalent circuits are shown in Figs. 2 and 3. As an initial state, we assume that the load current is owing through the clamping and as shown in Fig. 2(a). Snubber capacitors diode are assumed to be charged up to , and are assumed to be totally discharged. Note that turning does not make any difference in this process since off of no current ows though it. turning on. In this period, Step 1): Step 1 begins with increases, while the current through the current through decreases. Even though is turned on, the discharging is not formed since the load terminal current path of as far as conducts. voltage remains the same value, Neglecting In this step, the inductor voltage is kept at is the diode recovery current, the current increase through and determined by , where are the currents owing through and the clamping diode , respectively. the inductor and We thus obtain Hence, the load current is completely transferred to at from

Step 2): In Step 2, the current through continues to ceases to conduct, increase. As soon as clamping diode and the load terminal voltage goes up, charging and discharging The discharging loop is formed as shown in Fig. 2(c). through Its equivalent circuit for this step is shown in Fig. 3(b). Since , we obtain from (2) that

(4) where from Fig. 3(b) that Hence, we obtain

(5) Note on the other hand that (6) Therefore, it follows from (5) and (6) that (7)

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Applying Kirchhoffs current law (KCL) at point P in Fig. 3(b) and using (3) and (4), we obtain

nds a discharging path through so that the is discharged (to ). Therefore, overvoltage across the proposed scheme does not cause an imbalance problem. is completely discharged and is conIn Step 3, does not appear in the equivalent circuit ducting. Hence, as shown in Fig. 3(c). Thus, we obtain (15)

(8) and Since constant, we have (8) and using (4) and (7), we obtain is assumed to be Then, differentiating

(16) Using (16) that , we obtain from (15) and

(9) is not that large in governing the oscillatory motion, Since to be zero for computational convenience. we assume Then, (9) reduces to (10) and its solution is given by

(17) Since such that is small, (17) yields the underdamped solution

(18) (11) where where obtained such that for Thus, the corresponding solutions are and At the end is completely discharged and and of this step, are charged to and respectively. B. Commutation from (13) to

(12) In this commutation, is turned off, and after a dead is turned on. We assume that the initial state is the time, nal state of the previous commutation. During the turning off , the load current rejected by is absorbed by period of and as shown in Fig. 4(b). At the same time, and also play roles in limiting the voltage rising rate of Commutation sequences and the equivalent circuits are shown in Figs. 4 and 5. This commutation process is separated by following three steps. decreases linearly from to zero during Step 1): for this period, i.e., When the tail current of is neglected, we obtain from the equivalent circuit shown in Fig. 5(a) that (19) (20)

(14) in the capacitor chargExistence of the inductor ing/discharging path makes the dynamics of the loop a second-order system, thus causing a current to overshoot. In other words, the second-order system, differently from the rst-order system, does not make the current peak at the beginning, but after a certain time elapses. This helps reduce the initial current loading of GTOs and is another characteristic feature that makes this proposed snubber look like the McMurray snubber. This step ends when reaches its maximum. At the end at and and of this step, , i.e, and are charged to and respectively. Step 3): The current overshoot made in Step 2 decreases in Step 3. During this period, a voltage is developed over with positive polarity on the side. This makes a Such a voltage overshoot usually voltage overshoot over makes a voltage imbalance between the inner and outer GTOs and ) in the RLD/RCD snubber since clamping diode ( blocks the discharging path of inner GTO [8]. With the proposed scheme, however, snubber capacitor

(21) Using (2), we obtain from (20) that Therefore, differentiating (19) and using (21), we obtain (22)

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(a) Fig. 4. Commutation paths during the transition from

(b)
S1

(c) to
S0 :

(d)

(a) Initial state. (b) Step 1. (c) Step 2. (d) Step 3.

where To asceris small tain a simple solution, we may assume that of Step 2. Then, is compared with the period, Hence, it follows approximated to be a constant from (25) that for

(a)

(b)

(28) may not be true, but The assumption does not change the resulting error is not so large if while is conducting. Thus, much. Note that differentiating (28) with respect to , we obtain Note that this result is identical to (1). is charged to , the clamping Step 3): After begins to conduct and the eld energy in diode dissipates through as shown in Fig. 4(d). Due to the dissipation current, a voltage overshoot is generated over Note from Fig. 5(c) that and Thus, it follows that (29) (23) With the initial conditions , we obtain the solution and its corresponding that for

(c) Fig. 5. Equivalent circuits during the transition from

S1

to S0 :

Hence, its solution is given by

when reduces to zero. This step ends at ows through Step 2): In Step 2, the load current charging and discharging and diode Using and again, we obtain from Fig. 5(b) that (24) (25) Thus, it follows from (24) and (25) that (26) As an initial value, we use

such (30)

(31) where and In the last step, the inductor current decreases to zero, and all the load current ows through the When turns on after a dead time, the clamping diode whole commutation is completed. C. Commutation from to

which is the nal value of Step 1. Then, the solution is given by (27)

In this commutation, is turned off, and after a dead time, is turned on. At the initial state, are charged and are completely discharged. Also up to along with in this commutation, snubber capacitors

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(a) Fig. 6. Commutation paths during the transition from

(b)
S0

(c) to
S

(d)

01

(a) Initial state. (b) Step 1. (c) Step 2. (d) Step 3.

(a)

(b)

Step 2): The equivalent circuit of Step 2 is shown in Fig. 7(b). Note that this equivalent circuit is identical to Fig. 5(b), since is assumed to be constant. Therefore, the solution is given by which is the same as (28). This step ends at when reaches Step 3): Due to the current owing through , a voltage This voltage overshoot will overshoot is generated over We obtain disappear soon in the current loop from Fig. 7(c) that (35) For simplicity, we assume that obtain from (35) that is equal to zero. Then, we

(36) (37)
(c) Fig. 7. Equivalent circuits during the transition from S0 to
S

01

Applying KCL at point P in Fig. 7(c) and using (36), (37), and obtained from , we obtain (38) and With the initial conditions , the solution and corresponding values are obtained such that (39)

limit the voltage rising rate of At the nal state, the load current ows through the freewheeling diodes and Commutation sequences and the equivalent circuits are shown in Figs. 6 and 7. is turned off, the load current rejected Step 1): When is absorbed by both and as shown in Fig. 6(b). by turn-off operation, the voltage over remains During the while the voltage over increases. In Step 1, decreases linearly from to zero during the period, i.e, We obtain from Fig. 7(a) that (32) (33) Note that the derivation process of (33) is similar to that of (20). We obtain from (32) and (33) that (34) is the same which is identical to (22). Hence, its solution when reduces to zero. as (24). This step ends at

(40) where IV. ENERGY RECOVERY CIRCUITS In high-power inverter systems, it is common to recover the energy stored in the snubber circuits [6], [12], [13]. To recover the energy into the dc-link capacitor, a chopper circuit is used in place of a dissipation resistor. Note again that our proposed on each arm. Thus snubber has only one dissipation resistor only one chopper per arm can handle the energy recovery as shown in Fig. 8(a). Note that the number of choppers can be reduced further to one for an inverter by using the isolation transformers as shown in Fig. 8(b). In Fig. 8(a), the snubber

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(a) Fig. 8. Energy recovery circuit. (a) For an arm. (b) Three-arm integration to a single chopper.

(b)

resistor is replaced by a capacitor to which charges are transferred whenever the stored in is discharging paths are formed. If the capacitance of (for example, 100 times), can sufciently larger than be regarded as a voltage source. If the voltage level over exceeds a threshold level, then the two insulated gate bipolar transistors (IGBTs) begin to switch alternately. Energy can then be delivered to the dc link during both turn-on and turnoff periods. Energy transfer during the on period, however, is undesirable because the current may go beyond the limits of IGBT or diode rating. Hence, the turn ratio of the transformer is chosen such that the energy is transferred during the turnoff period (yback chopper) [10], [11]. Using the two IGBTs prevents the magnetization of the transformer [1], [3]. We calculate the total energy transfer from the snubber in a inductors and capacitors to storage capacitor pulsewidth modulation (PWM) cycle. The stored energy in is transferred to the storage capacitor when inductor turns off from a conducting state [see Figs. 4(d) and 10] and is equal to

In the second case, the transferred energy is equal to (43) Therefore, for the PWM sequence , neglecting the diode recovery current, the total energy per arm is equal to transferred to

(44) Thus, the chopper size or the power rating of dissipation resistor must be estimated based on (44). V. DESIGN PROCEDURE AND SIMULATION RESULTS Based on the circuit analysis, we may summarize the design procedure of the proposed snubber components. A. Design Procedure We assume that a proper GTO is selected for an inverter, and maximum load current with a specied dc-link voltage From the GTO manufacturers specication, we obtain and a the critical rate of rise of off-state voltage maximum rate of rise of on-state current Step 1) (Capacitor): Choose capacitance such that and The voltage rating of capacitors and should meet Step 2) (Inductor): Choose inductance such that Obviously, current rating of inductor should be larger than Step 3) (Resistor): To ensure safe discharging during such that turn-on period, it is normal to choose , where is the minimum turn-on time of the GTO. The power rating of the resistor

(41) In calculating the transferred energy from the snubber , we neglect since they are small capacitors to There are two operations in the compared with change: when changes from to zero and when changes from to The amount of transferred energy for the two cases is different. In the rst case, the transferred energy is equal to (42)

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Fig. 9. Simulation results (S0 to vCS 1 ; vCS 2 ; and (d) vCS 3 ; vCS 4 :

S1 ):

(a)

LS1 ; iDC 1 ;

(b)

LS1 ;

(c)

Fig. 10. Simulation results (S1 to vCS 1 ; vCS 2 ; and (d) vCS 3 ; vCS 4 :

S0 ):

(a)

LS1 ; iDC 1 ;

(b)

G1 ;

(c)

must be larger than , where is the PWM switching frequency [see (44)]. For the experiment, we chose a GTO (ABB 5SGA A, 1028F0001) with the following ratings: V, V/ s, and A/ s, where is the repetitive peak off-state voltage and is the maximum controllable turn-off current. For a V/ s. Additionally, the safe turn off, we limit A. maximum load current is assumed to be F. Hence, We then obtain from Step 1) that F and F. For we choose A/ s. Conforming a safe turn-on, we choose H. Since s, to Step 2), we choose according to the inequality in Step 3). we let B. Simulation Results All the simulations were carried out for a three-level single arm using the commercial simulation tool SABER with example parameters which are described in the previous subsection. V and We further assume that A. Voltage and current transitions in the three basic are shown in commutations clamping Figs. 911. Fig. 9 shows the inductor current inductor voltage and capacitor diode current during the commutation from voltages to off, on). One can notice from Fig. 9(a) and helps reduce the current (b) that the presence of inductor Note from Fig. 9(a) that is 260 growing rate of is almost 1000 A A/ s, and the peak turn-on current of while the load current is 300 A. This relatively large current overshoot is caused, in part, by the charging current of and and results in a voltage overshoot over as shown in Fig. 9(d).

Fig. 11. Simulation results (S0 to vCS 1 ; vCS 2 ; and (d) vCS 3 ; vCS 4 :

01 ):

(a)

LS2 ; iDC 1 ;

(b)

G2 ;

(c)

TABLE III COMPARISON OF DATA OBTAINED FROM ANALYSIS AND SIMULATION (ED = 2600 V, ILOAD = 300 A)

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Fig. 12. Simulation results of energy recovery circuit. (a) The storage capacitor voltage vCSS . (b) The load terminal voltage. (c) The voltage of the secondary coil. (d) The voltage of the primary coil.

, the anodecathode voltage of , and during the commutation from to ( off, on). One should notice from Fig. 10(c) and are the same that the voltage rising rates of increases without affecting (158 V/ s), showing that The voltage overshoot over caused by the current decrease is about 340 V [see Fig. 10(c)]. The current decreasing in rate of the inductor is about 65 A/ s. , the anodecathode voltage of Fig. 11 shows , and during the commutation from to ( off, on). One can check from Fig. 11(b) (165 V/ s) is about the that the voltage rising rate of shown in Fig. 10(b). The voltage overshoot same as that of caused by the current increase in is about 340 over V [see Fig. 11(b) and (c)]. We can observe from Figs. 911 and that substantiates (2) and (3), with no voltage imbalance problem between the serially connected GTOs in the blocking state. To verify the previous analytical results, we have computed analytically by using (15), the values of (18), (28), (31), and (40) and numerically by using SABER. Table III shows both results. Since some assumptions are used in obtaining the analytical solutions, both results are not identical, but agree within a reasonable amount. SABER simulation results of the energy recovery circuit are shown in Fig. 12. We simulated the chopper with a constant switching frequency (2 kHz). Fig. 12(a) shows the over ; Fig. 12(b) shows the load terminal voltage voltage; Fig. 12(c) shows the voltage of the secondary coil; and Fig. 12(d) shows the voltage of the primary coil. We can see from the load terminal voltage that the switching is repeated. Energy sequence

Fig. 10 shows

is transferred to the dc link during the turn-off period of the chopper switches, and one can check it by the clamped voltage of the secondary coil. remains around 220 V. VI. EXPERIMENTAL RESULTS A three-level GTO converter/inverter system for an induction motor (500 kW, 3300 V) was constructed with commercial GTOs (ABB 5SGA 1028F0001). A digital signal processor (DSP) processor TMS320C31 was used in the control boards. A space-vector modulation technique was used to generate three-level PWM signals and was implemented in EPLD by utilizing counters and digital comparators. The PWM signals were transmitted to the GTO gate amps through optical bers. Snubber parameters were the same used in the simulation, but a different environment caused us to perform the experiment V and A. with and when is turning Fig. 13(a) shows to The load current on during the commutation from is 100 A/ s. is about 85 A, and the current rising rate of Fig. 13(b) shows the corresponding voltage over inductor and the anodecathode voltage of The experimental condition and the simulation conditions are different, but one can compare the voltage and current transition shapes. A simulation result shown in Fig. 9 corresponds to Fig. 13. When we compare both gures, the shapes agree, except for a large current undershoot and a relatively large residual voltage oscillation observed in Fig. 13(a) and (b). The large current undershoot is caused by the snubber diode reverse recovery current. The residual voltage oscillation might be caused by the parasitic capacitance and inductance of the circuit. We can note from Fig. 13(b) that the voltage developed over the inductor , thus contributing a induces a sudden voltage drop in reduction of the turn-on switching loss.

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(a) Fig. 13. Experimental plots during the transition from

S0

(b) to
S1 :

(a)

LS

1;

CS

1;

CS

2:

(b)

LS

1;

G1 :

(a) Fig. 14. Experimental plots during the transition from

S1

(b) to
S0 :

(a)

LS1 ; vCS1 ; vCS2 :

(b)

CS1 ; vG1 :

Fig. 14(a) shows and when is turning to The current decreasing off during the transition from is 15 A/ s under 85-A load current. Fig. 14(b) rate of and the corresponding shows the capacitor voltage

anodecathode voltage of Fig. 14(b) shows that the is controlled at 38 V/ s by the action of rising rate of The corresponding simulation result, although in different condition, is shown in Fig. 10.

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(a) Fig. 15. Experimental plots during the transition from

S0

(b) to
S

01

(a)

LS

2;

CS

1;

CS

2:

(b)

CS

2;

G2 :

TABLE IV COMPARISON OF DATA OBTAINED FROM ANALYSIS AND EXPERIMENTS (ED = 1000 V, ILOAD = 85 A)

Fig. 15(a) shows and when is turning to Fig. 15(b) also shows off during the transition from and the anodecathode voltage of The rising rate is about 42 V/ s, which is about the same value as that of shown in Fig. 14(b). Note further that from Fig. 15(b), of reaches V after the anodecathode voltage of overshoot, but in the RLD/RCD snubber circuit, it can stay at , due the maximum overshoot value, without returning to The corresponding simulation to the blocking action of result, although in a different condition, is shown in Fig. 11. From all experimental gures, we can see that the voltage are the same, which veries (2). rising rates of Table IV shows data obtained from analytical solutions and experimental results. We can see that both results agree, within a small range for error or minor adjustments. VII. CONCLUDING REMARKS A simple snubber circuit is proposed for a three-level GTO inverter/converter. In the proposed snubber circuit, all snubber capacitors in an arm participate in limiting the voltage rising rate of a GTO. Furthermore, an inductor is also integrated into the capacitor circuit, thus there is no extra inductor energy discharging circuit. From these facts, the proposed snubber

can be looked upon as an extended version of the McMurray snubber for the three-level system. The characteristics of the proposed snubber are: 1) small number of parts, especially a reduced number of resistors; 2) suitable structure for snubber energy recovery; 3) second-order current discharging dynamics relieving the large initial current loading to GTOs; 4) guaranteed voltage balancing mechanism between serially connected GTOs; 5) reduced capacitance of snubber capacitors. Simulation and experimental works have demonstrated the validity of the proposed snubber. REFERENCES
[1] W. McMurray, Efcient snubbers for voltage-source GTO inverters, IEEE Trans. Power Electron., vol. PEL-2, pp. 264272, July 1987. [2] T. Undeland, F. Jenset, A. Steinbakk, T. Rogne, and M. Hernes, A snubber conguration for both power transistor and GTO PWM inverters, in IEEE PESC Rec., 1984, pp. 4253. [3] J. Holtz and K. H. Werner, A nondissipative snubber circuit for highpower GTO inverters, IEEE Trans. Ind. Applicat., vol. 25, no. 4, pp. 620626, 1989. [4] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Applicat., vol. 17, no. 5, pp. 518523, 1981. [5] S. Tamai et al., 3 level GTO converter-inverter pair system for large capacity induction motor drive, in EPE Annu. Meeting Conf. Rec., vol. 13, Sept. 1993, pp. 4550. [6] H. Okayama, M. Koyama, S. Tamai, and T. Fuji, Large capacity high performance 3-level GTO inverter system for steel main rolling mill drives, in Conf. Rec. IAS Annu. Meeting, 96, pp. 174179. [7] J. H. Suh, B. S. Suh, and D. S. Hyun, A new snubber circuit for high efciency and overvoltage limitation in three-level GTO inverters, IEEE Trans. Ind. Applicat., vol. 44, no. 2, pp. 145156, 1997. [8] B. S. Suh and D. S. Hyun, A circuit design for clamping an over-voltage in three-level GTO inverters, in IECON 94, pp. 651656.

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[9] G. Seguier and F. Labrique, Power Electronic Converters. New York: Springer-Verlag, 1993. [10] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [11] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics. New York: Wiley, 1995. [12] J. A. Tauq and Y. Shakweh, New snubber energy recovery scheme for high power traction drive, in IPEC-Yokohama 95, pp. 825830. [13] S. Irokawa, T. Kitahara, F. Kchikawa, and T. Nakajima, A new snubber energy recovery method for voltage source self-commutated converters, in IPEC-Yokohama 95, pp. 15721577.

Kwanghee Nam (S83M86) was born in Seoul, Korea, on September 26, 1956. He received the B.S. degree in chemical technology and the M.S. degree in control and instrumentation engineering, both from Seoul National University, Seoul, in 1980 and 1982, respectively, and the M.A. degree in mathematics and the Ph.D. degree in electrical engineering from the University of Texas, Austin, in 1986. He is currently an Associate Professor in the Department of Electrical Engineering, POSTECH University, Pohang, Korea. His main interests are ac motor control, highpower drives, power converters, and nonlinear systems analysis.

Jeong-Hyoun Sung (S96) was born in Pusan, Korea, on August 6, 1970. He received the B.S. and M.S. degrees in electrical engineering from POSTECH University, Pohang, Korea, in 1995 and 1997, respectively. He is currently working towards the Ph.D. degree in electrical engineering at POSTECH University. His main interests are ac motor control and power inverter/converter systems.