SRI KRISHNA COLLEGE OF ENGINEERING & TECHNOLOGY DEPARTMENT OF COMPUTER SIENCE AND ENGINEERING SUBJECT NAME: COMPUTER ORGANIZATION

AND ARCHITECTURE 2 MARKS QUESTION AND ANSWER UNIT-I BASIC STRUCTURE OF COMPUTERS 1.Define Computer Architecture Computer Architecture Is Defined As The Functional Operation Of The Individual H/W Unit In A Computer System And The Flow Of Information Among The Control Of Those Units. 2.Define Computer H/W Computer H/W is The Electronic Circuit And Electro Mechanical Equipment That Constitutes the Computer 3. What are the functions of control unit? The memory arithmetic and logic, and input and output units store and process information and perform i/p and o/p operation, the operation of these unit must be co ordinate in some way this is the task of control unit the cu is effectively the nerve center that sends the control signal to other units and senses their states. 4. What is an interrupt? An interrupt is an event that causes the execution of one program to be suspended and another program to be executed. 5. What are the uses of interrupts? Recovery from errors Debugging Communication between programs Use of interrupts in operating system 6.What is the need for reduced instruction chip? Relatively few instruction types and addressing modes. Fixed and easily decoded instruction formats. Fast single-cycle instruction execution. Hardwired rather than microprogrammed control. 7. Name any three of the standard I/O interface. SCSI (small computer system interface),bus standards Back plane bus standards IEEE 796 bus (multibus signals) NUBUS IEEE 488 bus standard 8. Differentiate between RISC and CISC RISC Reduced Instruction Set Computer Simple instructions take one cycle per Operation. CISC Complex Instruction set computer Complex instruction take multiple Cycles per operation.

Few instructions and address modes are Many instruction and address Modes. used Fixed format instructions are used Variable format instructions are used Instructions are compiled and then executed by Instructions are interpreted by the hardware. Microprogram and then executed. RISC machines are multiple register set. Complexity in the compiler RISC machines are higly piplined CISC machines use single register Set. Complexity in the microprogram CISC machines are not piplined

9. Explain the various classifications of parallel structures. SISD (single instruction stream single data stream SIMD(single instruction stream multiple data stream MIMD(multiple instruction stream multiple data stream MISD(multiple instruction stream single data stream 10. What is absolute addressing mode? The address of the location of the operand is given explicitly as a part of the instruction. Eg. Move a , 2000 11. Specify three types of data transfer techniques. Arithmetic data transfer Logical data transfer Programmed control data transfer 12. What is the role of MAR and MDR? The MAR (memory address register) is used to hold the address of the location to or from which data are to be transferred and the MDR(memory data register) contains the data to be written into or read out of the addressed location. 13. What are the various types of operations required for instructions? Data transfers between the main memory and the CPU registers Arithmetic and logic operation on data Program sequencing and control I/O transfers 14. What is the role of IR and PC? Instruction Register (IR) contains the instruction being executed. Its output is available to the control circuits, which generate the timing signals for controlling the processing circuits needed to execute the instructions. The Program Counter (PC) register keeps track of the execution of the program. It contains the memory address of the instruction currently being executed . During the execution of the current instruction, the contents of the PC are updated to correspond to the address of the next instructions to be executed. 15.What are the various units in the computer? Input unit Output unit Control unit

 Memory unit Arithmetic and logical unit 16.What is an I/O channel? An i/o channel is actually a special purpose processor, also called peripheral processor.The main processor initiates a transfer by passing the required information in the input output channel. the channel then takes over and controls the actual transfer of data. 17.What is a bus? A collection of wires that connects several devices is called a bus. 18.Define word length? Each group of n bits is referred to as a word of information and n is called the word length. 19.Explain the following the address instruction? Three-address instruction-it can be represented as add a,b,c Operands a,b are called source operand and c is called destination operand. Two-address instruction-it can be represented as Add a,b One address instruction-it can be represented as add a 20.Zero address instruction. It is also possible to use instruction where the location s of all operand are defined implicitly. This operand of the use of the method for storing the operand in which called push down stack. Such instructions are sometimes referred to us zero address instruction. 21.What is the straight-line sequencing? The CPU control circuitry automatically proceed to fetch and execute instruction, one at a time in the order of the increasing addresses. This is called straight line sequencing. 22.What is the role of PC? The CPU contains a register called the program counter, which holds the address of instruction to be executed next.. to begin the execution of the program the address of its First instruction must be placed into the PC. 23. Define Signal Signal - The binary information is represented in digital computers by physical quantities called signals. 24. Define Gates Gates The manipulation of binary information is done by logic circuits called gates. Gates are blocks of hardware that produce signals of binary 1 or 0 where input logic requirements are satisfied. 25. Flip flop Flip flop The storage elements employed in clocked sequential circuits are called flip flops. A flip flop is a binary cell capable of storing 1 bit of information. 26.State and explain the performance equation?

Suppose that the average number of basic steps needed to execute one machine instruction is S, where each basic step is completed in one clock cycle. If the clock cycle rate is R cycles per second, the program execution time is given by T = (N x S) / R This is often referred to as the basic performance equation. 27. Define CPI The term ClockCycles Per Instruction Which is the average number of clock cycles each instruction takes to execute, is often abbreviated as CPI. CPI= CPU clock cycles/Instruction count. 28. Define MIPS . MIPS:One alternative to time as the metric is MIPS(Million Instruction Per Second) MIPS=Instruction count/(Execution time x1000000). This MIPS measurement is also called Native MIPS todistinguish it from some alternative definitions of MIPS. 29.Define MIPS Rate: The rate at which the instructions are executed at a given time. 30.Define Throughput and Throughput rate. Throughput -The total amount of work done in a given time. Throughput rate-The rate at which the total amount of work done at a given time. 1.Specify the sequence of operation involved when an instruction is executed. a)Instruction Fetch b)Instruction Decode c)Operand Fetch d)Execute e) Write Back 2.Define parallel processing. Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer system. Instead of processing each instruction sequentially as in a conventional computer, a parallel processing system is able to perform concurrent data processing to achieve faster execution time. 3. Define sequential circuits. A sequential circuit is an interconnection of flip-flops and gates. The gates by themselves constitute a combinational circuit, but when included with the flip flops, the overall circuit is classified as a sequential circuit. 4.Define interface. The word interface refers to the boundary between two circuits or devices 5.Define processor clock. Processor clock: Processor circuits are controlled by a timing signal called processor clock, the clock defines regular time interval called clock cycle. 6. Define latency. The term memory latency is used to refer to the amount of time it takes to transfer a

word of data to or from the memory. The term latency is used to denote the time it takes to transfer the first word of data. This time is usually substantially longer than the time ne eded to transfer each subsequent word of a block. 7. Define bandwidth. Bandwidth is a product of the rate at which the data are transferred (and accessed) and the width of the data bus.. 8. Define hit rate. A successful access to data in a cache is called a hit. Number of hits stated as a fraction of all attempted accesses is called the hit rate. 9. Define miss rate. A miss rate is the number of misses stated as a fraction of attempted accesses. Extra time needed to bring the desired information into the cache is called the miss penalty. 10.Define Clock Rate: Clock rate, R=1/p cycles/sec(hz) Where p is length of one clock cycle 11.Define Throughput: The total amount of work done in a given time 12.Different types of buses. 1.Synchronous bus 2.Asynchronous bus 13. What is micro programming and micro programmed control unit? Microprogramming is a method of control unit design in which the control unit selection and sequencing information are stored in ROM and RAMs called control store or control memory. Micro programmed control unit is a general approach used for implementation of control unit. Here control signals are generated by a program similar to machine language programs 14. What is meant by hardwired control? It is the one that contains control units that use fixed logic circuits to interpret instructions and generate control signals from them. Here,the fixed logic circuit block includes combinational circuit that generates the required control outputs for decoding and encoding functions. 15. What is Register Renaming? If a temporary register assumes the role of the permanent register whose data it is holding and is given the same name is called as the Register Renaming. What is the function of commitment unit? When out-of-order execution is allowed, a s pecial control unit called as commitment unit is used to guarantee in-order commitment. It uses a queue called the reorder buffer to determine which instruction should be committed next. This is the function of commitment unit. 17. What is the neccesity of grouping signals? It is used to reduce the number of the bits in the microinstruction. It is used to overcome the draw back of assigning individual bits to each control signal results in long microinstructions, because the number of the required signals is usually large, moreover only a few bits are used in any given instruction. 18.List the techniques used for grouping of the control signals? a) Vertical organization b) Horizontal organization 19 List out Various branching technique used in micro program control unit? a) Bit-Oring b) Using Conditional Variable c) Wide Branch Addressing 20. Define the term Clock Rate. They are two possibilities for increasing the clock rate, R. First, improving the IC

technology makes logic circuits faster, which reduces the time needed to complete a basic step. This allows the clock period P to be reduce and the clock rate R to be increased Second, reducing the amount of processing done is one basic step makes it possible to reduce the clock period P. 21. What do you mean by out-of order execution? Is it Desirable? In a pipelined processor with several instructions is process concurrently it is Possible for instruction to finish out of sequence, one instruction finishes before Another which is issued earlier, as far as main computation is concerned no Hazards will happen but if an interrupts occurs it creates the problem. 22. Define Overflow Overflow -In the single precision, if the number requires a exponent greater then +127 or in a double precision, if the number requires an exponent form the overflow occurs. 23.Define Underflow Underflow-In a single precision ,if the number requires an exponent less than -26 or in a double precision, if the number requires an exponent less than -1022 to represent its normalized form the underflow occurs. 24. What are Condition Codes (CC)? Explain the use of them. Condition Codes are the list of possible conditions that can be tested during conditional instructions.CC is used to test the condition (<, =,>). Based on this result, Jump instructions move to specified loop.CC flags represent the value of processor that keeps the information about the results of various operations for use by conditional branches. 25. What is straight line sequencing? Process of fetching and executing an instruction; one at a time in order of increasing address with the help of information in program counter PIPELINING 1.Define pipelining. Pipelining is a technique of decomposing a sequential process into sub operations with each sub process being executed in a special dedicated segment that operates concurrently with all other segments. 2.Define parallel processing. Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer system. Instead of processing each instruction sequentially as in a conventional computer, a parallel processing system is able to perform concurrent data processing to achieve faster execution time. 3.Define instruction pipeline. The transfer of instructions through various stages of the CPU instruction cycle., including fetch opcode, decode opcode, compute operand addresses. Fetch operands, execute instructions and store results. This amounts to realizing most (or) all of the CPU in the form of multifunction pipeline called an instruction pipelining. 4. What are the steps required for a pipelinened processor to process the instruction? F Fetch: read the instruction from the memory D Decode: decode the instruction and fetch the source operand(s). E Execute: perform the operation specified by the instruction. W Write: store the result in the destination location 5. What are Hazards? A hazard is also called as hurdle .The situation that prevents the next instruction in the instruction stream from executing during its designated Clock cycle. Stall is introduced by hazard. (Ideal stage) 6. State different types of hazards that can occur in pipeline. The types of hazards that can occur in the pipelining were, 1. Data hazards.

2. Instruction hazards. 3. Structural hazards. 7. Define Data hazards A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in pipeline. As a result some operation has to be delayed, and the pipeline stalls. 8. Define Instruction hazards The pipeline may be stalled because of a delay in the availability of an instruction. For example, this may be a result of miss in cache, requiring the instruction to be fetched from the main memory. Such hazards are called as Instruction hazards or Control hazards. 9.Define Structural hazards? The structural hazards is the situation when two instructions require the use of a given hardware resource at the same time. The most common case in which this hazard may arise is access to memory. 10. What are the classification of data hazards? Classification of data hazard: A pair of instructions can produce data hazard by referring reading or writing the same memory location. Assume that i is executed before J. So, the hazards can be classified as, 1. RAW hazard 2. WAW hazard 3. WAR hazard 11.Define RAW hazard : ( read after write) Instruction j tries to read a source operand before instruction i writes it. 12. Define WAW hazard :( write after write) Instruction j tries to write a source operand before instruction i writes it. 13.Define WAR hazard :( write after read) Instruction j tries to write a source operand before instruction i reads it. 14. How data hazard can be prevented in pipelining? Data hazards in the instruction pipelining can prevented by the following techniques. a)Operand Forwarding b)Software Approach 15.How Compiler is used in Pipelining? A compiler translates a high level language program into a sequence of machine instructions. To reduce N, we need to have suitable machine instruction set and a compiler that makes good use of it. An optimizing compiler takes advantages of various features of the target processor to reduce the product N*S, which is the total number of clock cycles needed to execute a program. The number of cycles is dependent not only on the choice of instruction, but also on the order in which they appear in the program. The compiler may rearrange program instruction to achieve better performance of course, such changes must not affect of the result of the computation. 16. How addressing modes affect the instruction pipelining? Degradation of performance is an instruction pipeline may be due to address dependency where operand address cannot be calculated without available informatition needed by addressing mode for e.g. An instructions with register indirect mode cannot proceed to fetch the operand if the previous instructions is loading the address into the register. Hence operand access is delayed degrading the performance of pipeline. 17. What is locality of reference? Many instruction in localized area of the program are executed repeatedly during some time period and the remainder of the program is accessed relatively infrequently .this is referred as locality of reference. 18. What is the need for reduced instruction chip? Relatively few instruction types and addressing modes.

 Fixed and easily decoded instruction formats. Fast single-cycle instruction execution. Hardwired rather than micro programmed control 19. Define memory access time? The time that elapses between the initiation of an operation and completion of that operation ,for example ,the time between the READ and the MFC signals .This is Referred to as memory access time. 20. Define memory cycle time. The minimum time delay required between the initiations of two successive memory operations, for example, the time between two successive READ operations. 21.Define Static Memories. Memories that consist of circuits capable of retaining the state as long as power is applied are known as static memories. 22. List out Various branching technique used in micro program control unit? a) Bit-Oring b) Using Conditional Variable c) Wide Branch Addressing 23. How the interrupt is handled during exception? * CPU identifies source of interrupt * CPU obtains memory address of interrupt handles * pc and other CPU status information are saved * Pc is loaded with address of interrupt handler and handling program to handle it. 24. List out the methods used to improve system performance. The methods used to improve system performance are 1. Processor clock 2.Basic Performance Equation 3.Pipelining 4.Clock rate 5.Instruction set 6.Compiler 25. What is DMA? A special control unit may be provided to enable transfer a block of data directly between an external device and memory without contiguous intervention by the CPU. This approach is called DMA. UNIT-IV MEMORY SYSTEM 1.Give the classification of the Optical Media Optical media can be classified as CD-ROM Compact Disk Read Only Memory WORM Write Once Read Many Rewriteable - Erasable Multifunction WORM and Erasable 2. What is a Mini Disk? Minidisk for data (MD-Data) is the data version of the new rewriteable storage format developed by Sony Corporation for both business and entertainment as a convenient medium for carrying music , video and data. MD can be used in three formats to support all potential uses as follows: --A premastered optical disk --A recordable magneto-optical disk --A hybrid that is partially mastered and partially recordable 3. List some applications for WORM.

--Some of the application or WORM devices are --On-Line catalogs such as automobile partys dealer --Large Volume Distribution --Transaction logging such as stock trading company --Multimedia Archival 4. What are multifunctional drives A multifunctional drive is a single unit which is capable of reading and writing a variety of disk media. This type of drive provides the permanence of a read-only device as well as full flexibility of a rewriteable device along with the powerful intermediate write once capability 5. What are types of technology used in s multifunctional drive? Three types of technologies utilized for multifunctional drives are *Magneto Optical Disk for both rewriteable and WORM capability *Magneto- Optical disk for rewriteable and dye polymer disk for WORM capability *Phase change technology for both rewriteable and WORM capability 6.. What is Migration and Archiving? The process of moving an object from one level in the storage hierarchy to another level in that hierarchy is called migration. Migration of Objects to off-line media and removal of these objects from on-line media is called archiving. 7. How do we use a jukebox? A juke box is used for storing large volumes of multimedia information in one cost effective store . Jukebox based optical disk libraries can be networked so that multiple users can access the information. Opticla disk libraries serve as nearline storage for infrequently used ata. 8. List a few requirements imposed by advanced multimedia applications Some of the requirements imposed by multimedia application are *Support for windows based GUI, such as Microsoft Windows *Capability to run applications in Multitasking environments *Support for Multi User Applications *Network bases client server distributed applications 9. What is the use of High water marks in a cache? Cache design use a high-water mark and a low water mark to trigger cache management operations. When the cache storage fiklls up to the high water mark , the cache manager starts creating more space in cache storage. Space is created by discarding objects that have not been modified and writing back those object that have been modified. 10. What are the various cache usage in a LAN based system? In a LAN based system there can be as many as three stages of caches as follows 1. Disk Cache or System memory cache 2. Hard Disk cache for each object server 3. Shared network cache for all object servers 11. What are the multimedia applications which use caches? Some Multimedia application areas where cache is extensively used are *Multimedia Entertainment *Education *Office Systems *Audio and video Mail *Computer Architecture - Set 6 12. Explain virtual memory technique. Techniques that automatically move program and data blocks into the physical memory when they are required for execution are called virtual memory technique 13. What are virtual and logical addresses? The binary addresses that the processor issues for either instruction or data are called virtual or logical addresses. 14. Define translation buffer.

Most commercial virtual memory systems incorporate a mechanism that can avoid the bulk of the main memory access called for by the virtual to physical addresses translation buffer. This may be done with a cache memory called a translation buffer. 15. What is branch delay slot? The location containing an instruction that may be fetched and then discarded because of the branch is called branch delay slot. 16. What is optical memory? Optical or light based techniques for data storage, such memories usually employ optical disk which resemble magnetic disk in that they store binary information in concentric tracks on an electromechanically rotated disks. The information is read as or written optically, however with a laser replacing the read write arm of a magnetic disk drive. Optical memory offer high storage capacities but their access rate is are generally less than those of magnetic disk. 17. What are static and dynamic memories? Static memory are memories which require periodic no refreshing. Dynamic memories are memories, which require periodic refreshing. 18. What are the components of memory management unit? A facility for dynamic storage relocation that maps logical memory references into physical memory addresses. A provision for sharing common programs stored in memory by different users . 19. What is the role of MAR and MDR? The MAR (memory address register) is used to hold the address of the location to or from which data are to be transferred and the MDR(memory data register) contains the data to be written into or read out of the addressed location. 20. Distinguish Between Static RAM and Dynamic RAM? Static RAM are fast, but they come at high cost because their cells require several transistors. Less expensive RAM can be implemented if simpler cells are used. However such cells do not retain their state indefinitely; Hence they are called Dynamic RAM. 21. Distiguish between asynchronies DRAM and synchronous RAM. The specialized memory controller circuit provides the necessary control signals, RAS And CAS ,that govern the timing. The processor must take into account the delay in the response of the memory. Such memories are referred to as asynchronous DRAMS.The DRAM whose operations is directly synchronized with a clock signal. Such Memories are known as synchronous DRAM. 22. What do you mean associative mapping technique? The tag of an address received from the CPU is compared to the tag bits of each block of the cache to see if the desired block is present. This is called associative mapping technique. 23. What is SCSI? Small computer system interface can be used for all kinds of devices including RAID storage subsystems and optical disks for large- volume storage applications. 24. What are the two types of latencies associated with storage? The latency associated with storage is divided into 2 categories 1. Seek Latencies which can be classified into Overlapped seek,Mid transfer seek and Elevator seek 2. Rotational Latencies which can be reduced either by Zero latency read or Write and Interleave factor. 25. What are the data management activities involved in a storage? a. Command queuing : allows execution of multiple sequential commands with system CPU intervention. It helps in minimizing head switching and disk rotational latency b. Scatter gather : Scatter is a process whereby data is set for best fit in available block of memory or disk. Gather reassembles data into contiguous blocks on disk or in memory 27. What do you mean by Disk Spanning? Disk spanning is a method of attaching drives to a single host uadapter. All drives

appear as a single contiguous logical unit. Data is written to the first drive first and when the drive is full, the controller switches to the second drive, then the second drive writes until its full. 28. List some objectives for using RAID Systems -RAID systems are used to meet the following objectives -Hot backup of disk systems -Large volume storage at lower cost -Higher performance at lower cost -Ease of data recovery -High MTBF 29. What are the different levels RAID? There are six discrete levels of RIAD functionality. They are -Level 0 Disk Striping -Level 1 Disk Mirroring -Level 2 Bit Interleaving of Data -Level 3 Bit Interleaving with dedicated parity drives - Level 4 Sector interleaving of data with dedicated parity drive -Level 5 Block interleaving of data. 30.Two Types of storage devices. 1.Primary Memory 2.Secondary Memory UNIT-V I/O ORGANIZATION 1.Explain very briefly about ESDI Hard Drive ESDI stands for enhanced small device interface was developed by a consortium of several manufacturers. ESDI converts the data into serial bit streams and uses the RLL encoding scheme to pack more bits per sector. ESDI drives store a defect map containing the locations of bad and defective sectors on the drive. 2. Explain in brief about IDE Integrated device electronics contains an integrated controller with the drive as a single unit. Interface is a simple 16-bit parallel data interface and requires the data to be written and does not need to be told where and how to write the data on the disk. .IDE Interface supports 2 drives one drive has to be configured as the master and the second as the slave. 3. What is SCSI? Small computer system interface can be used for all kinds of devices including RAID storage subsystems and optical disks for large- volume storage applications. 4. Define the term RELIABILITY Means feature that help to avoid and detect such faults. A realible system does not silently continue and delivery result that include interrected and corrupted data, instead it corrects the corruption when possible or else stops 5.Define the term AVAILABLITY: Means features that follow the systerm to stay operational even offen faults do occur. A highly available systerm could dis able do the main functioning portion and continue operating at the reduced capacity 6. How the interrupt is handled during exception? * cpu identifies source of interrupt * cpu obtains memory address of interrupt handles * pc and other cpu status information are saved * Pc is loaded with address of interrupt handler and handling program to handle it 7. What is IO mapped input output? A memory reference instruction activated the READ M (or)WRITE M control line and

does not affect the IO device. Separate IO instruction are required to activate the READ IO and WRITE IO lines ,which cause a word to be transferred between the address aio port and the CPU. The memory and IO address space are kept separate. 8.Specify the three types of the DMA transfer techniques? --Single transfer mode(cyclestealing mode) --Block Transfer Mode(Brust Mode) --Demand Transfer Mode --Cascade Mode 9. What is an interrupt? An interrupt is an event that causes the execution of one program to be suspended and another program to be executed. 10.What are the uses of interrupts? *Recovery from errors *Debugging *Communication between programs *Use of interrupts in operating system 11.Define vectored interrupts. In order to reduce the overhead involved in the polling process, a device requesting an interrupt may identify itself directly to the CPU. Then, the CPU can immediately start executing the corresponding interrupt-service routine. The term vectored interrupts refers to all interrupt handling schemes base on this approach. 12. Name any three of the standard I/O interface. *SCSI (small computer system interface),bus standards *Back plane bus standards *IEEE 796 bus (multibus signals) *NUBUS *IEEE 488 bus standard 13. What is an I/O channel? An i/o channel is actually a special purpose processor, also called peripheral processor. The main processor initiates a transfer by passing the required information in the input output channel. the channel then takes over and controls the actual transfer of data. 14.What is a bus? A collection of wires that connects several devices is called a bus. 15.Define word length? Each group of n bits is referred to as a word of information and n is called the word length. 16. Why program controlled I/O is unsuitable for high-speed data transfer? In program controlled i/o considerable overhead is incurred.. because several program instruction have to be executed for each data word transferred between the external devices and MM.Many high speed peripheral; devices have a synchronous modes of operation.that is data transfer are controlled by a clock of fixed frequency, independent of the cpu. 17.what is the function of i/o interface? The function is to coordinate the transfer of data between the cpu and external devices. 18.what is NUBUS? A NUBUS is a processor independent, synchronous bus standard intended for use in 32 bit micro processor system. It defines a backplane into which upto 16 devices may be plugged each in the form of circuit board of standard dimensions. 19. Name some of the IO devices. *Video terminals *Video displays *Alphanumeric displays *Graphics displays

* Flat panel displays *Printers *Plotters 20. What are the steps taken when an interrupt occurs? *Source of the interrupt *The memory address of the required ISP * The program counter & cpu information saved in subroutine *Transfer control back to the interrupted program 21.Define interface. The word interface refers to the boundary between two circuits or devices 22.What is programmed I/O? Data transfer to and from peripherals may be handled using this mode. Programmed I/O operations are the result of I/O instructions written in the computer program. 23.Types of buses. -Synchronous bus -Asynchronous bus 24.Define Synchronous bus. - Synchronous bus on other hand contains synchronous clock that is used to validate each and every signal. - Synchronous buses are affected noise only when clock signal occurs. - Synchronous bus designers must control with meta stability when attempting different clock signal Frequencies - Synchronous bus of meta stability arises in any flip flop. when time will be violated. 25. Define Asynchronous bus. - Asynchronous buses can mistake noise pulses at any time for valid handshake signal. - Asynchronous bus designer must deal with events that like synchronously. - It must contend with meta stability when events that drive bus transaction. -When flip flop experiences effects can occur in downstream circurity unless proper design technique which are used

UNIT I 1. What are the basic functional units of a computer? Input, memory, arithmetic and logic unit, output and control units are the basic functional units of a computer 2. Define Response time and Throughput. Response time is the time between the start and the completion of the event. Also referred to as execution time or latency. Throughput is the total amount of work done in a given amount of time. 3. Define a program? A list of instructions that performs a task is called as a program 4.Define data.

Data are numbers and encoded characters that are used as operands by the instructions. The term data, however is often used to mean any digital information. 5.Give some examples for input devices. Keyboard,joysticks,trackballs and mousse are some examples for input devices.

6.Compute the effective CPI for the processor, for the following instruction mix: Instruction type ALU operation Loads Stores Branch taken Branch untaken Clock cycle count Frequency 1 40 3 20 2 10 3 20 2 10

Adding a branch prediction unit makes an enhancement to the processor. This decreases the number of cycle taken to execute a branch from 3 to 2. What is the improvement in performance? Speed up= execution time old / execution time
new

execution time old or CPU time= I.C. * Clk Cycles * Cycle time execution time old =[40*1+20*3+10*2+20*2+10*2] Cycles * cycles time. The enhancement decreases the number of cycles taken for branch instruction from 3 to 2. execution time new =[40*1+20*3+10*2+20*2+10*2] Cycles * cycles time = 180 Cycles * cycles time \\ Speed up = 200 Cycles * cycles time / 180 Cycles * cycles time = 1.1

7. Suppose that we are considering an enhancement to the processor of a server system used for web serving. The new CPU is 10 times faster on computation in the web serving application than the original processor. Assuming that the original CPU is busy with computation 40% of the time and is waiting for I/O 60% of the time. What is the overall speedup gained by incorporating the enhancement? Fraction enhanced = 0.4 Speedup enhanced = 10 Speedup overall = 1/(0.6+0.4/10) =1/0.64 = 1.56 8. Explain the different types of locality.

Temporal locality, states that recently accessed items are likely to be accessed in the near future.Spatial locality, says that items whose addresses are near one another tend to be referenced close together in time. 9. What is the function of memory unit? how will you classify it? The function of the memory unit is to store programs and data, there are two classes of storage, called primary and secondary.

10. Specify the CPU performance equation. CPU time = Instruction Count x Clock cycle Time x cycles per instruction 11. Explain the hybrid approach for encoding an instruction set? The hybrid approach reduces the variability in size and work of the variable architecture but provide multiple instruction lengths to reduce code size. 12. What are the registers used for MIPS processors. MIPS has 34, 64-bit general purpose registers (GPRs), named R0,R1R31. GPRs are sometimes called as integer registers. There are also a set of 32 floating point registers (FPRs), named F0,F1.F31, which can hold 32 single precision values and 32 double precision values. 13. Explain the concept behind pipelining. Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It takes advantage of parallelism that exists among actions needed to execute an instruction. 14. Write about pipe stages and processor cycle. Different steps in an instruction are completed in different parts of different instruction is parallel. Each of these steps is called a pipe stage or pipe segment. The time required between moving an instruction one step down the pipeline is called processor cycle. 15. Explain pipeline hazard and mention the different hazards in pipeline. Hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the overall performance from the ideal speedup gained by pipelining. The three classes of hazards are, Structural hazards. Data hazards. Control hazards

16. Explain the concept of forwarding. Forwarding can be generalized to include passing a result directly to the functional unit that fetches it. The result is forwarded from the pipeline register corresponding to the output of one unit to the input of the same unit. 17. Mention the different schemes to reduce pipeline branch penalties. a. Freeze or flush the pipeline b. Treat every branch as not taken c. Treat every branch as taken d. Delayed branch 18. what are timing signals? Timing signals are signals that determines when a given action is to take place.the actual timing signals that govern the transfers are generated by control circuits. 19.how will you compute the SPEC rating? SPEC stands for system performance evaluation corporation Running time on the reference computer SPEC rating= _________________________________ Running time on the computer under test 20. When do data hazards arise? Data hazards arise when an instruction depends on the results of a previous instruction in a way that is expressed by the overlapping of instructions in the pipeline. 1. what are the two approaches to reduce delay in address?

To use fastest possible electronic technology in implementing the ripple-carry logic design or variations of it. To use an augmented logic gate network structure

2. What is Instruction Level Parallelism? Pipelining is used to overlap the execution of instructions and improve performance. This potential overlap among instructions is called instruction level parallelism (ILP) since the instruction can be evaluated in parallel. 3. what is the purpose of fast adder? A fast adder circuit must speedup the generation of the carry signals.

4. What is the limitation of the simple pipelining technique? These technique uses in-order instruction issue and execution. Instructions are issued in program order, and if an instruction is stalled in the pipeline, no later instructions can proceed. 5. Briefly explain the idea behind using reservation station? Reservation station fetches and buffers an operand as soon as available, eliminating the need to get the operand from a register. 6. How does propagate function mean? The propagate function means that an input carry will produce an output carry when either xi is 1 or yi is 1 7.what is booths algorithm? Booths algorithm is a technique for generating a 2 nbit product. it treats both positive and negative 2s complement n bit operands uniformly.. 8. what is bit pair recoding? Bit pair recoding of multipliers is a technique that halves the maximum number of summands ,it is derived directly from booth algorithm.on a different pipeline. 9.Give the expression for generate and propagate functions for stage i. Generate function Gi=XiYi Propagate function Pi=Xi+Yi multiplication?

10. What are the techniques used to reduce the time needed to perform Bit pair recoding of multiplier Carry save addition of summands Look ahead addition.

11. What are branch-target buffers? To reduce the branch penalty we need to know from what address to fetch by end of IF (instruction fetch). A branch prediction cache that stores the predicted address for the next instruction after a branch is called a branch-target buffer or branch target cache. 12. Briefly explain the goal of multiple-issue processor? The goal of multiple issue processors is to allow multiple instructions to issue in a clock cycle. They come in two flavors: superscalar processors and VLIW processors. 13. What is speculation? Speculation allows execution of instruction before control dependences are resolved. 14. what is chopping?

Chopping is a simple way to truncate or remove the guard bits and make no changes in the retained bits. 15. What are super scalar processors? Superscalar processors issue varying number of instructions per clock and are either statically scheduled or dynamically scheduled. 16. what is the process involved in von-Neumann rounding? If the bits to be removed are all 0s they are simply dropped, with no changes to retained bits.however,if any of the bits to be removed are , the least significant bit of retained bit is set to 1. 17. Define a normalized number A normalized number is one in which the most significant digit of the significant is zero. 18.Give the range of negative numbers in floating point format. the range of negative numbers in floating point format (2-2-23) x 2 128 and -2-127

19. Give the range of positive numbers in floating point format. the range of positive numbers in floating point format 2-127 and (2-2-23) x 2128

20.List the conditions produced during a floating point operation. during a floating point operation, the conditions produced are

Exponent overflow Exponent underflow Significant underflow Significant overflow

UNIT III

1. What is loop unrolling? A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is loop unrolling. Unrolling simply replicates the loop body multiple times, adjusting the loop termination code. 2. When static branch predictors are used? They are used in processors where the expectation is that the branch behavior is highly predictable at compile time. Static predictors are also used to assists dynamic predictor. 3. Mention the different methods to predict branch behavior?

Predict the branch as taken Predict on basis of branch direction (either forward or backward) Predict using profile information collected from earlier runs. 4. Explain the VLIW approach? They uses multiple, independent functional units. Rather than attempting to issue multiple, independent instructions to the units, a VLIW packages the multiple operations into one very long instruction. 5. Mention the techniques to compact the code size in instructions? Using encoding techniques Compress the instruction in main memory and expand them when they are read into the cache or are decoded. 6. Mention the advantage of using multiple issue processor? They are less expensive. They have cache based memory system. And More parallelism. 7. What are loop carried dependence? They focuses on determining whether data accesses in later iterations are dependent on data values produced in earlier iterations; such a dependence is called loop carried dependence. e.g for(i=1000;i>0;i=i-1) x[i]=x[i]+s; 8. Mention the tasks involved in finding dependences in instructions? Good scheduling of code. Determining which loops might contain parallelism Eliminating name dependence 9. Use the G.C.D test to determine whether dependence exists in the following loop: for(i=1;i<=100;i=i+1) X[2*i+3]=X[2*i]*5.0; Solution: a=2,b=3,c=2,d=0 GCD(a,c)=2 and d-b=-3 Since 2 does not divide -3, no dependence is possible. 10. What is meant by pipelining? Software pipelining is a technique for reorganizing loops such that each iteration in the software pipelined code is made from instruction chosen from different iterations of the original loop.

11. What is global code scheduling? Global code scheduling aims o compact code fragment with internal control structure into the shortest possible sequence that preserves the data and control dependence. Finding a shortest possible sequence is finding the shortest sequence for the critical path. 12. What is trace? Trace selection tries to find a likely sequence of basic blocks whose operations will be put together into a smaller number of instructions; this sequence is called trace. 13. Mention the steps followed in trace scheduling? Trace selection Trace compaction

14. What is superblock? Superblocks are formed by a process similar to that used for traces, but are a form of extended basic block, which are restricted to a single entry point but allow multiple exits. 15. Mention the advantages of predicated instructions? Remove control dependence Maintain data flow enforced by branch Reduce overhead of global code scheduling 16. Mention the limitations of predicated instructions? They are useful only when the predicate can be evaluated early. Predicated instructions may have speed penalty. 17. What is poison bit? Poison bits are a set of status bits that are attached to the result registers written by the speculated instruction when the instruction causes exceptions. The poison bits cause a fault hen a normal instruction attempts to use the register. 18. What are the disadvantages of supporting speculation in hardware? Complexity Additional hardware resources required 19. Mention the methods for preserving exception behavior? Ignore Exception Instructions that never raise exceptions are used Using poison bits Using hardware buffers

20. What is an instruction group? It is a sequence of consecutive instructions with no register data dependence among them. All the instructions in the group could be executed in parallel. An instruction group can be arbitrarily long.

1. What is cache miss and cache hit? When the CPU finds a requested data item in the cache, it is called cache miss. When the CPU does not find that data item it needs in the cache, a cache miss occurs. 2. What is write through and write back cache? Write through- the information is written to both the block in the cache and to the block in the lower level memory.write back- The information is written only to the block in the cahce. The modified cache block is written to main memory only when it is replaced.

3. What is miss rate and miss penalty? Miss rate is the fraction of cache access that result in a miss. Miss penalty depends on the number of misses and clock per miss. 4. Give the equation for average memory access time? Average memory access time= Hit time + Miss rate x Miss penalty 5. What is striping? Spreading multiple data over multiple disks is called striping, which automatically forces accesses to several disks. 6. Mention the problems with disk arrays? When devices increases, dependability increases Disk arrays become unusable after a single failure 7. What is hot spare? Hot spares are extra disks that are not used in normal operation. When failure occurs, an idle hot spare is pressed into service. Thus, hot spares reduce the MTTR. 8. What is mirroring? Disks in the configuration are mirrored or copied to another disk. Withthis arrangement data on the failed disks can be replaced by reading it from the other mirrored disks. 9. Mention the drawbacks with mirroring? Writing onto the disk is slower Since the disks are not synchronized seek time will be different Imposes 50% space penalty hence expensive. 10. Mention the factors that measure I/O performance measures?

Diversity Capacity Response time Throughput Interference of I/o with CPU execution

11. What is transaction time? The sum of entry time, response time and think time is called transaction time. 12. State littles law? Littles law relates the average number of tasks in the system. Average arrival rate of new asks. Average time to perform a task.

13. Give the equation for mean number of tasks in the system? Mean number of arrival in the system = Arrival rate x Mean response time. 14. What is server utilization? Mean number of tasks being serviced divided by service rate Server utilization = Arrival Rate/Server Rate The value should be between 0 and 1 otherwise there would be more tasks arriving than could be serviced. 15. What are the steps to design an I/O system? Nave cost-performance design and evaluation Availability of nave design Response time Realistic cost-performance, design and evaluation Realistic design for availability and its evaluation. 16. Briefly discuss about classification of buses? I/O buses - These buses are lengthy ad have any types of devices connected to it. CPU memory buses They are short and generally of high speed. 17. Explain about bus transactions? Read transaction Transfer data from memory

Write transaction Writes data to memory 18. What is the bus master? Bus masters are devices that can initiate the read or write transaction. E.g CPU is always a bus master. The bus cn have many masters when there are multiple CPUs and when the Input devices can initiate bus transaction. 19. Mention the advantage of using bus master? It offers higher bandwidth by using packets, as opposed to holding the bus for full transaction.

20. What is spilt transaction? The idea behind this is to split the bus into request and replies, so that the bus can be used in the time between request and the reply

1. What are multiprocessors? Mention the categories of multiprocessors? Multiprocessors are used to increase performance and improve availability. The different categories are SISD, SIMD, MISD, MIMD 2. What are threads? These are multiple processors executing a single program and sharing the code and most of their address space. When multiple processors share code and data in the way, they are often called threads. 3. What is cache coherence problem? Two different processors have two different values for the same location. 4. What are the protocols to maintain coherence? Directory based protocol Snooping Protocol

5. What are the ways to maintain coherence using snooping protocol? Write Invalidate protocol Write update or write broadcast protocol

6. What is write invalidate and write update?

Write invalidate provide exclusive access to caches. This exclusive caches ensure that no other readable or writeable copies of an item exists when the write occurs. Write update updates all cached copies of a data item when that item is written. 7. What are the disadvantages of using symmetric shared memory? Compiler mechanisms are very limited Larger latency for remote memory access Fetching multiple words in a single cache block will increase the cost.

8. Mention the information in the directory? It keeps the state of each block that are cached. It keeps track of which caches have copies of the block.

9. What the operations that a directory based protocol handle? Handling read miss Handling a write to a shares clean cache block

10. What are the states of cache block? Shared, Uncached, Exclusive

11. What are the uses of having a bit vector? When a block is shared, the bit vector indicates whether the processor has the copy of the block. When block is in exclusive state, bit vector keep track of the owner of the block. 12. When do we say that a cache block is exclusive? When exactly one processor has the copy of the cached block, and it has written the block. The processor is called the owner of the block. 13. Explain the types of messages that can be send between the processors and directories? Local node Node where the requests originates Home Node Node where memory location and directory entry of theaddress resides. Remote Node - The copy of the block in the third node called remote node 14. What is consistency? Consistency says in what order must a processor observe the data writes of another processor.

15. Mention the models that are used for consistency? Sequential consistency Relaxed consistency model

16. What is sequential consistency? It requires that the result of any execution be the same, as if the memory accesses executed by each processor were kept in order and the accesses among different processors were interleaved. 17. What is relaxed consistency model? Relaxed consistency model allows reads and writes to be executed out of order. The three sets of ordering are: W-> R ordering W->W ordering R->W and R-> R ordering.

18. What is multi threading? Multithreading allows multiple threads to share the functional units of the single processor in an overlapping fashion. 19. What is fine grained multithreading? It switches between threads on each instruction, causing the execution of multiple threads to be interleaved. 20. What is coarse grained multithreading? It switches threads only on costly stalls. Thus it is much less likely to slow down the execution of an individual thread.

PART-B 1.Explain about memory technology. and also write short notes on interleaved memory. 2.i) Describe the cache with its feature, organization and operation. ii) Discuss in detail about associative memories. 3. Discuss in detail the CPU organization with its additional features 4.Discuss in detail the principles of designing pipelined processors. 5.Discuss the principles of vector processing. 6.describe about the performance of the pipeline.

7.Explain briefly about CPU control unit. 8.what is meant by ALU? Explain it with a neat sketch. 9.i) write notes on methods of hardwired control. ii) Discuss the basic concepts of a micro-programmed control. 10.design a micro programmed control unit for a multiplier (using shift-add operations). Give the complete design. 11.Discuss the various techniques used to handle control hazards in a pipelined processor. 12.what is data hazard? Explain in detail. 13.what is instruction hazard? Explain in detail. 14.discuss the influence on instruction set. 15.how is parallelism achieved in uniprocessor machines? Discuss. 1.i) what is meant by the dynamic data flow computer and explain it? ii) List out the differences between RISC and CISC processors. 2.Explain in detail about standard I/O interfaces. 3.Give the advantage of fault tolerant system. 4.Explain the various ways to measure I/O performance? Throughput versus response time Little queuing theory 5.i) what is meant by interrupts and explain its types? ii) Discuss in briefly about IOP. 6.Explain the static and dynamic dataflow design. 7.Explain detail about the direct Access memory. 8.Explain the techniques that are available to access the I/O devices. 9.what are interface circuits? Explain in detail. 1.Explain in detail about static pipeline and dynamic pipeline. 2.i) Explain in detail the instruction pipelining.(8)

ii) Describe with neat sketch the parallel computer structures. 3. Explain the different technique to reduce miss rate? Larger block size Larger caches Higher associativity Way prediction and pseudoassociative caches Compiler optimization 4.Discuss briefly the serial access memories and random access memories. 5.i) discuss about programmed IO. ii) Explain structure versus performance of a cache design. 6. Explain the different technique to reduce cache miss penalty? 7. Discuss how main memory is organized to improve performance? 8.Explain in detail the high-speed memories and virtual memory. 9.i) Describe the features of multiport memory and interleaved memory. ii) Explain about segmentation and paging. 10.discuss the different mapping techniques used in cache memories. 1.Explain in Detail about the different functional units of a computer. 2.Explain the software performance of a computer. 3.what are the different types of instructions and also explain the instruction sequence. 4. Explain about the memory locations and addresses, memory operations. 5.Define addressing modes. And explain the different types of addressing modes.

6.Write short notes on generation of computer and give its evaluation of performance 7. Write short notes on the basics of computer architecture? 8.i) Describe about stock organization. ii) Discuss in detail about some addressing modes. 9.discuss in detail the instruction formats and its types.

10.i) describe stored program organization in detail. ii) What are the instruction formats available and explain each? 11.Explain briefly about the stack organization. 1. write short notes on fixed point and floating-point numbers of data representation? Explain the instruction and its types with examples? 2.Briefly discuss about fixed-point arithmetic and floating point. 3.Explain with a diagram, the design of a fast multiplier using carry save adder circuit. 4.show how a 64 bit adder can be constructed using 4-bit adder modules and ahead generator modules. what is the delay in generating C64 and S63 here? 5.Discuss any one binary division algorithm and simulate the same for 25/15 6.give the organization of a floating-point adder / subtractor unit and explain its operation. 7.what is booths Algorithm? Explain in detail. 8.Expalin with a diagram, the design of fast adder. 9.Expalin in detail, the arithmetic operations performed on floating point numbers. 10.what are two types of integer division techniques? Explain with an example. 4-bit carry look

S2253 COMPUTER ORGANIZATION AND ARCHITECTURE question bank

UNIT I BASIC STRUCTURE OF COMPUTERS Part A( 2Marks) 1. What is meant by the stored program concept? 2. What are the basic functional units of a computer? 3. What is the use of buffer register? 4. Define memory access time. 5. Write the differences between RISC and CISC. 6. What is meant by MAR and MDR? 7. What is an interrupt? 8. Why data bus is bidirectional in most microprocessors? 9. What do you mean by multiprogramming or multitasking? 10. Give the basic performance equation. 11. What are the limitations of assembly language? 12. What are the two techniques used to increase the clock rate R? 13. What are big-endian and little-endian representations?

14. What is the information conveyed by addressing modes? 15. What are the different types of addressing modes available? 16. What is indirect addressing mode? 17. What is indexed addressing mode? 18. Define auto increment mode of addressing? 19. Define auto decrement mode of addressing? 20. What are condition code flags? 21. What is the use of assembler directive? 22. What is meant by straight line sequencing? 23. What is stack? 24. Which data structure is best supported using indirect addressing mode? 25. What are the differences between Stack and Queue? 26. What is byte addressable memory? 27. What is big endian and Little endian format? 28. Define clock rate? 29. What is the function of ALU? 30. Draw the full adder circuit using two half adders and give the truth table. 31. Why floating point number is more difficult to represent and process than integer? 32. What are the two approaches used to reduce delay in adders? 33. What is a carry look-ahead adder? 34. Discuss the principle behind the Booths algorithm? 35. How can we speed up the multiplication process? 36. What is bit pair recoding? Give an example. 37. What are the two methods of achieving the 2s complement? 38. What is the advantage of using Booth algorithm? 39. Write the algorithm for restoring division. 40. Write the algorithm for non restoring division. 41. Define IEEE floating point single and double precision standard. 42. When can you say that a number is normalized? 43. Explain about the special values in floating point numbers. 44. Write the Add/subtract rule for floating point numbers. 45. Write the multiply rule for floating point numbers. 46. What is the purpose of guard bits? 47. What are the ways to truncate the guard bits? 48. Define carry save addition (CSA) process. 49. What are generated and propagate function? 50. What is excess-127 format? 51. What is a ripple carry adder? 52. Draw the structure of 4-bit MSI ALU circuit block. 53. What are the various ways of representing signed integers in the system? 54. Give the booths recoding and bit pair recoding of the number 1000011100100101. 55. When performing signed division, the sign of the remainder should be the same as the sign of
the dividend. Why?

Part B 1. Explain the basic functional units of a simple computer. (8) 2. Explain the basic I/O operations of modern processors. (8) 3. Explain various addressing modes found in modern processors (16) 4. Explain various assembler directives used in assembly language program (8) 5. What are stack and queues? Explain its use and give its differences (10) 6. What are the various types of ISAs possible? Discuss. (8)

7. Discuss the various issues to be considered while designing the ISA of a processor.(8) 8. Write the difference between CISC and RISC. 9. Discuss the principle of operation of carry-look ahead adders. (8) 10. Discuss the non-restoring division algorithm. Simulate the same for 23/5. (8) 11. Multiply the following pair of signed 2s complements numbers using bit pair recoded multiplier: Multiplicand = 110011 Multiplier = 101100. (8) 12. With a neat sketch, Explain in detail about logic design for fast adders. (16) 13. Describe how the floating-point numbers are represented and used in digital arithmetic operations. Give an example. (16) 14. Explain the representations of floating point numbers in detail. (6) 15. Design a multiplier that multiplies two 4-bit numbers. (6) 16. Give the block diagram of the hardware implementation of addition and subtraction of signed number and explain its operations. (10) 17. Explain the working of floating point adder and subtractor. (10)

UNIT II BASIC PROCESSING UNIT Part A( 2Marks) 1. What are the limitations of super scalar device? 2. Define pipeline speedup. 3. What is a processor clock? 4. Write down the control sequence for Move (R1), R2. 5. What is the function of a TLB (translation look-aside buffer)? 6. What is the WMFC step needed when reading from or writing to the main memory? 7. Define register file. 8. Name the methods for generating the control signals. 9. Define hardwired control. 10. Discuss the principle of operation of a micro programmed control. 11. Differentiate micro programmed control from hardwired control. 12. Define parallelism in microinstruction. 13. What are the types of microinstructions available? 14. Differentiate horizontal microinstruction from vertical microinstruction. 15. What is MFC? 16. What is the principle of Nanoprogramming? 17. Write the various actions required to fetch a word from memory. 18. Write the control sequence for execution of the instruction Add(R3), R1. 19. Write the control sequence for an unconditional branch instruction. Part B 1. Give the organization of typical hardwired control unit and explain the functions performed by the various blocks. (16) 2. With a neat block diagram, explain in detail about micro programmed control unit and explain its operations. (16) 3. Explain the execution of an instruction with diagram. (8) 4. Explain the multiple bus organization in detail. (8) 5. Explain the instruction cycle highlighting the sub-cycles and sequence of steps to be followed. (8) 6. Consider a processor is having single bus organization of the datapath inside a processor. Write the sequence of control steps required for each of the following instructions: a) Add the (immediate) number NUM to register R1 b) Add the contents of memory location NUM to register R1. c) Add the contents of the memory location whose address is at memory location NUM to register R1.

UNIT 3 PIPELINING PART A 1. What is pipelining? 2. What are the major characteristics of a pipeline? 3. What is a pipeline hazard? 4. What is data hazard? 5. What is instruction or control hazard? 6. Define structural hazards. 7. What is side effect? 8. What do you mean by branch penalty? 9. What is branch folding? 10. What do you mean by delayed branching? 11. What are the two types of branch prediction techniques available? 12. What is the ideal speedup expected in a pipelined architecture with n stages. Justify your answer. 13. Draw the structure of two stage instruction pipeline. 14. What is RAW hazard? 15. What is WAW hazard? 16. What is the use of branch prediction technique? 17. What is the use of pipelining? 18. What are the characteristics of the MIPS Instruction Set Architecture (ISA) that facilitate
pipelined execution?

PART B 1. Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome/minimize these hazards. (16) 2. Explain in detail about instruction execution characteristics. (16) 3. Explain the function of a six segment pipeline showing the time it takes to process eight tasks. (10) 4. Highlight the solutions of instruction hazards. (6) 5. Define the terms "structural hazard", "control hazard", and "data hazard" in the context of pipelines. Which of these hazards is addressed by a hardware branch predictor (which guesses whether a branch will be taken or not)? For one of the other hazards, suggest a way, either in software or hardware, the effect of that hazard could be reduced. 6. The five stages of the simple MIPS pipeline we covered in class are: instruction fetch, instruction decode and register read, execute or calculate address, memory access, and register write. Describe the purpose of each of these stages. 7. Define the terms "structural hazard", "control hazard", and "data hazard" in the context of pipelines. Which of these hazards is addressed by a hardware branch predictor (which guesses whether a branch will be taken or not)? For one of the other hazards, suggest a way, either in software or hardware, the effect of that hazard could be reduced.

8. Define the terms "spatial locality" and "temporal locality", and explain how caches are used to exploit them for a performance benefit. Be specific in the different ways that caches exploit these two phenomena.

UNIT IV MEMORY SYSTEM Part A (2Marks) 1. Define Memory Access time for a computer system with two levels of caches. 2. How to construct an 8M * 32 memory using 512 K * 8 memory chips. 3. Write two advantages of MOS device. 4. List the factors that determine the storage device performance. 5. What will be the width of address and data buses for a 512K * 8 memory chip? 6. Define memory cycle time. 7. What is RAM? 8. What is cache memory? 9. Explain virtual memory. 10. List the various semiconductors RAMs? 11. What do you mean by static memories? 12. Define DRAMs. 13. Define DDR SDRAM. 14. What is ROM? 15. What is the mapping procedures adopted in the organizatio n of a cache Memory? 16. Give the format for main memory address using direct mapping function for 4096 blocks in main memory and 128 blocks in cache with 16 blocks per cache. 17. Give the format for main memory address using associative mapping function for 4096 blocks in main memory and 128 blocks in cache with 16 blocks per cache. 18. Give the format for main memory address using set associative mapping function for 4096 blocks in main memory and 128 blocks in cache with 16 blocks per cache. 19. Define Hit and Miss rate? 20. What are the enhancements used in the memory management? 21. What is meant by memory management unit? 22. What is meant by memory interleaving? 23. What do you mean by seek time? 24. What is disk controller? 25. What is RAID? 26. Define data stripping? 27. How the data is organized in the disk? 28. Define latency time. 29. What is the significance of TLB?

Part B 1. Discuss the various mapping techniques used in cache memories. (8) 2. A computer system has a main memory consisting of 16 M words. It also has a 32Kword cache organized in the block-set-associative manner, with 4 blocks per set and 128 words per block. Calculate a) the number of bits in each of the TAG, SET and WORD fields of the main memory address format.

How will the main b) memory address look like for a fully associative mapped cache? (8) 3. Explain the concept of virtual memory with any one virtual memory management technique. (8) 4. Give the basic cell of an associative memory and explain its operation. Show how associative memories can be constructed using this basic cell. (8) 5. Give the structure of semiconductor RAM memories. Explain the read and write operations in detail. (16) 6. Explain the organization of magnetic disks in detail. (8) 7. A digital computer has a memory unit of 64K*16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words. How many bits are there in the tag, index, block and word fields of the address format? How many blocks can the caches accommodate? (10) 8. Explain the concept of memory hierarchy. (6) 9. Define the terms "spatial locality" and "temporal locality", and explain how caches are used to exploit them for a performance benefit. Be specific in the different ways that caches exploit these two phenomena. 10. Suppose physical addresses are 32 bits wide. Suppose there is a cache containing 256K words of data (not including tag bits), and each cache block contains 4 words. For each of the following cache configurations, a. direct mapped b. 2-way set associative c. 4-way set associative d. fully associative specify how the 32-bit address would be partitioned. For example, for a direct mapped cache, you would need to specify which bits are used to select the cache entry and which bits are used to compare against the tag stored in the cache entry. 11. Draw the implementation of the 2-way set associative version of the above cache, at the level of detail shown in figure 7.19 on page 574 of the text. Be sure to include the logic for selecting the desired word of the cache block. 12. Cache misses can be characterized as one of the following: compulsory misses, capacity misses, and conflict misses. Describe how each of these kinds of misses can be addressed in the hardware. 13. Suppose you own a computer that exhibits the following properties on the programs that you run: the a) pipeline can accept a new instruction every cycle the cache can provide b) data every cycle (i.e. no penalty for cache hits) the instruction cache c) miss rate is 2.5% the data cache miss rate is 3.5% d) 30% of instructions e) are memory instructions the cache miss penalty is 80 cycles. f) Suppose, also, that you have decided to purchase a new computer. For the budget allocated, you can either purchase a machine with a processor and cache that is twice as fast as your current one (memory speed is the same as the old machine, though), or purchase a machine with a processor and cache that is the same speed as your old machine but in which the cache is twice as large. Assume, for the purposes of this problem, that the cache miss rate for the programs you run will drop by 40% with this larger cache (although this is generally not true in the real

world). Which computer are you best off purchasing? Explain in detail, showing the relative performance of each choice. 14. Describe the number of bits required in each entry of a TLB that has the following characteristics: Virtual addresses a) are 32 bits wide Physical addresses are 31 bits wide b) The page size is 2K c) bytes The d) TLB contains 16 entries of the page table The TLB is direct-mapped e)

UNIT V I/O ORGANIZATION

Part A (2Marks) 1. What are the functions of I/O interface? 2. How does the processor handle an interrupt request? 3. What are the necessary operations needed to start an I/O operation using DMA? 4. What are the three types of channel usually found in large computers? 5. Why does a DMA have priority over the CPU when both request a memory transfer? 6. What is the advantage of using interrupt initiated data transfer? 7. Why do you need DMA? 8. What is the difference between subroutine and interrupt service routine? 9. What is the need for interrupt masks? 10. How does bus arbitration typically works? 11. How does a processor handle an interrupt? 12. Distinguish synchronous bus and asynchronous bus. 13. Why I/O devices cannot be directly be connected to the system bus? 14. What are the major functions of I/O system? 15. What is an I/O interface? 16. Write the factors considered in designing an I/O subsystem? 17. Explain Direct Memory Access. 18. Define DMA controller. 19. What is polling? 20. What is the need of Interrupt controller? 21. What is a priority interrupt? 22. Define bus. 23. Define synchronous bus. 24. Define asynchronous bus. 25. State the differences between memory mapped I/O and I/O mapped I/O. 26. Define interrupt. 27. Define exception. 28. What are the different methods used for handling the situation when multiple interrupts occurs? 29. What is a privileged instruction? 30. What is bus arbitration? 31. What is port? What are the types of port available? 32. What is a parallel port? 33. What is a serial port? 34. What is PCI bus? 35. What is SCSI? 36. Define USB.

Part B 1. Explain the functions to be performed by a typical I/O interface with a typical input output interface. (16) 2. Discuss the DMA driven data transfer technique. (8)

3. Discuss the operation of any two input devices (8) 4. Explain in detail about interrupt handling. (16) 5. Explain in detail about standard I/O interface. (16) 6. Describe the functions of SCSI with a neat diagram. (16) 7. What is the importance of I/O interface? Compare the features of SCSI and PCI interfaces. (8) 8. Write note on the following. a) Bus arbitration b) Printer process communication c) USB d) DMA (16) 9. Explain the use of vectored interrupts in processes. Why is priority handling desired in interrupt controllers? How does the different priority scheme work? (8) B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2010 Fourth Semester Computer Science and Engineering CS2253 COMPUTER ORGANIZATION AND ARCHITECTURE

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(Regulation 2008) Time: Three hours Maximum: 100 Marks Answer ALL Questions PART A (10 2 = 20 Marks) 1. Distinguish between autoincrement and autodecrement addressing mode. 2. Compare RISC with CISC architecture. 3. Under what situations the micro program counter is not incremented after a new instruction is fetched from micro program memory? 4. What are the relative merits of horizontal and vertical microinstruction format? 5. What is pipelining and what are the advantages of pipelining? 6. List the key aspects in gaining the performance in pipelined systems. 7. How many memory chips are needed to construct 2 M 16 memory system using 512 K 8 static memory chips? 8. What is virtual memory and what are the benefits of virtual memory? 9. What is meant by bus arbitration? 10. Name and give the purpose of widely used bus standard. PART B (5 16 = 80 Marks) 11. (a) (i) Describe the role of system software to improve the performance of a computer. (Marks 8) (ii) Design a 4-bit adder/subtracter circuit using full adders and explain its function. (Marks 8) Or (b) (i) What are the special registers in a typical computer? Explain their purposes in detail. (Marks 8)

(ii) Design a 4-bit fast adder and explain its function in detail. (Marks 8) 12. (a) (i) Draw and explain the block diagram of a complete processor. (Marks 6) (ii) Briefly describe the design of a hardwired control unit. (Marks 10) Or (b) (i) Explain the basic organization of a microprogrammed control unit and the generation of control signals using microprogram. (Marks 12) (ii) What are the advantages and disadvantages of hardwired and microprogrammed control? (Marks 4) 13. (a) (i) Describe the role of cache memory in pipelined system. (Marks 8) (ii) Discuss the influence of pipelining on instruction set design. (Marks 8) Or (b) What is instruction hazard? Explain the methods for dealing with the instruction hazards. (Marks 16) 14. (a) (i) What are the different secondary storage devices? Elaborate on any one of the devices. (Marks 8) (ii) Explain how the virtual address is converted into real address in a paged virtual memory system. (Marks 8) Or (b) (i) Explain approaches for addressing multiple-module memory systems with suitable diagrams. (Marks 6) (ii) Briefly describe magnetic disk principles and also the organization and accessing of data on a disk. (Marks 10) 15. (a) (i) Describe the hardware mechanism for handling multiple interrupt requests. (Marks 8) (ii) What are handshaking signals? Explain the handshake control of data transfer during input and output operation. (Marks 8) Or (b) (i) What are the needs for input-output interface? Explain the functions of a typical 8-bit parallel interface in detail. (Marks 10) (ii) Describe the USB architecture with the help of a neat diagram. (Marks 6)

1. Why IO devices cannot be directly be connected to the system bus? Ans: The IO devices cannot be directly connected to the system bus because 1. The data transfer rate of IO devices is slower that of CPU. 2. The IO devices in computer system has different data formats and work lengths that of CPU. So it is necessary to use a module between system bus and IO device called IO module or IO system

2. What are the major functions of IO system?

Ans: i. Interface to the CPU and memory through the system bus. ii. Interface to one or more IO devices by tailored data link.

3. What is an I/O Interface? Ans: Input-output interface provides a method for transferring binary information between internal storage, such as memory and CPU registers, and external I/O devices

4. Write the factors considered in designing an I/O subsystem? Ans: 1. 2. 3. 4. Data Location: Device selection, address of data with in device( track, sector etc) Data transfer: Amount, rate to or from device. Synchronization: Output only when device is ready, input only when data is available. I/O operation: refers to a data transfer between an I/O device and Memory or between an I/O device and CPU.

5. Explain Direct Memory Access. Ans: A modest increase in hardware enables an IO device to transfer a block of information to or from memory without CPU intervention. This task requires the IO device to generate memory addresses and transfer data through the bus using interface controllers.

6. Define DMA controller. Ans: The I/O device interface control circuit that is used for direct memory access is known as DMA controller. 7. What is polling? Ans: Polling is a scheme or an algorithm to identify the devices interrupting the processor. Polling is employed when multiple devices interrupt the processor through one interrupt pin of the processor.

8. What is the need of interrupt controller? Ans: The interrupt controller is employed to expand the interrupt inputs. It can handle the interrupt requests from various devices and allow one by one to the processor.

9. What is a Priority Interrupt? Ans: A priority interrupt is an interrupt that establishes a priority over the various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously.

10. Define bus. Ans: When a word of data is transferred between units, all the bits are transferred in parallel over a set of lines called bus. In addition to the lines that carry the data, the bus must have lines for address and control purposes.

11. Define synchronous bus. Ans: Synchronous buses are the ones in which each item is transferred during a time slot(clock cycle) known to both the source and destination units. Synchronization can be achieved by connecting both units to a common clock source.

12. Define asynchronous bus. Ans: Asynchronous buses are the ones in which each item being transferred is accompanied by a control signal that indicates its presence to the destination unit. The destination can respond with another control signal to acknowledge receipt of the items.

13. What do you mean by memory mapped I/O? Ans: In Memory mapped I/O, there are no specific input or output instructions. The CPU can manipulate I/O data residing in interface registers with the same instructions that are used to manipulate memory words i.e. the same set of instructions are used for reading and writing memory can be used to input and output.

14. What is program-controlled I/O? Ans: In program controlled I/O the processor repeatedly checks a status flags to achieve the required synchronization between the processor and an input and output device.

15. Define interrupt.

Ans: An interrupt is any exceptional event that causes a CPUU to temporarily transfer control from its current program to another program , an interrupt handler that services the event in question.

16. Define exception. Ans: The term exception is used to refer to any event that causes an interruption 17. What are the different methods used for handling the situation when multiple interrupts occurs? Ans: 1) Vectores interrupts

2) Interrupt nesting 3) Simultaneous Requests.

18. What is a privileged instruction? Ans: To protect the operating system of a computer from being corrupted by user programs, certain instructions can be executed only while the processor is in the supervisor mode. These are called privileged instruction.

19. What is bus arbitration? Ans: it is process by which the next device to become the bus master is selected and bus mastership is transferred to it. There are two ways for doing this: 1. Centralized arbitration 2. Distributed arbitration.

20. What is port? What are the types of port available? Ans: An I/O interface consists of circuitry required to connect an I/O device to computer bus. One side consists of a data path with its associated controls to transfer data between the interface and I/O device. This is called port. It is classified into: 1) Parallel port 2) Serial port.

21. What is a parallel port? Ans: A parallel port transfers data in the form a number of bits, typically 8 to 16, simultaneously to or from the device.

22. What is a serial port? Ans: A serial port transfers and receives data one bit at a time.

23. What is PCI bus? Ans: The Peripheral component interconnect(PCI) bus is a standard that supports the functions found on a processor bus but in a standardized format that is independent of any particular processor.

24. What is SCSI? Ans: It is the acronym for small computer system interface. It refers to a standard bus defined ANSI. Devices such as disks are connected to a computer via 50-wire cable, which can be upto 25 meters in length and can transfer data at rate up to 55 megabytes/s.

25. Define USB. Ans: The Universal Serial Bus(USB) is an industry standard developed to provide two speed of operation called low-speed and full-speed. They provide simple, low cost and easy to use interconnection system. 16 MARKS QUESTIONS WITH HINTS:

1. What are the functional units of a computer? Explain briefly. Hints: The different functional units are: 1) Input Unit. 2) Output Unit. 3) Memory Unit.

4) Arithmetic & logic Unit. 5) Control Unit. Refer Page no. 3-7

2. Explain the basic operational concepts of a computer. Hints: Explain about the MAR, MDR, and the connection between the processor and the memory with a neat diagram. Refer page no. 7-9.

3. Describe the different classes of instruction format with example and different addressing modes. Hints: The different instruction formats are : 1) Three address instruction 2) Two address instruction 3) Zero address instruction Refer page no. 38-42 The different addressing modes are:

Immediate addressing mode Register addressing mode Direct or absolute addressing mode Indirect addressing mode Indexed addressing mode Relative addressing mode Autoincrement Autodecrement

Refer Page no. 48-58.

4. Explain the basic input operations with suitable examples. Hints: Expalin about program-controlled I/O and memory mapped I/O. Draw the diagram of bus connection for processor , keyboard and display.

Refer Page no. 64-68

5. Write short notes on i) Software performance Hints: Refer page no. 10-12. ii) Memory locations and addresses Hints: Explain about byte addressability, big endian and little endian assignments, word alignment. Refer page no. 33-36.

6. Describe the multiplication speed up technique with an example. Hints: There are two techniques to speed up the multiplication process: 1) The first technique guarantees that the maximum number of summands that must be added is n/2 for n-bit operands ie bit pair recoding . 2) The second technique reduces the time needed to add the summands i.e Carry save addition Refer page no. 383-390

7. Explain the floating point Addition subtraction unit with neat diagram. Hints: In some cases, the binary point is variable and is automatically adjusted as computation proceeds. In such case, the binary point is said to float and the numbers are called floating point numbers. S E M

Sign of the Number 0 Positive 1 Negative

8-bit signed exponent in excess-127 representations

23- bit Mantissa fraction

value represented= 1. M 2E-127

1) Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents. 2) Set the exponent of the result equal to the larger exponent. 3) Perform addition/subtraction on the mantissa and determine the sign of the result 4) Normalize the resulting value, if necessary. Refer page no. 393-402. Draw the diagram.

8. Explain the organization of a sequential binary multiplier with example. Hints: Explain about the sequential circuit binary multiplier with registers. Write the procedure. Draw the diagram. Refer page no. 376-379.

9. Explain the Booth algorithm. Multiply 11-9 using Booth algorithm Hints: Explain about the Booth algorithm.The advantages are: 1) It handles both positive and negative multiplier uniformly. 2) It achieves efficiency in the number of additions required when the multiplier has a few large blocks of 1s. 3) The speed gained by skipping 1s depends on the data

10. Explain the Integer division techniques with suitable example. Hints: The algorithm for restoring division:

Do the following for n times: 1) Shift A and Q left one binary position. 2) Subtract M and A and place the answer back in A. 3) If the sign of A is 1, set q0 to 0 and add M back to A.

Where A- Accumulator, M- Divisor, Q- Dividend Give an example. The algorithm for non restoring division:

Do the following for n times: Step 1: Do the following for n times: 1) If the sign of A is 0 , shift A and Q left one bit position and subtract M from A; otherwise , shift A and Q left and add M to A. 2) Now, if the sign of A is 0,set q0 to 1;otherwise , set q0 to0. Step 2: if the sign of A is 1, add M to A. Give an example. Refer page no. 390-393.

11. Explain the multiple bus organization structure with neat diagram. Hints: The multiple bus organization is using more buses instead of one bus to reduce the number of steps needed and to provide multiple paths that enable several transfers to take place in parallel. Refer page no. 423-425.

12. Describe the Hardwired control method for generating the control signals Hints: Hard-wired control can be defined as sequential logic circuit that generates specific sequences of control signal in response to externally supplied instruction Refer page no. 425- 429

13.Describe the micro programmed control unit in detail. Hints: A micro programmed control unit is built around a storage unit is called a control store where all the control signals are stored in a program like format. The control store stores a set of micro programs designed to implement the behavior of the given instruction set. Refer page no. 429-445

14. Give the organization of the internal data path of a processor that supports a 4-stage pipeline for instructions and uses a 3- bus structure and discuss the same. Hints: The speed of execution of programs can be improved by arranging the hardware so that more than one operation can be performed at the same time. Explain about the 4- stage pipeline. Refer page no. 4556-459 For 3- bus structure refer page no. 479-481.

15. What is pipelining? What are the various hazards encountered in pipelining? Explain in detail. Hints: The major characteristics of a pipeline are: a) Pipelining cannot be implemented on a single task, as it works by splitting multiple tasks into a number of subtasks and operating on them simultaneously. b) The speedup or efficiency achieved by suing a pipeline depends on the number of pipe stages and the number of available tasks that can be subdivided. c) If the task that can be subdivided has uneven length of execution times, then the speedup of the pipeline is reduced. d) Though the pipeline architecture does not reduce the time of execution of a single task, it reduces the overall time taken for the entire job to get completed. The various pipeline hazards are: 1. Data hazard 2. Structural Hazard 3. Control Hazard. Refer page no. 459-476.

16. Describe the three mapping techniques used in cache memories with suitable Example.

Hints: The cache memory is a fast memory that is inserted between the larger slower main memory and the processor. It holds the currently active segments of a program and their data. i) ii) iii) Associative mapping. Direct mapping. Set-associative mapping

Refer page no. 314-325

17. Explain with neat diagram the internal organization of bit cells in a memory chip. Hints: Memory cells are usually organized in the form of an array, in which each cell is capable of storing one bit of information. Each row consists a memory word, and all cells of a row are connected to a common line referred to as word line, which is driven by he address decoder on the chip. Refer Page no. 295-297.

18. Discuss the virtual memory management technique in detail W: Write inst. E: Execute inst D:Decode & fetch inst F: Fetch instruction Hints: The data is to be stored in physical memory locations that have addresses different from those specified by the program. The memory control circuitry translates the address specified by the program into an address that can be used to access the physical memory. Refer page no. 337-343

19. Explain the various secondary storage devices in detail. Hints: The various secondary storage devices are: 1. Magnetic hard disks

2. Optical disks 3. Magnetic tape systems Refer page no. 344-359

20. What is memory interleaving? Explain with neat diagram. Hints: The main memory of a computer is structure as a collection of physically separate modules each with its own address buffer register and data buffer register, memory access operations may proceed in more than one module at the same time. Thus the aggregate rate of transmission of words to and from the main memory system can be increased. Refer page no. 330-331

21. Describe the data transfer method using DMA. Hints: A modest increase in hardware enables an IO device to transfer a block of information to or from memory without CPU intervention. This task requires the IO device to generate memory addresses and transfer data through the bus using interface controllers. Refer page no. 234-240.

22. Explain about the interrupts in detail Hints: An interrupt is any exceptional event that causes a CPUU to temporarily transfer control from its current program to another program , an interrupt handler that services the event in question. Refer page no. 208-221.

23. Explain the different types of buses with neat diagram. Hints: When a word of data is transferred between units, all the bits are transferred in parallel over a set of lines called bus. In addition to the lines that carry the data, the bus must have lines for address and control purposes.The different types of buses are: 1. Synchronous Buses: Synchronous buses are the ones in which each item is transferred during a time slot(clock cycle) known to both the source and destination units. Synchronization can be achieved by connecting both units to a common clock source. 2. Asynchronous buses

Asynchronous buses are the ones in which each item being transferred is accompanied by a control signal that indicates its presence to the destination unit. The destination can respond with another control signal to acknowledge receipt of the items. Refer page no. 241-247

24. Explain the various interface circuits. Hints: An I/O interface consists of circuitry required to connect an I/O device to computer bus. One side consists of a data path with its associated controls to transfer data between the interface and I/O device. This is called port. It is classified into: 1) Parallel port 2) Serial port. Refer page no. 248-259.

25. Explain in details the various standard I/O interfaces. Hints: The various standard I/O interfaces are: 1. The Peripheral component interconnect(PCI) bus is a standard that supports the functions found on a processor bus but in a standardized format that is independent of any particular processor 2. It is the acronym for small computer system interface. It refers to a standard bus defined ANSI. Devices such as disks are connected to a computer via 50-wire cable, which can be upto 25 meters in length and can transfer data at rate up to 55 megabytes/s. 3. The Universal Serial Bus(USB) is an industry standard developed to provide two speed of operation called low-speed and full-speed. They provide simple, low cost and easy to use interconnection system. Refer Page no. 259-281.