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Compare/Capture/PWM (CCP)
HIGHLIGHTS
This section of the manual contains the following major topics: 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 Introduction .................................................................................................................. 17-2 CCP Control Register .................................................................................................. 17-3 Capture Mode .............................................................................................................. 17-4 Compare Mode ............................................................................................................ 17-7 PWM Mode ................................................................................................................ 17-10 Initialization ................................................................................................................ 17-15 Design Tips ................................................................................................................ 17-17 Related Application Notes.......................................................................................... 17-19 Revision History ......................................................................................................... 17-20
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CCP
DS39517A-page 17-1
17.1.1
Timer Resources
Table 17-2 shows the resources of the CCP modules, in each of its modes. Table 17-3 shows the interactions between the CCP modules, where CCPx is one CCP module and CCPy is another CCP module. Table 17-2: CCP Mode - Timer Resource CCP Mode Capture Compare PWM Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2
Table 17-3: Interaction of Two CCP Modules CCPx Mode Capture Capture CCPy Mode Capture Interaction TMR1 or TMR3 time-base. Time base can be different for each CCP.
Compare The compare could be configured for the special event trigger, which clears either TMR1 or TMR3 depending upon which time base is used.
Compare Compare The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3 depending upon which time base is used. PWM PWM PWM PWM Capture The PWMs will have the same frequency, and update rate (TMR2 interrupt). None
Compare None
DS39517A-page 17-2
Unimplemented: Read as '0' DCxB<1:0>: PWM Duty Cycle bit1 and bit0 Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
17
CCP
bit 3-0
CCPxM<3:0>: CCPx Mode Select bits 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = Capture/Compare/PWM off (resets CCPx module) Reserved Compare mode, toggle output on match (CCPxIF bit is set) Reserved Capture mode, every falling edge Capture mode, every rising edge Capture mode, every 4th rising edge Capture mode, every 16th rising edge Compare mode, Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set) Compare mode, Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set) Compare mode, Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected) Compare mode, Trigger special event (CCPIF bit is set) PWM mode
DS39517A-page 17-3
An event is selected by control bits CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set. The CCPxIF bit must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value will be lost. Note: The dedicated time base (Timer1 or Timer3) must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCPxIE clear to avoid false interrupts and should clear flag bit CCPxIF following any such change in operating mode. Figure 17-1 shows that a capture does not modify (clear) the 16-bit timer register. This is so the timer (Timer1 or Timer3) can also be used as the time-base for other operations. The time between two captures can easily be computed as the difference between the value of the 2nd capture and that of the 1st capture. When the timer overflows, the timer interrupt bit, TMRxIF will be set. If enabled, an interrupt will occur, allowing the time-base to be extended to greater than 16 bits.
DS39517A-page 17-4
17
TMR3L TMR3 Enable
T3CCP2
CCP
CCPR1L
TMR1L
TMR3L
CCPR2L
T3CCP2 T3CCP1
TMR1H
TMR1L
CCP2CON<3:0> Qs
DS39517A-page 17-5
To clear the Capture prescaler count, the CCP module must be configured into any non-capture CCP mode (Compare, PWM, or CCP off modes).
17.3.3
Sleep Operation
When the device is placed in SLEEP, the timer will not increment (since it is in synchronous mode), but the prescaler will continue to count events (not synchronized). When a specified capture event occurs, the CCPxIF bit will be set, but the capture register will not be updated. If the CCP interrupt is enabled, the device will wake-up from SLEEP. The value in the 16-bit TMR1 register is not transferred to the 16-bit capture register. Effectively, this allows the CCP pin to be used as another external interrupt.
17.3.4
Effects of a Reset
The CCP module is off, and the value in the capture prescaler is cleared.
DS39517A-page 17-6
The action on the pin is based on the value of control bits CCPxM3:CCPxM0 (CCPxCON3:CCPxCON0). At the same time, interrupt flag bit CCPxIF is set. Note: The dedicated time base (Timer1 or Timer3) must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
17
CCP
CCPR1H CCPR1L Q CCP1 Pin TRISX<Y> Output Enable S R Output Logic Comparator
match
T3CCP2
TMR1L
TMR3H
TMR3L
T3CCP1 T3CCP2
S R
Output Logic
DS39517A-page 17-7
Selecting the compare output mode, forces the state of the CCP pin to the state that is opposite of the match state. So if the Compare mode is selected to force the output pin low on match, then the output will be forced high until the match occurs (or the mode is changed). In the compare toggle mode, the CCPx pin output is initially forced to the low state.
17.4.2
17.4.3
17.4.4
Sleep Operation
When the device is placed in SLEEP, the timer will not increment (since it is in Synchronous mode), and the state of the module will not change. If the CCP pin is driving a value, it will continue to drive that value. When the device wakes-up, it will continue from this state.
17.4.5
Effects of a Reset
The CCP module is off.
DS39517A-page 17-8
Name
INTCON PIR1 PIE1 IPR1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON PIR2 PIE2 IPR2 TMR3L TMR3H T3CON
Bit 7
GIE/ GIEH PSPIF (1) PSPIE (1) PSPIP (1)
Bit 6
PEIE/ GIEL ADIF ADIE ADIP
Bit 5
TMR0IE RCIF RCIE RCIP
Bit 4
INT0IE TXIF TXIE TXIP
Bit 3
RBIE SSPIF SSPIE SSPIP
Bit 2
TMR0IF CCP1IF CCP1IE CCP1IP
Bit 1
INT0IF TMR2IF TMR2IE TMR2IP
Bit 0
RBIF TMR1IF TMR1IE TMR1IP
PORTC Data Direction Register Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1register RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) DC1B1 DC1B0 Capture/Compare/PWM register2 (LSB) Capture/Compare/PWM register2 (MSB) DC2B1 DC2B0
17
CCP
Holding register for the Least Significant Byte of the 16-bit TMR3 register Holding register for the Most Significant Byte of the 16-bit TMR3 register RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
Legend:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture, Compare, Timer1 and Timer3. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2x2 devices. Always maintain these bits clear.
DS39517A-page 17-9
Figure 17-3 shows a simplified block diagram of one CCP module in PWM mode. Depending on the device there can be more than one CCP module connected to Timer2. Each CCP module can support one Pulse Width Modulation (PWM) output signal. This PWM signal can attain a resolution of up to 10-bits, from the 8-bit Timer2 module. Two extra bits are used to extend Timer2 to 10 bits (see Section 17.5.1 ). A PWM output waveform is shown in Figure 17-4. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 17.5.4. Figure 17-3: Simplified PWM Block Diagram
Duty Cycle Registers CCPRxL (DCxB<9:2>) 10 CCPxCON<5:4> (DCxB<1:0>)
TRIS<y>
CCPx
(Note 1)
Clear Timer, Force CCPx pin high, and latch the Duty Cycle
Note 1: For 10-bit time base generation see Section 17.5.1. Figure 17-4: PWM Output Waveform
DutyCycle = DCxB9:DCxB0 Period = PR2 + 1
1 1 2 3
Timer2 is cleared and new duty cycle value is loaded from the Duty Cycle latch into the Duty Cycle Slave register Timer2 value equals to value in Duty Cycle Latch register, CCP Pin is driven low Timer2 overflow, value from Duty Cycle Latch is loaded into Slave Register, CCP Pin driven high
DS39517A-page 17-10
TB9
TMR2
TB2
TB1
(1)
TB0 (1)
17
CCP
Note 1:
These two bits are not readable or writable and are not mapped into the data memory.
17.5.2
PWM Period
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using Equation 17-1. Equation 17-1:Calculation for PWM Period TPWM period = [(PR2) + 1] 4 TSCLK (TMR2 prescale value) Where PR2 = Value in PR2 Register TSCLK = Oscillator Clock When TMR2 is equal to PR2, the following three events occur on the next increment cycle: TMR2 is cleared The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set) The PWM duty cycle is latched from CCPRxL into CCPRxH Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to generate TMR2 interrupts at a different frequency than the PWM output.
DS39517A-page 17-11
)
bits
If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. This allows a duty cycle of 100%.
The minimum resolution (in time) of each bit of the PWM duty cycle depends on the prescaler of Timer2. Table 17-5 shows the selections for the minimum resolution time. Table 17-5: Minimum Duty Cycle Bit Time Prescaler Value 1 4 16 T2CKPS1:T2CKPS0 0 0 0 1 1 x Minimum Resolution (Time) TSCLK TCY 4 TCY
DS39517A-page 17-12
17
CCP
Find the maximum resolution of the duty cycle that can be used with a 78.125 kHz frequency and 20 MHz oscillator: 1 / 78.125 kHz = 2PWM RESOLUTION 1/20 MHz 1 12.8 ms 256 log(256) = 2PWM RESOLUTION 50 ns 1 = 2PWM RESOLUTION = (PWM Resolution) log(2)
PWM Resolution= 8.0 At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and a 20 MHz oscillator (i.e., 0 DCxB9:DCxB0 255). Any value greater than 255 will result in a 100% duty cycle. In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Table 17-6 lists example PWM frequencies and resolutions for FOSC = 20 MHz. Table 17-7 lists example PWM frequencies and resolutions for FOSC = 40 MHz. The TMR2 prescaler and PR2 values are also shown. Table 17-6: Example PWM Frequencies and Bit Resolutions at 20 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 5.5
Table 17-7: Example PWM Frequencies and Bit Resolutions at 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2.44 kHz 16 0xFF 10 9.76 kHz 4 0xFF 10 39.06 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 208.3 kHz 1 0x1F 7 416.6 kHz 1 0x17 5.5
DS39517A-page 17-13
17.5.5
Sleep Operation
When the device is placed in sleep, Timer2 will not increment, and the state of the module will not change. If the CCP pin is driving a value, it will continue to drive that value. When the device wakes-up, it will continue from this state.
17.5.6
Effects of a Reset
The CCP module is off.
Name
INTCON PIR1 PIE1 IPR1 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
Bit 7
GIE/GIEH
Bit 6
PEIE/GIEL
Bit 5
TMR0IE
Bit 4
INT0IE
Bit 3
RBIE
Bit 2
TMR0IF
Bit 1
INT0IF TMR2IF (1) TMR2IE (1) TMR2IP (1)
Bit 0
RBIF
PORTC Data Direction Register Timer2 modules register Timer2 modules period register TOUTPS3 TOUTPS2
Legend:
x = unknown, u = unchanged, = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39517A-page 17-14
17
CCP
Timer1 starts to increment ; ; The CCP1 interrupt is disabled, ; do polling on the CCP Interrupt flag bit ; Capture_Event BTFSS PIR1, CCP1IF GOTO Capture_Event ; ; Capture has occured ; BCF PIR1, CCP1IF ; This needs to be done before ; next compare
DS39517A-page 17-15
Timer1 starts to increment ; ; The CCP1 interrupt is disabled, ; do polling on the CCP Interrupt flag bit ; Compare_Event BTFSS PIR1, CCP1IF GOTO Compare_Event ; ; Compare has occured ; BCF PIR1, CCP1IF ; This needs to be done before ; next compare
Example 17-5:PWM Initialization CLRF CLRF MOVLW MOVWF MOVLW MOVWF CLRF BCF CLRF CLRF MOVLW MOVWF BSF CCP1CON TMR2 0x7F PR2 0x1F CCPR1L INTCON TRISC, PWM1 PIE1 PIR1 0x2C ; ; ; ; ; ; ; ; ; ; ; ; CCP1CON ; T2CON, TMR2ON ; CCP Module is off Clear Timer2
Duty Cycle is 25% of PWM Period Disable interrupts and clear T0IF Make pin output Disable peripheral interrupts Clear peripheral interrupts Flags PWM mode, 2 LSbs of Duty cycle = 10
Timer2 starts to increment ; ; The CCP1 interrupt is disabled, ; do polling on the TMR2 Interrupt flag bit ; PWM_Period_Match BTFSS PIR1, TMR2IF GOTO PWM_Period_Match ; ; Update this PWM period and the following PWM Duty cycle ; BCF PIR1, TMR2IF
DS39517A-page 17-16
What timers can I use for the capture and compare modes?
17
CCP
Can I use one CCP module to do capture (or compare) AND PWM at the same time, since they use different timers as their reference?
I am setting up the CCP1CON module for Compare Mode, trigger special event (1011) that resets TMR1. When a compare match occurs, will I have both the TMR1 and the CCP1 interrupts pending (TMR1IF is set, CCP1IF is set)?
Answer 5: The CCP1IF flag will be set on the match condition. TMR1IF is set when Timer1 overflows, and the special trigger reset of Timer1 is not considered an overflow. However, if both the CCPR1L and CCPR1H registers are set at FFh, then an overflow occurs at the same time as the match, which will then set both CCP1IF and TMR1IF. Question 6: Answer 6: Timer2 always resets to zero when it equals PR2 and flag bit TMR2IF always gets set at this time. By putting FFh into PR2, you will get an interrupt on overflow at FFh. Quite often it is desirable to have an event occur at a periodic rate, perhaps an interrupt driven event. Normally an initial value would be placed into the timer so that the overflow will occur at the desired time. This value would have to be placed back into the timer every time it overflowed to make the interrupts occur at the same desired rate. The benefit of Timer2 is that a value can be written to PR2 that will cause it to reset at your desired time interval. This means you do not have the housekeeping chore of reloading the timer every time it overflows, since PR2 maintains its value.
How do I use Timer2 as a general purpose timer, with an interrupt flag on rollover?
DS39517A-page 17-17
I am using a CCP module in PWM mode. The duty cycle being outputted is almost always 100%, even when my program writes a value like 7Fh to the duty cycle register, which should be 50%. What am I doing wrong?
Answer 7: 1. The value in CCPRxL is higher than PR2. This happens quite often when a user desires a fast PWM output frequency and writes a small value in the PR2. In this case, if a value of 7Eh were written to PR2, then a value 7Fh in CCPRxL will result in 100% duty cycle. If the TRIS bit corresponding to the CCP output pin you are using is configured as an input, the PWM output cannot drive the pin. In this case, the pin would float and duty cycle may appear to be 0%, 100% or some other floating value.
2.
Question 8:
I want to determine a signal frequency using the CCP module in capture mode to find the period. I am currently resetting Timer1 on the first edge, then using the value in the capture register on the second edge as the time period. The problem is that my code to clear the timer does not occur until almost twelve instructions after the first capture edge (interrupt latency plus saving of registers in interrupt), so I cannot measure very fast frequencies. Is there a better way to do this?
Answer 8: You do not need to zero the counter to find the difference between two pulse edges. Just take the first captured value and put it into another set of registers. Then when the second capture event occurs, subtract the first event from the second. Assuming that your pulse edges are not so far apart that the counter can wrap around past the last capture value, the answer will always be correct. This is illustrated by the following example: 1. 2. 3. First captured value is FFFEh. Store this value in two registers. The second capture value is 0001h (the counter has incremented three times). 0001h - FFFEh = 0003, which is the same as if you had cleared Timer1 to zero and let it count to 3. (Theoretically, except that there was a delay getting to the code that clears Timer1, so actual values would differ).
The interrupt overhead is now less important because the values are captured automatically. For even faster inputs, do not enable interrupts and just test the flag bit in a loop. If you must also capture very long time periods, such that the timer can wrap around past the previous capture value, then consider using an auto-scaling technique that starts with a large prescale, and shorten the prescale as you converge on the exact frequency.
DS39517A-page 17-18
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CCP
Note:
Please visit the Microchip Web site for additional software code examples. These code examples are stand alone examples to assist in the understanding of the PIC18CXXX. The web address for these examples is: http://www.microchip.com/10/faqs/codeex/
DS39517A-page 17-19
DS39517A-page 17-20