Princess Sumaya Univ.

Computer Engineering Dept.

4241 Digital Logic Design Timing Analysis

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4241 - Digital Logic Design

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Sequential Circuits Sequential circuits can contain both combinational logic and edge-triggered flip flops A clock signal determines when data is stored in flip flops How fast can the circuit operate?
Minimum clock period: Tmin
Maximum clock frequency: fmax

Maximum clock frequency is the inverse of the minimum clock period Clock
1/Tmin = fmax Period

Clock

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Combinational Logic Timing: Inverter Combinational logic is made from electronic circuits
An input change takes time to propagate to the output

The output remains unchanged for a time period equal to the contamination delay tcd The new output value is guaranteed to be valid after a time period equal to the propagation delay tpd
A

Y t cd t pd

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Combinational Logic Timing: XNOR Gate The output is guaranteed to be stable with old value until the contamination delay
Unknown values shown in waveforms as Xs

The output is guaranteed to be stable with the new value after the propagation delay

A B

C
C t cd t pd

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Combinational Logic Timing: complex circuits

Tpd = 2ns Tcd = 1ns

Circuit X
Tpd = 3ns Tcd = 1ns

A B

Circuit X

B Propagation delays are additive

Locate the longest combination of tpd

Tpd = 5ns Tcd = 1ns

Contamination delays may not be additive

Locate the shortest path of tcd

Find propagation and contamination delay of new, combined circuit

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Clocked Device: Contamination and Propagation Delay Timing parameters for clocked devices are specified in relation to the clock input (rising edge) Output is unchanged for a time period equal to the contamination delay tcd after the rising clock edge New output is guaranteed to be valid after a time period equal to the propagation delay tClk-Q after the rising clock edge
D Q
D Clk Q t cd t Clk-Q

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Clocked Devices: Setup and Hold Times Timing parameters for clocked devices are specified in relation to the clock input (rising edge) D input must be valid at least a setup time ts before the rising clock edge D input must be held steady for a hold time th after rising clock edge Setup and hold are input restrictions
Failure to meet restrictions causes circuit to operate incorrectly

ts
D Clk Q

th

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Analyzing Sequential Circuits

TClk-Q = 5ns D X Tpd = 5ns Comb. Logic G CLK Y TClk-Q = 5 ns Ts = 2 ns

FFA

FFB

What is the minimum time between rising CLK edges?

Tmin = TCLK-Q (FFA) + Tpd (G) + Ts (FFB)

Fmax = _______

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Analyzing Sequential Circuits

Tpd = 4ns Comb. Logic F

Comb. Logic H

FFA

FFB

Tpd = 5ns
CLK TClk-Q = 5ns TClk-Q = 4 ns Ts = 2 ns

What is the minimum clock period (Tmin) of this circuit? Hint: evaluate all FF to FF paths

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4241 - Digital Logic Design

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Analyzing Sequential Circuits

Tpd = 4ns Comb. Logic F

Comb. Logic H Tpd = 5ns

FFA CLK

FFB

TClk-Q = 5ns

Path FFA to FFB Path FFB to FFB

TClk-Q = 4 ns Ts = 2 ns

TClk-Q(FFA) + Tpd(H) + Ts(FFB) = 5ns + 5ns + 2ns

TCLK-Q(FFB) + Tpd(F) + Tpd(H) + Ts(FFB) = 4ns + 4ns + 5ns + 2ns

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Analyzing Sequential Circuits: Hold Time Violation

Tcd = 1ns
D X Tcd = 2ns Comb. Logic Y

Th = 2 ns

FFA

FFB

G
CLK

Y should remain stable for the hold time (Th) after the rising clock edge
Contamination delay ensures signal doesnt change How long before Y starts to change?
Tcd(FFA) + Tcd(G) Th 1ns + 2ns > 2ns

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Analyzing Sequential Circuits: Hold Time Violations

Tcd = 1ns All paths must satisfy requirements Comb. Logic F

Comb. Logic H Tcd = 2ns

FFA CLK

FFB

Path FFA to FFB

TClD = 1ns

TCD(FFA) + TCD(H) Th(FFB) 1 ns + 2ns > 2ns

TClD = 1 ns Th = 2 ns

Path FFB to FFB

TCD(FFB) + TCD(F) + TCd(H) Th(FFB) 1ns + 1ns + 2ns > 2ns

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Homework
1. Find the contamination and propagation delays for the priority encoder shown in Mano's Fig. 4-23. Assume contamination delays of 1 ns, 1.5 ns and 2 ns for inverters, OR gates, and AND gates, respectively. Assume propagation delays of 2 ns, 2.5 ns, and 3 ns for inverters, OR gates, and AND gates, respectively. Consider all input-to-output paths when determining the contamination and propagation delays for the circuit taken as a whole. Consider the sequential circuit shown in Mano; Fig. 5-17(a). Assume contamination and propagation delays of 1 ns and 2 ns for the XOR gates. Assume contamination and propagation delays of 2 ns and 10 ns, respectively, for the D flip-flop. Assume a setup time of 3 ns and a hold time of 5 ns for the D flip flop. a) Calculate the maximum clock frequency for this circuit. (Ignore the inputs x and y for this part.) b) For proper operation of the circuit, how long before the clock pulse must the data inputs x and y become stable? How long must they be held stable?

2.

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Summary Maximum clock frequency is a fundamental parameter in sequential computer systems Possible to determined clock frequency from propagation delays and setup time The longest path determines the clock frequency

All flip-flop to flip-flop paths must be checked

Hold time are satisfied by examining contamination delays

The shortest contamination delay path determines if hold times are met