F9 : Asynchronous State Machines (ASMs)

Asynchronous Sequential Machines

An Asynchronous Sequential Machine is a Sequential Machine without Flip-flops inside. Asynchronous Sequential Machines are based on an analysis of feedbacks in combinatorial gate networks. Prerequisite: Only ONE signal in the gate network at the time is allowed to change its value at any point in time.

The D-Latch (a Mux with a feedback)

M UX
f 1 f 0 1 0 f

Lat ch
D D Q

Sel ect Enable

Q D

Enabl e 0 1

D Q - M D D

Enabl e

Asynchronous behaviour
M UX
Pr es.st at e f 0 1 N extst at e Sel f 01 10 1 = 00 F F F 0 1 0 1 0 0 11 F 1 f 0 1 Sel ect 0 f 1 1 F f

Letus anal yze t he M ux w i t ht he f eedback agai n.Thi st i m e, we i ncl ude t he del ay i nsi de t he M ux.Then i ti s possi bl et o wr i t e dow n t he st at et abl ef ort he st at e m achi ne oft he syst em .

State Machine of the D-Latch (Moore)

Self 1=11

00, 01 Self 1=10,

0
Self 1=10

Self 00, 01 1=11,

Excitation table
Pr es.St at e f 0 1 N extst at e Sel f 1 = 00 F 0 1 01 F 0 1 10 F 0 0 11 F Q 1 1 0 1

The asynchr onous st at et abl ei s cal l ed an Exci t at i on t abl e. St abl e st at es ( w her e nextst at e = pr es.st at e)ar e m ar ked by a ci r cl e.

State Machine of the D-latch (Mealy)

Pr es.st at e 0 1 N extst at e 01 10 Sel f 1 = 00 0 0 0 1 1 0 11 1 1 O ut putQ Sel f 01 1 = 00 0 0 1 1 10 0 11 1

Self 1=11 |-

Self 00, 01 |0 1=10,

0
Self 1=10 |-

Self 00, 01 |1 1=11,

The Flow table

Pr es.St at e f A B N extst at e Sel f 1 = 00 F A B 01 F A B 10 F A A 11 F Q B B 0 1

I nt he Fl ow Tabl e,abst r actst at es ( t hati s,a st at e bef or ei thas been assi gned a bi nar y code)ar e assi gned.St abl e st at es ar e m ar ked w i t h a ci r cl e.

Analysis of Asynchronous Circuits.

The analysis is performed using the following procedure:
1) Replace feedbacks in the circuit with a delay-element i. The input-signal to the delay-element composes the next state signal Yi, while the output signal yi represents the present state. 2) Find out the expressions for the next state and output 3) Create the corresponding Excitation Table 4) Create a Flow Table and replace coded States with Symbolic ones. 5) Draw a state diagram if needed.

Example: The D Flip-flop

M ast er Sl ave
D
ym ys Y m =D C l k + Cl k ym

Q Q

Y s=ym C l k + Cl k ys

Exci t at i on Tabl e
P re s . S ta te ym ys Ne xt s ta te Clk D = 00 01 YmYs 00 00 11 11 00 00 11 11 10 00 01 00 01 11 Q 10 11 10 11 0 1 0 1

Clk

D Fl i pf l op
D Q Q

00 01 10 11

Exploiting impossible transitions

P re s . S ta te ymys S0 S1 S2 S3 Ne xt s ta te Clk D = 00 01 Ym Ys S0 S0 S3 S3 S0 S0 S3 S3 10 S0 S1 S0 S1 11 Q S2 S3 S2 S3 0 1 0 1

The i nputm ust have been 10 t o end up i nt hi s st at e. Thus,t he nexti nput cannotbe 01.

I m possi bl et r ansi t i ons ( onl y one si gnalcan change val ue at t he sam e t i m e)can be r epl aced w i t h a D on tC ar e! ! !

D-Flip-Flop state diagram (Moore)

Cl k D =11

Cl k D = 00, 01, 10

S0

Cl k D =10

S2

Cl k D =11

Cl k D =00

Cl k D =11

Cl k D = 01

Cl k D =10

S1 Cl k D =10

S3

Cl k D =00,01,11

Design of Asynchronous Circuits

To design an Asynchronous circuit, the following procedure can be used:
1) Create a State Diagram according to the functional specification. 2) Create a Flow Table and reduce the number of states as far as possible. 3) Assign binary codes to the states and create the Excitation Table. 4) Write down the expressions for the next state and output functions. 5) Draw a circuit that implements the derived expressions.

Example: A Serial Parity Generator

I nputx;out puty;y=1 i ft he num berofpul ses on t he i nputx has been odd.y=0 i ft he num berofpul ses has been even.

x=0

A/ 0

x=1

B/ 1

x=1

x=0

x=0

x=1

D/ 0

x=1

C/ 1

x=0

Example ctd.: Flow Table

Pr es st at e N extSt at e Q

X=0 A B C D A C C A

1 B B D D 0 1 1 0

Example ctd.: Excitation table

Pr es st at e N extSt at e Q

Pr es st at e

N extSt at e

X=0 y2y1 00 01 10 11 Y 2Y 1 00 10 10 00

1
y2y1

X=0 Y 2Y 1 00 11 11 00

01 01 11 11

0 1 1 0

00 01 11 10

01 01 10 10

0 1 1 0

B ad code ( H D =2! )

G ood C ode ( H D =1)

Create the Karnaugh diagram

Pr es st at e N extSt at e Q

x 0 1

y2y1 00 01 11 10 0 1 1 0 0 0 1 1

x 0 1

y2y1 00 01 11 10 0 1 1 0 1 1 0 0

X=0 y2y1 00 01 11 10 Y 2Y 1 00 11 11 00

01 01 10 10

0 1 1 0

Y 2= x y1+ y2y1 + x y2 y1 0 0 0

Y 1= x y2+ y2y1+ x y1

y2 0 1

1 1 1

Q =y1

Example ctd.: Draw the Circuit

x 0 1 y2y1 00 01 11 10 0 1 1 0 0 0 1 1 y2 0 1 y1 0 0 0 1 1 1

Y 2= x y1+ y2y1 + x y2 Q =y1 y2y1 00 01 11 10 0 1 1 0 1 1 0 0 y2 x y1 Q

x 0 1

Y 1= x y2+ y2y1+ x y1

State Minimization
Procedure for minimization of the number of states
1) Create Equivalance classes
- Output with the same value belong to the same group plus - Stable states must be at the same place plus - Dont cares in the next state position must be at the same place

2) Minimize the equivalence classes using state reduction 3) Build a Merger Diagram, either for a Mealy or for a Moore implementation. 4) Merge Compatible states in groups while keeping the number of groups minimal. Each state may only be part of one group. 5) Design the reduced Flow Table by merging the rows of the selected groups. 6) Repeat step 3-5 until no more minimizations can be performed.

Example: Coca Cola Machine

TF=00 F F B/ 0 TF=00 TF=00 F F E/ 1 T D/ 0 T F/ 1 T A/ 0 T C/ 1 Pres state A B C D E F Next State TF=00 01 10 A D A D A A B B E E C C F F Q 11 0 0 1 0 1 1

A Fl ow Tabl e onl y cont ai ni ng O N E St abl e St at e perr ow i s cal l ed a Primitive Fl ow Tabl e.

State reduction
Equi val ence cl asses
p1=( AD ) ( B) ( C F) ( E) p2=( A) ( D) ( B) ( C F) ( E) p3=p2.

Pr i mi t i ve Fl ow Tabl e
Pres state A B C D E F Next State TF=00 01 10 A D A D A A B B E E C C F F Q 11 0 0 1 0 1 1

R esul t i ng Fl ow Tabl e
Pres state A B C D E Next State TF=00 01 10 A D A D A B B E E C C C Q 11 0 0 1 0 1

Merger diagram
R esul t i ng Fl ow Tabl e
Pr es st at e A B C D E N ext St at e TF=00 01 10 11 A D A D A B B E E C C C Q 0 0 1 0 1

C om pat i bi l i t y gr aph C E M oor e com pat i bl e

Ever y R ow becom es a poi nti nt he com pat i bi l i t y gr aph.

M eal y com pat i bl e

An illustrative Example
Equi val ence cl asses Pr i mi t i ve Fl ow Tabl e
P re s s ta te A B C D E F G H J K L N e xt S ta te X= 0 0 0 1 1 0 1 1 A A G G G G A F B F F B L B L C C E J E J E H D D D K H K K Q 0 1 0 1 1 0 0 1 0 1 1

P 1= ( AG ) ( BL) ( C) ( D) ( E) ( F) ( H K) ( J) P 2= ( A) ( G) ( BL) ( C) ( D) ( E) ( F) ( H K) ( J) P 3=P 2

R educed Fl ow Tabl e
P re s sta te A B C D E F G H J Ne xt S ta te X=00 01 10 11 A A G G G G F B F F B B C C E J E J H D D D H H Q 0 1 0 1 1 0 0 1 0

An illustrative example (ctd.)

H B D E

R educed Fl ow Tabl e
P re s s ta te A B C D E F G H J Ne xt S ta te X=00 01 10 11 A A G G G G F B F F B B C C E J E J H D D D H H Q 0 1 0 1 1 0 0 1 0

0
A F J G C
Q 0 1 0 1 0

Pr es st at e A B C D G

N extSt at e X=00 01 10 11 A A G G G A B C D B B D D -

- C A B D G

An illustrative example (ctd.)

R educed f l ow t abl e
Pr es st at e A B C D G N extSt at e X=00 01 10 11 A A G G G A B C D B B D D Q

Fi nalf l ow t abl e
0 1 0 1 0 Pr es st at e A B C D N extSt at e X=00 01 10 11 A A C C A B B A C D C D B B D D Q 0 1 0 1

- C A B D G

State encoding
Procedure to check out good binary codes:
1) Draw transition diagrams along the edges of the Hypercube created by the codes. 2) Remove any crossing lines by a) exchange places on two neighbouring nodes b) use available codes not currently used (exploit unstable states) c) introduce more dimensions in the Hyper cube (i.e., add more Flip-flops)

Serial Parity Generator revisited

C =10 x=1 D =11

D =10 x=1 C =11

x=0

x=0

x=0

x=0

A=00

x=1

B=01

A=00

x=1

B=01

Bad code

G ood code

Exploiting Unstable States

C =10
01 00 00 10 00

C =10

10 01 01 00

Justpassi ng t hr ough. . .

10

A=00 01
11

B=01

A=00 01
11

B=01

Bad code

G ood code

Extra States (more dimensions)

G A B A
E

B
F G

D C A

E F B

Avoid Hazard!
St at i c hazar di s caused by m i ssi ng pr i mei m pl i cant si n t he Kar naugh Di agr am

St at i c1 1

St at i c0 0

D ynam i c1 0

D ynam i c0 1

D ynam i c hazar d can happen i n an ASM w hen passi ng unst abl e st at es w i t h di f f er entout put val ues.

Example of Blinking when passing Unstable States

Pr es st at e N extSt at e Q

X=0 y2y1 Y 2Y 1 00 00 01 11

D ynam i c 1 0 H azar d on Q ( out puti s bl i nki ng)

00 01 11 10

01 11 10 10

0 1 0 1

D ynam i c 0 1 H azar d on Q ( out puti s bl i nki ng)

More examples of Blinking

P re s s ta te XY=00 y2 y1 00 01 10 11 00(1) 00(1) 01(1) --(-) Ne xt S ta te 01 Y2 Y1 00(0) 10(0) 11(0) 01(1) --(-) --(-) 11(0) 10 11

10(1) 00(0)

D anger ous t r ansi t i on! ! ! The M achi ne m i ghthang i fy2 happens t o change f i r ston t he w ay t o st at e 11 f r om pr es st at e 00.

01(1) 10(1) 11(0)

M eal y not at i on:St at e( out put )