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Resonant Inverter with a Variable-Frequency Asymmetrical Voltage-Cancellation Control for Low Q-Factor Loads in Induction Cooking

Samart Yachiangkam1, Anawach Sangswang1, Sumate Naetiladdanon1, Chayant Koompai1, and Saichol Chudjuarjeen2 Department of Electrical Engineering, Faculty of Engineering King Mongkut's University of Technology Thonburi Bangkok, Thailand 2 Department of Electrical and Telecommunication Engineering, Faculty of Engineering Rajamangala University of Technology Krungthep Bangkok, Thailand Tel.: +66 / (2) 470 90 41 Fax: +66 / (2) 470 90 43 E-Mail: mart_northern@hotmail.com, anawach.san@kmutt.ac.th, sumate.nae@kmutt.ac.th URL: http://www.ee.kmutt.ac.th
1

Keywords
Resonant converter, Induction cooking, Switching losses, ZVS converter, Efficiency

Abstract
This paper presents a power control strategy of the full-bridge series resonant inverter based on the asymmetrical voltage-cancellation control with variable-frequency in induction cooking appliances with a load of low Q factor on the domestic markets. The switching frequency of inverter is suitably operated higher than the resonant frequency under zero-voltage-switching (ZVS) condition. The proposed control strategy ensures to minimize the switching loss in all switches of inverter, so that can improve the efficiency of inverter system. The theoretical results of proposed control method are verified by simulation and experimental results as shown in this paper. The advantages of the proposed control are simple, low switching loss and system reliability for the entire operating region.

Introduction
The induction cooking appliance is one of the induction heating applications using the power semiconductor devices and a high-frequency switching (20kHz up to 100kHz), and is used in home appliance due to as its cleanness, safety, maintainability, quick warming, controllability, high efficiency, high reliability, and low cost [1], [2]. In recent years, the induction cooking have been focused on the development of the control strategy by using high switching frequency with a resonant inverters to eliminate the switching loss of semiconductor devices with operation of the soft switching or the zero-voltage-switching (ZVS) operation. The output power of inverter can be controlled by using various control methods. The square wave (SW) modulation controls the output power by adjusting the switching frequency while the inverter operates under ZVS condition [3], [4]. The pulse density modulation (PDM) technique controls the output power by adjusting the period of switches [4]-[6]. The asymmetrical duty cycle (ADC) control regulates the output power by adjusting the switching frequency and duty cycle [7], [8]. The discontinuous current mode (DCM) varies the output power by varying the switching frequency and the duty cycle which depends on the switching frequency [9]. The phase-shift (PS) control varies the output power by shifting the phase of the switch conduction sequences [10], [11]. The asymmetrical voltage-cancellation (AVC) control with a fixedfrequency control technique that varies the output power by varying the control angle [12]-[14]. This

method is proper for a high quality factor load. Using this method with a low quality factor load, a ZVS area will be decreased as the duty cycle is adjusted for power control of load that leads to NONZVS operation condition. Then, the switching frequency is needed to be adjusted for ensuring ZVS operation. This paper describes the design of power control of a full-bridge series resonant inverter by using a variable-frequency asymmetrical voltage-cancellation control (VFVAC) scheme for induction cooking appliances. The proposed control strategy operates at slightly above the resonant frequency in order to obtain the ZVS operation condition for a low quality factor load in a wide range. As the result, this proposed control strategy improves the efficiency of inverter for induction cooking. Moreover, the control is simple and does not require the phase-locked loop control as proposed in [13].

Principle of induction cooking

Fig. 1: The block diagram of induction cooking appliance Fig. 1 shows the main block diagram of induction cooking. Induction coil-pan takes the energy from the main power source. The AC voltage is rectified by the uncontrolled rectifier of four diodes while it is filtered by the DC link capacitor and fed to the inverter. Induction coil is received a high-frequency current from the inverter. This high-frequency current induces an alternating magnetic field that induces eddy current and causes hysteresis effect heating up the food in the pan. Usually, the pan must be made of the ferromagnetic metals because the efficiency of the electromagnetic coupling of these is higher than the non-ferromagnetic metals. The induction coil-pan of the induction cooking is modeled as an equivalent inductor Leq and resistor Req in series connection. Generally, the variation of the equivalent loads depends on various parameters including the different pan materials, spacing between pan and induction coil, excitation frequency and temperature. It is necessary to analyze the load characteristics of the induction cooking system, so the different loads can be classified by its quality factor (Q) and the angular resonant frequency (r) with load characteristics is determined by the resonant capacitor Cr and Leq, respectively.

Q =

r Leq
Req
1 Leq Cr

Leq Cr Req

(1)

r =

(2)

Circuit description and operation


A. Circuit description
Fig. 2 shows a schematic diagram of a full-bridge series resonant inverter for induction cooking. The schematic diagram comprises a DC-link capacitor, four switches with antiparallel diodes using IGBTs, and a series resonant circuit load that represents a resonant capacitor (Cr) and an equivalent load Req-Leq. The stray capacitance of switching device S1, S2, S3 and S4 are noted as CCoss (C1, C2, C3 and C4). Moreover, the voltage vo and current io are the output voltage and output current, respectively.

S1

D1

C1

S3

D3

C3

VDC
S2

io

Leq

Req Cr

vo
D2
C2

S4

D4

C4

Fig. 2: Full-bridge series resonant inverter


TS td

td

S1 S2 S3 S4

tc

I D1
I D2 I D3 I D4 iC1

iC 2 iC 3 iC 4 iS 1

iS 2 , iS 3
iS 4 vo vo1 io
v1

VDC

i1
A B C

F G

t1 t0 t0

t2 t2

t4 t3 t3

t5

Fig. 3: Typical waveforms of VFVAC strategy

S1

D1

C1

S3 Req Cr vo S4

D3

C3

S1

D1

C1

S3

D3

C3

VDC
S2
D2

Leq io
C2

VDC
D4 C4

Leq io S2
D2 C2

Req Cr
vo S4
D4 C4

) Mode A (t0 t0

t3 ) Mode E (t2

S1

D1

C1

S3

D3

C3

S1

D1

C1

S3 Req Cr vo S4

D3

C3

VDC
S2
D2

Leq
io
C2

Req Cr
vo S4
D4 C4

VDC
S2
D2

Leq io
C2

D4

C4

t1 ) Mode B (t0

) Mode F (t3 t3

S1

D1

C1

S3
Req Cr

D3

C3

S1

D1

C1

S3
Req Cr

D3

C3

VDC
S2
D2

Leq

io
C2

vo S4
D4 C4

VDC
S2
D2

Leq

io
C2

vo S4
D4 C4

ModeC (t1 t2 )

t4 ) ModeG (t3

S1

D1

C1

S3
Req Cr
vo

D3

C3

S1

D1

C1

S3
Req Cr vo

D3

C3

VDC
S2
D2

Leq
io
C2

VDC
D4 C4

Leq io

S4

S2

D2

C2

S4

D4

C4

) Mode D (t2 t2
Fig.4. Operation modes of VFAVC strategy
B: Modes of operation

Mode H (t4 t5 )

Fig. 3 and 4 show the typical waveforms and the eight operation modes of the full-bridge series resonant inverter in the case of inductive load for the operating frequency higher than the resonant frequency as follows.

1) Mode A (t0-t'0): When the switches S2 and S3 are turned off. The switches S1 and S4 are still maintained OFF due to the dead time td. While the negative current io flows through stray capacitors C1, C2, C3 and C4. The stray capacitors C2 and C3 are charged by the Leq-Cr resonant circuit while the stray capacitors C1 and C4 are discharged. Consequently, the output voltage vo gradually increases from -VDC to +VDC. 2) Mode B (t'0t1): At t = t'0, the switches S2 and S3 are already turned off. The voltage across the diodes D1 and D4 reaches -0.7V, both diodes turn on, and the negative current io is diverted from the stray capacitors C1 and C4 to the diodes D1 and D4. After the switch dead time, the switches S1 and S4 receive a positive gating signal and the ZVS operation is achieved. 3) Mode C (t1t2): At t = t1, when the antiparallel diodes D1 and D4 are off, the switches S1 and S4 conduct and receive a positive gating signals. During this mode, the positive current io flows. 4) Mode D (t2t'2): At t = t2, while the switch S1 still conducts, the switch S4 is turned off due to the phase angle that is adjusted to control the output power. During this mode, the current io flows in the same direction. The stray capacitor C4 is charged while the stray capacitor C3 is discharged. At this stage the output voltage decreased to zero. 5) Mode E (t'2t3): At t = t'2, the switch S1 still conducts while the switch S4 is turned off and the antiparallel diode D3 conducts. During this mode, the positive current io flows. 6) Mode F (t3t'3): During this period, all switches are off simultaneously. At the same time, the charge in the stay capacitor C1 increases whereas the charge in the stay capacitor C2 decreases. Consequently, the current io flows through the antiparallel diode D3 and C2, and the output voltage vo gradually changes from zero to -VDC. 7) Mode G (t'3t4): At t = t'3, the switch S1 is already turned off. The antiparallel diode D3 still conducts whereas the diode D2 starts conducting the positive current io. After the switch dead time, the switches S2 and S3 receive a positive gating signal. At this stage the output voltage vo is equal -VDC. 8) Mode H (t4t5): At t = t4, as soon as the antiparallel diodes D2 and D3 are off, the switches S2 and S3 conduct and receive a positive gating signals. At this stage, both the output current io and voltage vo become negative and the ZVS operation is achieved during this mode. The next operating cycle continues to repeat from modes A to H.

Proposed control algorithm and analysis


The proposed control algorithm is implemented on a DSPIC controller to generate a high-frequency signal for gate drivers based on asymmetrical voltage-cancellation control with a variable-frequency control. The desired output power of inverter can be controlled by variation of the phase angle () through the switch S4 and the period TS of switches, as shown in Fig. 3. For the case of practical switching device of CCoss, the switching frequency (fs) of inverter is operated slightly above the resonant frequency (fr) with the variation of the period TS of all switches to still maintain the operation conditions of zero-voltage-switching (ZVS) by making a complete charging process of CCoss before the next-coming turn-on time of switches [15]. Therefore, the losses of switches are decreased. The output current waveform of inverter is a sinusoidal while the output voltage is a square wave because those Cr and Leq act as a low-pass filter. Therefore, the fundamental (first) harmonic average output power of inverter in steady state can be calculated by the following Fourier series [12], [14] as
2 = I oh , rm s Req h =1

P =

2 Req V oh 2 h =1 2 Z eq

2 VDC (5 + 3cos ) 2 2 Req 1 2 1 + Q n n

(3)

where VDC is the DC input voltage source

n =

s (the normalized switching frequency) r


2

Z eq = Req 1 + Q 2 s r r s

= VDC 10 + 6cos V 01

The phase of the fundamental (first) frequency of the output voltage (v1) is given by

v1 = tan 1

sin 3 + cos

(4)

The phase angle () can be defined as

= tan 1 Q n

1 n

(5)

To achieve the operating condition of ZVS, the switching frequency (fs) must operate higher than the resonant frequency (fr) and correspond a function as (i1 = v1 ) > 0 Therefore, we get
sin + 4Q 2 (3 + cos ) 2 + sin 2 2Q (3 + cos )

n =

(6)

1.2 Normalized Switching Frequency 1.15 1.1 1.05 1 0 Q=1 Q=4

30

60 90 120 Phase Angle, (degree)

150

180

Fig. 5: The phase angle () vs. the normalized switching frequency (n) with different quality factors Fig. 5 shows the normalized switching frequency (n) as a function of the controlled phase angle () with different Q factor of loads. In the case of high Q factor load, the normalized switching frequency (n) is almost unchanged as the controlled phase angle () changes. As a result, the fixed-frequency method is sufficient for output power control of inverter. On the contrary for the low Q factor load, as the output power is reduced, the normalized switching frequency will be increased from 1 until it SSSS

reaches the maximum then it will be decreased back to 1. If the fixed-frequency control is used in this case, the ZVS areas between the output current and voltage of inverter during the adjusting power control are lost and cause the NON-ZVS condition. The efficiency of inverter will be decreased. Thus, in the case of the low Q factor load, the switching frequency must be controlled to be higher than above the curve in Fig. 5 in order to obtain the ZVS condition at any power level.

Simulation and experimental results


A computer simulation and a hardware experiment are performed to confirm the validity of the proposed control strategy using parameters in Table I. This is an attempt to concentrate on the accomplishment of the proposed control strategy in the full-bridge series resonant inverter under operating conditions of ZVS. The operation control of all switches has been implemented in hardware using DSPIC controller (Digital Signal Peripheral Interface Controller). The induction coil consists of 28 litz wire and 26 turns. The calculated resonant frequency using (1) is 26.5 kHz. As a result, the Q factor of the load is 1.03. The phase angle () is varied from 0 to 150 for the purpose of output power control. With the proposed control, the output power can be controlled by varying the phase angle () from 0 to 150 while the switching frequency (fs) will be adjusted higher than the resonant frequency (fr) by varying the switching period Ts in the whole power range, and must be controlled above the load characteristic curve in Fig. 5 in order to operate under the ZVS condition. The simulation results under output power control from full load to light load with a variation of the phase angle () for = 0 operating at 30 kHz, = 90 operating at 39 kHz and = 150 operating at 50 kHz are shown in Fig. 6(a), (b) and (c), respectively. As the phase angle () increases, the inverter output voltage vo and output current io decrease. As a result, the output power of inverter is decreased. The experimental results are shown in Fig. 7 as the same set of simulation parameters in Table I. Fig. 7(a) shows the vo, io ,vs4 and is4 waveforms of inverter at full load condition with the output power of 1.2 kW at = 0, where the inverter operates at a switching frequency of 30 kHz. This stage is to ensure the ZVS operation with the efficiency of inverter of 91%. When the phase angle () is also adjusted to = 90 to reduce the output power to 45% load at 39 kHz, the output voltage and current waveforms are shown in Fig. 7(b) through a change of switches S4. In Fig. 7(c), while the phase angle () is adjusted to = 150, the vo, io ,vs4 and is4 waveforms of inverter are obtained. As a result, the output power is reduced to 27%. The switching frequency (fs) will be also adjusted to 50 kHz to maintain the phase angle of i1. In order to obtain the ZVS condition, the phase angle (i1) is not lost when the output power reduces. Therefore, the switching frequency (fs) of inverter must be adjusted to operate above the load characteristic curve as shown in Fig. 6(b), 6(c), 7(b) and 7(c).

Table I: Parameter and inverter specifications


Parameter Value

VDC fr Cr Leq Req S1 - S4

140V 26.5kHz 470nF 72H 12 IGBT IRG4PH40UD

200 100 0 -100 -200 220us

vo io

200 150 100 50 0 -50

vs 4

is 4

240us

260us

Time

280us

300us

320us

-100 220us

240us

260us Time

280us

300us

320us

(a)
200 100

vo io

200 150 100 50 0

vs 4 is 4

-100

-50 -100 220us

-200 220us

240us

260us Time

280us

300us

320us

240us

260us

Time

280us

300us

320us

(b)
200 100

vo io

200 150 100 50 0 -50

vs 4

0 -100

is 4
240us 260us Time 280us 300us 320us

-200 220us

240us

260us Time

280us

300us

320us

-100 220us

(c)
\

Fig. 6: Simulated results of the proposed control strategy (a) vo, io ,vs4 and is4 waveforms at the full load with fs = 30kHz (vo: 100V/div, io: 10A/div, vs4: 50V/div, is4: 5A/div, and Time:10s/div.) (b) vo, io ,vs4 and is4 waveforms at 45% load with fs = 39kHz (vo: 100V/div, io: 10A/div, vs4: 50V/div, is4: 5A/div, and Time: 10s/div.), and (c) vo, io ,vs4 and is4 waveforms at 27% load with fs = 50kHz (vo: 100V/div, io: 10A/div, vs4: 50V/div, is4: 5A/div, and Time: 10s/div.)

Conclusion
A variable-frequency asymmetrical voltage-cancellation control (VFVAC) strategy with the fullbridge series resonant inverter has been presented in this paper. The proposed control system operates under operation condition of ZVS which is a new choice to increase the overall efficiency and performance of inverter in the induction cooking with the low Q factor. The analytical expression of the output power as a function of the variable phase angle is given in this work. Based on the derived expression, this proposed control strategy is proper to control the output power for the induction cooking appliances owing to its safety, high efficiency and performance.

vo

io vs 4

is 4

(a)

vo io vs 4

is 4

(b)

vo io vs 4

is 4

(c) Fig. 7: Experimental results of the proposed control strategy (a) vo, io ,vs1 and is1 waveforms at the full load with fs = 30kHz (vo: 50V/div, io: 5A/div, vs1: 100V/div, is1: 10A/div, and Time: 10s/div.) (b) vo, io ,vs1 and is1 waveforms at 45% load with fs = 39kHz (vo: 50V/div, io: 5A/div, vs1: 100V/div, is1: 10A/div, and Time: 10s/div.), and (c) vo, io ,vs1 and is1 waveforms at 27% load with fs = 50kHz (vo: 50V/div, io: 5A/div, vs1: 100V/div, is1: 10A/div, and Time: 10s/div.)

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