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11002 GS2
Slide
Class Objective
When you finish this class you will:
Understand the basics of the inner workings of a PIC16 Understand most instructions Understand memory organization Understand how to write simple programs
2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 2
Agenda
O O O O O
Architecture Basics Instruction Set Overview Memory Organization and Addressing Modes Special Features Hands-on Exercises
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Architecture
O
The high performance of the PIC microcontroller can be attributed to the following architectural features:
Harvard Architecture Instruction Pipelining Large Register File Single Cycle Instructions Single Word Instructions Long Word Instructions Reduced Instruction Set Orthogonal Instruction Set
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Harvard Architecture
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Harvard Architecture:
Uses two separate memory spaces for program instructions and data Improved operating bandwidth Allows for different bus widths
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Instruction Pipelining
O
Instruction Cycles
T2 T3 T4
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T5
T6
T7
Time to execute normal instruction Time to execute call instruction includes pipeline flush
Fetch
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Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
movlw 0x05
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0 Fetch
Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
movwf REG1
movlw 0x05
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
call SUB1
movwf REG1
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T2
Time to execute normal instruction
Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
addwf REG2
call SUB1
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T2
T3
Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
movf PORTB,w
call SUB1
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T2
T3
T4
Fetch
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Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
return
movf PORTB,w
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T2
T3
T4
T5
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Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
movf PORTC,w
return
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T2
T3
T4
T5
T6
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13
Instruction Pipelining
Pre-Fetched Instruction Executing Instruction
addwf REG2
return
Instruction Cycles
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T2
T3
T4
T5
T6
T7
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ldaa #k
1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 k k k k k k k k k k k k k k k k
movlw k
1 1 1 1 0 0 0 0 0 0 0 0 k k k k k k k k k k k k k k k k
O O
2007 Microchip Technology Incorporated. All Rights Reserved.
ALU
Data Bus Bus Data
Register File Concept: All of data memory is part of the register file, so any location in data memory may be operated on directly All peripherals are mapped into data memory as a series of registers Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location The Long Word Instruction format allows a directly addressable register file
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W W
10h
Opcode d Opcode d
Address Address
Address of Second Source Operand
Result Destination
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Bit Bit Oriented Oriented Operations Operations f,b f,b Bit Bit Clear Clear ff f,b f,b f,b f,b Bit Bit Set Set ff Bit Bit Test Test f, f, Skip Skip if if Clear Clear
f,b f,b Bit Bit Test Test f, f, Skip Skip if if Set Set Literal Literal and and Control Control Operations Operations k k k k k k -k k k k k k -k k --k k k k Add Add literal literal and and W W AND AND literal literal with with W W Call Call subroutine subroutine Clear Clear Watchdog Watchdog Timer Timer Go Go to to address address Inclusive Inclusive OR OR literal literal with with W W Move Move literal literal to to W W Return Return from from interrupt interrupt Return Return with with literal literal in in W W Return Return from from Subroutine Subroutine Go Go into into standby standby mode mode Subtract Subtract W W from from literal literal Exclusive Exclusive OR OR literal literal with with W W
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0x0A ,
Literal Data from Instruction Word Data Bus Register File
Execute
Reset
Address
w d
ALU
FF FF FF 18 FF FF FF FF FF FF
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FF
W
Register
2007 Microchip Technology Incorporated. All Rights Reserved.
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh
STATUS 2 1 0
1 0 0
Z DC C
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SFR
SFR
10Fh 110h
SFR
18Fh 190h
SFR
01Fh 020h
09Fh 0A0h
128 Bytes
GPR 96 Bytes
GPR 80 Bytes
GPR 96 Bytes
GPR 96 Bytes
16Fh
1EFh
17Fh
1FFh
Bank 0
2007 Microchip Technology Incorporated. All Rights Reserved.
11002 GS2
STATUS Register
IRP IRP
bit 7
RP1 RP1
RP0 RP0
TO TO
PD PD
Z Z
DC DC
C C
bit 0
Z: Zero bit
1 = Result of arithmetic operation is zero
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0 0
RP1 RP0
0 0 0 0 0 0 0
f Operand
0x183
Bank 3 FF FF FF FF FF FF 1C 1C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Register File Address Bus
Bank 0 00h 01h 02h 03h 04h 05h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh FF FF FF FF FF FF
Bank 1
Bank 2 FF FF FF FF FF FF 18 18 FF FF FF FF
Address
FF FF FF FF FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF FF FF FF FF
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F0
9-Bit Effective Address:
0 0 0 0
RP1 RP0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
7-bits from Instruction
FF FF FF FF FF FF 38 38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Bin Dec
FF FF FF FF FF FF 38 38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Hex
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0
IRP
0 0 0 0 0 0 0 0
FSR
0x1FC
Bank 0,1 000h 001h 002h 003h 004h 005h 0FAh 0FBh 0FCh 0FDh 0FEh 0FFh 100h 101h 102h 103h 104h 105h 1FAh 1FBh 1FCh 1FDh 1FEh 1FFh
Bank 2,3
FF FF FF FF FF FF 1C 1C FF FF FF FF
FF FF
FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF
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20
9-Bit Effective Address:
0 0
IRP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FSR
00 00 FF FF FF FF 18 18 80 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF FF
00h : INDF 01h : TMR0 02h : PCL 03h : STATUS 04h : FSR 20h 21h 22h 23h 7Dh 7Eh 7Fh 80h
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LOOP
bcf STATUS,IRP movlw 0x20 movwf FSR clrf INDF incf FSR,f btfss FSR,7 goto LOOP <next instruction>
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Program memory is divided into four 2k14 pages Required to maintain single word/single cycle execution Paging is only a concern when using the call or goto instructions, or when directly modifying the program counter
0000h 0004h
Page Page 0 0
PCH PCH = = 00h 00h 0800h
Page Page 1 1
PCH PCH = = 08h 08h
2k
1000h
Page Page 2 2
PCH PCH = = 10h 10h
2k
1800h
Page Page 3 3
PCH PCH = = 18h 18h 1FFFh
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2k
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Program Counter
PCH
12 11 10 9 8 7 6 5
PCL
4 3 2 1 0
Program Counter
O O O O O O
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
13-bit PC can access up to 213 = 8192 words Contains address of NEXT instruction (pipelining) Lower byte accessible in data memory as PCL Upper byte indirectly accessible via PCLATH Runs freely across page boundaries Events that modify PC out of sequence:
Interrupts Instructions: CALL, GOTO, RETURN, RETLW, RETFIE Any instruction that uses the PCL register as an operand
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PC Absolute Addressing
CALL and GOTO Instructions:
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode Opcode
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
PC Absolute Addressing
14-Bit CALL or GOTO Instruction in Program Memory
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 PCH PCH
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
PCL PCL
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PC Absolute Addressing
Example: Jumping to code located in a different program memory page. PCLATH Register
7 6 5 4 3 2 1 0
0 0
0 0
0 0
0 0
0 0
Opcode Opcode
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
W Register
FF
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
MySubroutine
org 0x0020 movlw HIGH MySubroutine movwf PCLATH call MySubroutine org 0x1250 <do something useful> return
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0020
0 1 2 3 4 5 6 7 13-bit x 8-Level Return Address Stack
MySub1
MySub2
MySub3 MySub4
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PC Relative Addressing
W Register
FF
8-bit Data Bus
To write to PC:
n Write high byte to PCLATH o Write low byte to PCL (PCH will be loaded with value from PCLATH)
PCLATH
FF
PCH PCL
FF
FF
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PIC MCU
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Configuration Word
CP CP bit 1 -DEBUG DEBUG WRT1 WRT1 WRT0 WRT0 CPD CPD LVP LVP BOREN BOREN --PWRTEN PWRTEN WDTEN WDTEN FOSC1 FOSC1 FOSC0 FOSC0 bit 0
Located in program memory space, outside the reach of the program counter Used to setup device options:
Code Protection Oscillator Mode Watchdog Timer Power Up Timer Brown Out Reset Low Voltage Programming Flash Program Memory Write
Standard Standard frequency frequency crystal crystal oscillator oscillator High High frequency frequency crystal crystal oscillator oscillator Low Low frequency frequency crystal crystal oscillator oscillator External External RC RC oscillator oscillator Internal Internal RC RC oscillator oscillator
100kHz 100kHz - 4MHz 4MHz 4MHz 4MHz - 20MHz 20MHz 5kHz 5kHz - 200kHz 200kHz DC DC - 4MHz 4MHz 4 4 or or 8 8 MHz MHz 2% 2%
Sleep Mode
O
The processor can be put into a power-down mode by executing the SLEEP instruction
System oscillator is stopped Processor status is maintained (static design) Watchdog timer continues to run, if enabled Minimal supply current is drawn - mostly due to leakage (0.1 2.0A typical)
Events Events that that wake wake processor processor from from sleep sleep
MCLR MCLR WDT WDT INT INT TMR1 TMR1 ADC ADC CMP CMP Master Master Clear Clear Pin Pin Asserted Asserted (pulled (pulled low) low) Watchdog Watchdog Timer Timer Timeout Timeout INT INT Pin Pin Interrupt Interrupt Timer Timer 1 1 Interrupt Interrupt (or (or also also TMR3 TMR3 on on PIC18) PIC18) A/D A/D Conversion Conversion Complete Complete Interrupt Interrupt Comparator Comparator Output Output Change Change Interrupt Interrupt
CCP Input CCP Input Capture Capture Event Event PORTB PORTB PORTB PORTB Interrupt Interrupt on on Change Change 2 SSP Synchronous C SSP Synchronous Serial Serial Port Port (I (I2 C Mode) Mode) Start Start // Stop Stop Bit Bit Detect Detect Interrupt Interrupt PSP PSP Parallel Parallel Slave Slave Port Port Read Read or or Write Write
11002 GS2 Slide 42 2007 Microchip Technology Incorporated. All Rights Reserved.
Watchdog Timer
O O O O O O O
Helps recover from software malfunction Uses its own free-running on-chip RC oscillator WDT is cleared by CLRWDT instruction Enabled WDT cannot be disabled by software WDT overflow resets the chip Programmable timeout period: 18ms to 3.0s typical Operates in SLEEP; on time out, wakes up CPU
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When voltage drops below a particular threshold, the device is held in reset Prevents erratic or unexpected operation Eliminates need for external BOR circuitry
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Configuration Option (set at program time) Cannot be enabled / disabled in software Four selectable BVDD trip points: 2.5V Minimum VDD for OTP PIC MCUs 2.7V 4.2V 4.5V
Holds PIC MCU in reset until ~72ms after VDD rises back above threshold
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LVDIF
Internal VREF
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Only two pins required for programming Convenient for In-System Programming of
Calibration Data Serialization Data
Function Function Programming Programming Voltage Voltage = = 13V 13V Supply Supply Voltage Voltage Ground Ground Clock Clock Input Input Data Data I/O I/O & & Command Command Input Input
MCLR/VPP
To application circuit
Isolation circuits
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I/O Ports
O O O
High Drive Capability Can directly drive LEDs Direct, single cycle bit manipulation Each pin has individual direction control under software All pins have ESD protection diodes Pin RA4 is usually open drain All I/O pins default to inputs (high impedance) on startup All pins multiplexed with analog functions default to analog inputs on startup
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O O O
movwf PORTB
Write Operation
RB1
Read Operation
movf PORTB,w
2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 50
I/O Ports
Bit n in TRISx controls the data direction of Bit n in PORTx 1 = Input, 0 = Output
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Hands-on Exercises
2007 Microchip Technology Incorporated. All Rights Reserved.
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MPLAB ICD2
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RESET_V RESET_V
org org 0x0004 0x0004 retfie retfie {Begin {Begin your your code code here} here} END END
O O
If not using interrupts, lines 8 and 9 could be omitted The labels in the left column may be anything you want; these are just examples
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By default, MPASM assembler expects numbers in hexadecimal Default can be changed through IDE or by adding r=hex or r=dec as a parameter to the LIST directive:
LIST LIST p=16f877a, p=16f877a, r=dec r=dec
Good programming practice suggests that a numbers radix be specified explicitly: Radix MPASM Syntax
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1 Instruction
Load number into W
4 Instructions
Move value to TRISB
1 Instruction
Switch to Bank 0
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Lab 1: Template
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Lab 1: Solution
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Lab 1: Results
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A delay is required to make the blinking slow enough for the human eye At 4MHz, one instruction executes in 1s A 16-bit software counter is sufficient to implement the delay
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Naming Registers/Constants
O
Equate Method: MyReg0 equ 0x20 MyReg1 equ 0x21 MyReg2 equ 0x23
Constant Block Method: CBLOCK 0x20 MyReg0 ;MyReg0 = 0x20 MyReg1: 2 ;MyReg1 = 0x21 MyReg2 ;MyReg2 = 0x23 ENDC
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1 Instruction
1 Instruction
1 Instruction
2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 66
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Lab 2: Results
O
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Using one of the rotate instructions, move the illuminated LED across the lower 4 bits of PORTB. When it reaches one side, send it back to the start.
RB3 RB2 RB1 RB0
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Rember: The rotate instructions operate on 9-bits, with the Carry bit in the STATUS register as the 9th bit
1 Instruction
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Lab 3: Results
O
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Same as Lab 3, but this time make the direction of rotation change when the LED is rotated to either end
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Setup PORTB
bsf STATUS,C
1 Instruction 1 Instruction Subroutine Call
No
Delay
RB3 = 1?
Yes
Rotate Right PORTB
Delay
No
RB0 = 1?
Yes
Slide 80
Lab 4: Template
O
RIGHT RIGHT
DELAY DELAY
decfsz decfsz goto goto decfsz decfsz goto goto return return END END
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Lab 4: Solution
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Lab 4: Results
O
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3 Instructions
1 Instruction
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;Reset ;Reset Vector Vector ;Clear ;Clear PORTB PORTB output output latches latches ;Switch ;Switch to to bank bank 1 1 ;Load value to make ;Load value to make lower lower 4 4 bits bits outputs outputs ;Move value to TRISB ;Move value to TRISB ;Switch ;Switch to to bank bank 0 0 ;Clear ;Clear index index into into table table ;Load ;Load W W with with high high byte byte of of TABLE TABLE address address ;Move ;Move W W to to PCLATH PCLATH
clrf PORTB clrf PORTB bsf STATUS,RP0 bsf STATUS,RP0 movlw b11110000' movlw b11110000' movwf TRISB movwf TRISB bcf STATUS,RP0 bcf STATUS,RP0 st st {1 Instruction} {1 Instruction} nd nd {2 Instruction} {2 Instruction} rd rd {3 Instruction} {3 Instruction}
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;Reset ;Reset Vector Vector ;Clear ;Clear PORTB PORTB output output latches latches ;Switch to bank 1 ;Switch to bank 1 ;Load ;Load value value to to make make lower lower 4 4 bits bits outputs outputs ;Move ;Move value value to to TRISB TRISB ;Switch ;Switch to to bank bank 0 0 ;Clear ;Clear index index into into table table ;Load W with high byte ;Load W with high byte of of TABLE TABLE address address ;Move ;Move W W to to PCLATH PCLATH
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Lab 5: Results
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Summary
O O O O
PIC16 Architecture PIC16 Instruction Set PIC16 Memory Organization Simple Programming Techniques
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References
O
PIC MCU Mid-Range Family Reference Manual (DS33023A) Microchip Technology Programming and Customizing PICmicro Microcontrollers by Myke Predko Design with PIC Microcontrollers by John B. Peatman
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References
O
123 PIC Microcontroller Experiments for the Evil Genius by Myke Predko
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Thank You
2007 Microchip Technology Incorporated. All Rights Reserved.
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, KeeLoq logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies.
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