CH 01

Chapter 1 VLSI Design Methods
Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan
Outline
Introduction VLSI Design Flows & Design Verification VLSI Design Styles System-on-Chip Design Methodology
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
Complexity & Productivity Growth of ICs

Complexity grows 58%/yr (doubles every 18 mos) Productivity grows 21%/yr (doubles every 31/2 yrs) unless methodology is updated
Complexity and Productivity Growth
10,000,000 Com plexity C om ple xity Tra ns istors per C hip (K ) Produc tiv ity Tra ns is tors /Sta ff M onth 1,000,000 100,000 10,000 1,000 100 10 1980
100,000,000 Productivity 10,000,000 1,000,000 100,000 10,000 1,000 100 1985 1990 1995 2000 2005 2010
[Source: MITRE]
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Jin-Fu Li, EE, NCU
VLSI Design Methodologies

Design methodology Process for creating a design Methodology goals Design cycle Complexity Performance Reuse Reliability
Jin-Fu Li, EE, NCU
IC Community
Design rules
Silicon foundry
Simulation models and parameters Mask layouts Integrated circuits
IC design
CAD
Process information
tool provider
Software tools
[M. M. Vai, VLSI design]
Jin-Fu Li, EE, NCU
System to Silicon Design

System Requirements Algorithm X[k] = x[n]e-j2 k/N x[n] = X[k]e+j2 k/N Hardware Architecture Synthesis
System Integration
Fabricate and Test
Physical
Design For Test

Observe
Co nt ro l
[Source: MITRE]
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Y-Chart
Structural Domain
Processor Register ALU Leaf Cell Transistor FSM Module Description Boolean Equ.
Behavioral Domain
Algorithm
Mask Cell Placement
Module Placement Chip Floorplan
Physical Domain
VLSI Design Flow

Concept
Design Validation
Designer
Final Product Product Verification
Behavior Specification
Manufacturing
RTL Verification
Behavior Synthesis
Layout (Masks) Layout Verification
RTL Design
Layout Synthesis
Logic Verification
Logic Synthesis
Netlist (Logic Gates)
Jin-Fu Li, EE, NCU
Behavioral Synthesis & RTL Synthesis

4 cycles=16 ns
Behavioral Synthesis
Vary clock period 3 cycles=15 ns
HDL
z = a(i) b(i) c d (k ) + f
Vary # clock cycles
2 cycles=20 ns
Multiple Architectures
RTL Synthesis
Vary clock period 1 clock cycle 1 cycle=50 ns
Single Architecture
Source: Synopsys
Behavioral Synthesis (Resource Allocation)

Source code defines the functionality
y_real := a_real * b_real - a_imag * b_imag y_imag := a_real * b_imag + a_imag * b_real
Constraints allow designer to explore different architectures, trading off speed vs. area Two possible implementations for a complex multiplier:
Fast, but large (4 mult, 1 add, 1 sub)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU
Small, but slow (1 mult, 1 add/sub)

[Source: MITRE]
10
Behavioral Synthesis (Retiming)

Allows designer to trade off latency for throughput by adding and moving registers in order to meet timing constraints Specification needs to include registers at functional boundaries, without regard to register-to-register timing: software takes care of optimizing register placement
Compiled Functional Description Circuit After Behavioral Retiming
> create_clock clk -period 10 > pipeline_design -stages 3 > optimize_registers register tp = 0.5
tp=5
tp=8.7
tp=23.0
tp=9.5
Max. Speed= 1/23.0 nSec = 43 MHz Latency = 1 clock cycle
Max. Speed= 1/10 nSec = 100 MHz Latency

Jin-Fu Li, EE, NCU
= 3 clock cycles
[Source: MITRE]
11
Verification
The four representations of the design
Behavioral, RTL, gate level, and layout
In mapping the design from one phase to another, it is likely that some errors are produced
Caused by the CAD tools or human mishandling of the tools
Usually, simulation is used for verification, although more recently, formal verification has been gaining in importance Two types of simulations are used to verify the design
Functional simulation & timing simulation
Jin-Fu Li, EE, NCU
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DFT Flow
Behavioral Description Behavioral DFT Synthesis RTL Description Logic DFT Synthesis Gate Description Test Pattern Generation Low Fault Coverage ? High Good Product
Gate Technology Mapping Layout Parameter Extraction Manufacturing Product Test Application
Design Styles Full Custom

A B Z
Vss z
Vdd
Jin-Fu Li, EE, NCU
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Design Styles Programmable Logic Array

AND array OR array
Buffering Inputs
Buffering Outputs
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Design Styles Gate Array

Cell 1 Cell 2 Cell 3 Cell 4 Cell 5 Cell 6 Cell 7 Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
Cell 13
Cell 14
Cell 15
Cell 16
Cell 17
Cell 18
Cell 19
Cell 20
Cell 21
Cell 22
Cell 23
Cell 24
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Jin-Fu Li, EE, NCU
Design Styles Field Programmable Gate Array (FPGA)

Xilinx SRAM-based FPGA
Configurable Logic Block (CLB) I/O Block Routing channel
Jin-Fu Li, EE, NCU
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Xilinx XC4000 Configurable logic block
Jin-Fu Li, EE, NCU
18

SRAM-based programmable switch
Jin-Fu Li, EE, NCU
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Architecture of Altera FLEX 10K FPGA
FastTrack Interconnect
I/O I/O I/O I/O
EAB
I/O I/O Embedded Array Block I/O I/O
I/O I/O
Logic Array Block (LAB)
EAB
I/O I/O
Jin-Fu Li, EE, NCU
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Logic array block
Jin-Fu Li, EE, NCU
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Standard-Cell Design Styles

Cell 1 Cell 2 Cell 3 Cell 4 Cell 5
Cell 6
Cell 7
Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
Cell 13
Cell 14
Cell 15
Cell 16
Cell 17
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Jin-Fu Li, EE, NCU
Standard-Cell Design Styles

Design entry
Enter the design into an ASIC design system, either using a hardware description language (HDL) or schematic entry
An example of Verilog HDL

module fadder(sum,cout,a,b,ci); output sum, cout; input a, b, ci; reg sum, cout; always @(a or b or ci) begin sum = a^b^ci; cout = (a&b)|(b&ci)|(ci&a); end endmodule
ci
fadder
cout
sum
23
Design Styles Comparison

Design Styles Full-custom Advantages - Compact designs; - Improved electrical characteristics; -Well-tested standard cells which can be shared between users; -Good for bottom-up design; -Fast implementation; -Easy updates; Disadvantages - Very time consuming; - More error prone;
Semi-custom
-Can be time consuming to built-up standard cells; -Expensive in the short term but cheaper in long-term costs; -Can be wasteful of space and pin connections; -Relatively expensive in large volumes;
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FPGA
Jin-Fu Li, EE, NCU
Emergence of SOC Idea

Motivation:
Transistor density Moor's law
Integration with analog parts

AMS specification, synthesis, simulation
SoC Design Methodology and Tools

Filling the Gap through
Reuse Design Automation System Specification Methodology
Source: Synopsys
Jin-Fu Li, EE, NCU
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Whats a System?
System
[Source: M. Gudarzi]
Whats a System?
Customers view: System = User/Customer-specified functionality + requirements in terms of: Cost, Speed, Power, Dimensions, Weight,
Designers view: System = HW components +SW modules
Hierarchical Design Flow for an System Chip
Specification Hardware Architecture Detail Design
Requirements and specification Architecture Hardware Design Software Design
Specification Software Architecture Module Design
Integration Test
Integration System test
Integration Test
Jin-Fu Li, EE, NCU
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HDLs & SDLs: Requirements

HDLs HardwareC Verilog AHDL VHDL
SDLs
C Pascal ADA
HDLs & SDLs: Realization

Hardware Program Software Program
Compilation Synthesis
Operating System
HDLs & SDLs: Features

Any SW-realizable algorithm is HW-realizable as well.
Hardware Realization
Speed Energy Efficiency Cost Efficiency (in high volumes)
Software Realization
Flexibility Ease of Development Ease of Test and Debug Cost = SW + Processor
Jin-Fu Li, EE, NCU
31
HW-SW Co-design
How much SW + how much HW? Objectives:
Power Speed Area Memory space Time-to-market
Implementation platform:
Collection of chips on a board (MCM)
Jin-Fu Li, EE, NCU
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HW/SW Co-Design Methodology

Must architect hardware and software together:
provide sufficient resources; avoid software bottlenecks.
Can build pieces somewhat independently, but integration is major step. Also requires bottom-up feedback
Jin-Fu Li, EE, NCU
33
HW/SW Co-design Main Topics

Synthesis
System
System
OS Specification Verification
System Specification
Verification
Co-Synthesis
Partitioning HW Parameter Estimation SW Parameter Estimation Verification
HW Synthesis ASIC
SW Synthesis
Verification
OS EXE Code
Verification
System Integration Jin-Fu Li, EE, NCU
Final Verification
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SOC Design Essentials

Realization strategy:
Automated HW-SW Co-design + Reusable Cores Intellectual Property: IP Cores
IP Core Examples:
Processors: PowerPC, 680x0, ARM, Controllers: PCI, DSP Processors: TI ...
IP Core Categories:
Soft Cores: HDL, SW/HW Cores Firm Cores: Synthesized HDL Hard Cores: Layout for a specific fabrication process
Jin-Fu Li, EE, NCU
36
Trends and Challenges of SOC Designs

Technology trends
3D technology + System-in-package
Architecture trends
Regular architectures, e.g., multi-core architecture Network-on-chip communication
Challenges
Power Reliability Yield Design-for-manufacturability
Jin-Fu Li, EE, NCU
37

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Chapter 1 VLSI Design Methods

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Complexity & Productivity Growth of ICs

Jin-Fu Li, EE, NCU

VLSI Design Methodologies

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Simulation models and parameters Mask layouts Integrated circuits

[M. M. Vai, VLSI design]

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

System to Silicon Design

Fabricate and Test

Design For Test

Mask Cell Placement

Module Placement Chip Floorplan

VLSI Design Flow

Final Product Product Verification

Layout (Masks) Layout Verification

Netlist (Logic Gates)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Behavioral Synthesis & RTL Synthesis

Vary # clock cycles

Behavioral Synthesis (Resource Allocation)

Fast, but large (4 mult, 1 add, 1 sub)

Small, but slow (1 mult, 1 add/sub)

Behavioral Synthesis (Retiming)

Max. Speed= 1/23.0 nSec = 43 MHz Latency = 1 clock cycle

Max. Speed= 1/10 nSec = 100 MHz Latency

Advanced Reliable Systems (ARES) Lab.

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Full Custom

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Programmable Logic Array

Design Styles Gate Array

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Field Programmable Gate Array (FPGA)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Field Programmable Gate Array (FPGA)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Field Programmable Gate Array (FPGA)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Field Programmable Gate Array (FPGA)

Logic Array Block (LAB)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design Styles Field Programmable Gate Array (FPGA)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Standard-Cell Design Styles

Jin-Fu Li, EE, NCU

Standard-Cell Design Styles

An example of Verilog HDL

Design Styles Comparison

Advanced Reliable Systems (ARES) Lab.