Brief DSP overview

Basic DSP pardigm: A/D ----Processor ----D/A

Sometimes the A/D or the D/A might be present. What characterizes a DSP processor?

Typically the presence of a multiply and accumulate instruction. Actually, one can do DSP on any computer. Even those that only cost twenty-ve cents. One is always balancing cost versus performance.

CampCAEN Wireless Summer 2010

Page 1/9

Wednesday June 30, 2010

Hardware overview

The A/D converter operates at sample rates or upto 12.5 MHz. We normally operate it at much lower rates. Up to 16 channels are supported. Sampling of channels is sequential. The F28335 does not have any D/A converters, per se. It does have six high resolution pulse width modulators that can be used to emulate six D/A converters.

CampCAEN Wireless Summer 2010

Page 2/9

Wednesday June 30, 2010

A/D

Twelve-bit values. Twos complement. Input is centered around 1.5V (the virtual ground level). Input span is from 0 Volts to 3.0 Volts. Values are returned in a 16-bit word.

Low 12 bits. Values range from -2048 to +2047. Top most 12 bits. Values range from -32768 to 32767 but with the low 4 bits set to zero. This method means that if more bits were added programming scalings would not be signicantly aected. In DSP parlance, the values are 16-bits in Q15 form.

CampCAEN Wireless Summer 2010

Page 3/9

Wednesday June 30, 2010

D/A

Set pulse width to 128/150 microseconds. Can set the width in 150 picosecond steps. (pico = 1012 ). Could express as 0.15 nanosecond steps (nano = 109 ). (128/150 106 )/(0.15 109 = 5689) There are nominally 5689 distinguishable possible pulse widths. This is slightly more than 212 widths. Low pass ltering the pulses results in a DC output. Performance is about equivalent to a 12-bit D/A converter and depends on the low pass lter design. We use a second order LRC lter designed to have a low pass cuto frequency on the order of 20 kHz. The ltered output nominally ranges from 0 Volts (-2048) to 3.3 Volts (2047). Output values are in the top 12 bits (Q15).

CampCAEN Wireless Summer 2010

Page 4/9

Wednesday June 30, 2010

A/D and D/A support

Actual hardware support is somewhat involved. Dont really have time to delve into it. Have created basic support and starter code. Contained in SinGen project.

CampCAEN Wireless Summer 2010

Page 5/9

Wednesday June 30, 2010

SinGen prolog
//#include "DSP2833x_Device.h" //#include "DSP2833x_Examples.h" #include <stdio.h> #include <math.h> #include "MyDataTypes.h" #define EINT asm(" clrc INTM") #define ERTM asm(" clrc DBGM") #define FOREVER 1 void InitF28335(void); void InitAdcBasic(Uint32); void InitDacBasic(Uint32); void InitLedBlink(void); void InitEpwm6Clock(Uint16); int GetAdc(void); void PutDac(void); extern volatile int16 AdcReady, AdcIn0, AdcIn1; extern volatile int16 DacReady, DacOut0, DacOut1, DacOut2, DacOut3, DacOut4, DacOut5; #define N 256 #define FS 10000 int SinTable[N]; // Peripheral address definitions // Defines lots of things that are useful

CampCAEN Wireless Summer 2010

Page 6/9

Wednesday June 30, 2010

SinGen main
void main(void) { unsigned int ctr, index, step, FTV, f; float pi=3.14159265; InitF28335(); InitAdcBasic(FS); // Set adc InitDacBasic(FS); // Set dac //InitEpwm6Clock(1000); // Set InitLedBlink(); // Blink

sample clock in Hz (nominally) sample clock in Hz (nominally) Epwm6 raw output for fc = 1000 kHz (nominally) LED to show program is alive

// Enable global Interrupts and higher priority real-time debug events: EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM for (ctr = 0; ctr < N; ctr++) { SinTable[ctr] = 20000.0; } DacReady = 0; while(FOREVER) { while (DacReady==0); DacOut0 = AdcIn0; DacOut1 = AdcIn1; DacReady = 0; } }

CampCAEN Wireless Summer 2010

Page 7/9

Wednesday June 30, 2010

Comments

We will be restricting the A/D and D/A sample rates to be equal. Special programming techniques need to be used when they dier. This the starter for investigating A/D and D/A programming. The DAC timing and the ADC timing are synchronized. No need to check individually. Will use the DAC ready ag. Operates using interrupts. Values come and go apparently magically. The DacReady synchronizes the code with the magic.

CampCAEN Wireless Summer 2010

Page 8/9

Wednesday June 30, 2010

Overview of the exercises

Testing out the SinGen program using signal generator input, DAC output. Investigate aliasing. Do simple sine table waveform generator. Stepping the simple generator to create higher output frequencies. Tunable direct digital sine wave generator. The concept of the frequency tuning variable. Generates a wider range of frequencies.

CampCAEN Wireless Summer 2010

Page 9/9

Wednesday June 30, 2010