ES4008

Home Theater Digital Audio Processor

ESS Technology, Inc. Data Sheet

DESCRIPTION FEATURES
The ES4008 home theater digital audio processor is a • Single-chip digital audio processor.
single-chip digital audio decoder for audio stream data • 6.1-channel audio outputs.
processing to provide 6.1 channel high-quality analog
audio output and digital audio output for A/V receiver and
• Integrated high-speed I2S serial bitstream interface.
other audio-decoder applications. • Dolby Digital (AC-3).
The ES4008 is built on the ESS proprietary dual CPU • Dolby Pro Logic.
Programmable Multimedia Processor (PMP) core • Dolby Pro Logic II.
consisting of 32-bit RISC and 64-bit DSP processors that
• Dolby Digital Surround EX.
enable simultaneous parallel execution of system
commands and data processing to perform specialized • DTS Surround.
audio decoding tasks. • DTS ES.
The ES4008 performs audio processing to provide • SRS TruSurround.
consumers with rich audio decode features, such as Dolby • High Definition Compatible Digital (HDCD) decoding.
Digital (AC-3), Dolby Pro Logic, Dolby Pro Logic-II,
Dolby Digital Surround EX, DTS Surround, DTS ES, • S/PDIF digital audio output.
SRS TruSurround, as well as bass management. • TDM interface for direct connection to external devices.
The ES4008 integrates an industry-standard serial • On-Screen-Display controller with 3-bit blending to
interface for audio input and output, using either the provide 256 colors display.
normal format or I2S format, to interface to audio DACs • Direct interface to SDRAM.
and ADCs. The ES4008 implements a high-speed,
bidirectional time-division-multiplexed (TDM) serial bus • Direct interface to EEPROM or flash memory.
interface that supports high-speed serial protocols. The • Bass management.
ES4008 also includes a S/PDIF interface to output high-
quality digital audio. LICENSING REQUIREMENTS
The ES4008 also includes an On-Screen-Display (OSD) • Dolby Laboratories, Inc.
controller to provide a user-friendly setup menu to enable
or modify the various audio decoding features. • Digital Theater Systems, Inc.
The ES4008 is available in an industry-standard 208-pin
• SRS Labs, Inc.
Plastic Quad Flat Pack (PQFP) device package.

ESS Technology, Inc. SAM0490-102902 1


CONTENTS
ES4008 PINOUT DIAGRAM .................................................. 3
ES4008 Pin DESCRIPTION ................................................... 4
ES4008 DEVICE INTERFACES ............................................ 7
LICENSING REQUIREMENTS ............................................ 10
FUNCTIONAL DESCRIPTION............................................. 11
Device Architecture ....................................................... 11
DMA Controller........................................................... 11
ESS RISC Processor ................................................. 11
Instruction Cache ...................................................... 12
Data Cache ............................................................... 12
Cache Line Operation ............................................... 12
RISC Interrupts ......................................................... 12
STALL# Flag Operation ............................................ 13
Gateway ..................................................................... 13
Huffman Decoder ....................................................... 13
On-Screen Display Controller .................................... 13
Transport Stream Parser ............................................ 13
Device Interfaces .......................................................... 13
Audio Interface ........................................................... 13
Audio Decoding Features........................................... 14
Dolby Digital (AC-3) Audio Decoding........................ 14
Dolby ProLogic and Pro Logic II ............................... 14
DTS Multi-Channel Decoding ................................... 14
DTS Surround ........................................................... 15
DTS Extended Surround (DTS-ES) .......................... 15
HDCD Decoding ....................................................... 15
SRS TruSurround ..................................................... 15
Private DMA Bus Interface......................................... 15
FIGURES
Figure 1 ES4008 Device Pinout ....................................... 3
Figure 2 ES4008 System Block Diagram ......................... 9
Figure 3 ES4008 Block Diagram .................................... 11
Figure 4 STALL# Flag Operation ................................... 13
Figure 5 Typical Dolby Digital AC-3 Sync
Audio Framing ............................................... 14
Figure 6 Right Justified Mode / 16-Bit Cycle Frame /
16-Bit Data Frame / MSB First ...................... 26
Figure 7 Right Justified Mode / 24-Bit Cycle Frame /
16-Bit Data Frame / MSB First ...................... 26
Figure 8 Right Justified Mode / 32-Bit Cycle Frame /
24-Bit Data Frame / LSB First ....................... 26
TABLES
Table 1 ES4008 Pin Description ..................................... 4
Table 2 ES4008 Device Interfaces ................................. 7
Table 3 ESS RISC Interrupts ........................................ 12
Table 4 Typical SDRAM Configurations ....................... 15
Table 5 SDRAM Configurations and Signal Pins .......... 16
Table 6 ROM Width Selection Options ......................... 21
2 SAM0490-102902
ES4008 DATA SHEET
CONTENTS
System SRAM Interface .............................................15
SDRAM Interface ........................................................15
SDRAM Address Mapping ........................................16
SDRAM Configuration Requirements ........................16
TDM Interface ............................................................. 16
Vacuum Fluorescent Display Controller Interface ......16
REGISTERS ......................................................................... 18
Host Interface Host Side Registers ............................... 18
On-Screen Display Controller Registers ........................19
Host Interface RISC Side Registers .............................. 21
Host Interface RISC-SRAM Interface Registers ............21
Bus Controller Registers ................................................22
Bus Controller (Memory Controller) Registers ............22
Audio Interface Registers ..............................................23
S/PDIF Interface Registers ......................................... 25
AUDIO INTERFACE TIMING ................................................26
SDRAM INTERFACE TIMING .............................................. 28
SRAM INTERFACE TIMING ................................................33
TDM INTERFACE TIMING ...................................................35
ELECTRICAL SPECIFICATIONS..........................................36
Absolute Maximum Ratings ...........................................36
Recommended Operating Conditions ...........................36
DC Electrical Characteristics .........................................36
AC Electrical Characteristics .........................................37
Device Clock Characteristics .........................................37
MECHANICAL DIMENSIONS ..............................................38
ORDERING INFORMATION ................................................40
Figure 9 Left Justified Mode / 32-Bit Cycle Frame /
24-Bit Data Frame / MSB First .......................27
Figure 10 I2S Mode ..........................................................27
Figure 11 SDRAM Random Column Read Timing ...........28
Figure 12 SDRAM Random Column Write Timing ............29
Figure 13 SDRAM Random Row Read Timing .................30
Figure 14 SDRAM Random Row Write Timing .................31
Figure 15 SRAM Read Timing ..........................................33
Figure 16 SRAM Write Timing ..........................................34
Figure 17 TDM Interface Timing .......................................35
Figure 18 Audio Master Clock and TDM Interface
Clock Timing ..................................................37
Figure 19 208-pin Plastic Quad Flat Package (PQFP) ..... 38
Table 7 Hex Values for Wait States ...............................21
Table 8 SDRAM Interface Timing ..................................32
Table 9 Operating AC Characteristics ...........................32
Table 10 DC Electrical Characteristics ............................36
Table 11 VFD Interface Characteristics ...........................37
ESS Technology, Inc.
ES4008 DATA SHEET
ES4008 PINOUT DIAGRAM

ES4008 PINOUT DIAGRAM

The device pinout for the ES4008 is shown in Figure 1. The
pound symbol (#) denotes an active-low signal.

AUX1[6]/VFD_DOUT
AUX2[0]/VFD_CLK
AUX1[7]/VFD_DIN

RESERVED

RESERVED
RESERVED
AUX2[7]/IR
AUX4[3]
AUX4[2]
AUX3[6]
AUX3[7]
AUX3[4]
AUX4[6]
AUX4[5]

AUX3[3]
AUX3[5]
AUX4[7]
AUX4[0]
AUX4[1]
AUX2[6]

AUX2[5]
AUX2[4]
AUX2[3]
AUX2[2]
AUX2[1]

AUX1[5]
AUX1[4]
AUX1[3]
AUX1[2]
AUX1[1]
AUX1[0]

AUX3[0]
AUX3[1]
AUX3[2]

ADVSS
ADVEE
COMP
VDAC

RSET

DCLK
VREF
VCC

VCC
VSS

VEE
VSS

VSS

VEE
VSS

VSS

NC
NC
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VEE 157 104 VEE
AUX4[4] 158 103 VSS
VEE 159 102 DSCK
I2CDATA/AUX[0] 160 101 DQM
I2C_CLK/AUX[1] 161 100 DCS0#
AUX[2] 162 99 VEE
VSS 163 98 VSS
VEE 164 97 DCS1#
AUX[3] 165 96 DB15
AUX[4] 166 95 DB14
AUX[5] 167 94 DB13
AUX[6] 168 93 DB12
AUX[7] 169 92 VEE
LOE# 170 91 VSS
VSS 171 90 DB11
VCC 172 89 DB10
LCS0# 173 88 DB9
LCS1# 174 87 DB8
LCS2# 175 86 DB7
LCS3# 176 85 DB6
VSS 177 84 VSS
LD0 178 83 VCC
LD1 179 82 DB5
LD2 180 81 DB4
LD3
LD4
181
182
ES4008F 80
79
DB3
DB2
VEE 183 78 DB1
VSS 184 77 DB0
LD5 185 76 VSS
LD6 186 75 VEE
LD7 187 74 DMBS1
LD8 188 73 DMBS0
LD9 189 72 DRAS#
LD10 190 71 DWE#
LD11 191 70 DOE#/DSCK_EN
VSS 192 69 DCAS#
VEE 193 68 VEE
LD12 194 67 VSS
LD13 195 66 DMA11
LD14 196 65 DMA10
LD15 197 64 DMA9
LWRLL# 198 63 DMA8
LWRHL# 199 62 DMA7
VSS 200 61 DMA6
VEE 201 60 VSS
NC 202 59 VEE
NC 203 58 DMA5
LA0 204 57 DMA4
LA1 205 56 DMA3
LA2 206 55 DMA2
LA3 207 54 DMA1
VSS 208 53 DMA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
VSS
VEE
TDMDX/RSEL

TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
AVSS
SPDIF/SEL_PLL3

Figure 1 ES4008 Device Pinout

ESS Technology, Inc. SAM0490-102902 3

 ES4008 DATA SHEET
ES4008 PIN DESCRIPTION

ES4008 PIN DESCRIPTION

Table 1 lists the pin descriptions for the ES4008. The
pound symbol (#) denotes an active-low signal.
Table 1 ES4008 Pin Description
Name Pin Numbers I/O Definition
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
VEE P I/O power supply.
148, 157, 159, 164,
183, 193, 201
2:7, 10:16, 19:23,
LA[21:0] O RISC port address bus.
204:207
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
VSS G Ground.
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
9, 35, 44, 83, 121,
VCC P Core power supply.
139, 172
RESET# 24 I Reset input (active-low).
TDMDX O TDM transmit data.
I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read during reset.
25 RSEL Selection
RSEL
0 16-bit ROM

1 8-bit ROM

TDMDR 28 I TDM receive data.

TDMCLK 29 I TDM clock.
TDMFS 30 I TDM frame sync.
TDMTSC# 31 O TDM output enable (active-low).
TWS O Audio transmit frame sync.
32
SEL_PLL2 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
TSD0 O Audio transmit serial data port 0.
33
SEL_PLL0 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
TSD1 O Audio transmit serial data port 1.
36
SEL_PLL1 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
TSD2 37 O Audio transmit serial data port 2.
TSD3 38 O Audio transmit serial data port 3.
42, 48, 115, 116,
NC — No connect.
202, 203
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 O Audio transmit bit clock.

4 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
ES4008 PIN DESCRIPTION

Table 1 ES4008 Pin Description (Continued)

Name Pin Numbers I/O Definition
SPDIF O S/PDIF output.
41
SEL_PLL3 I Pull down to ground via 4.7-kΩ resistor for proper operation; read during reset.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
XIN 49 I 27-MHz crystal input.
XOUT 50 O 27-MHz crystal output.
AVEE 51 I Analog power for PLL.
AVSS 52 G Analog ground for PLL.
DMA[11:0] 53:58, 61:66 O DRAM address bus.
DCAS# 69 O DRAM column address strobe (active-low).
DOE# O DRAM output enable.
70
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable (active-low).
DRAS# 72 O DRAM row address strobe (active-low).
DMBS0 73 O SDRAM bank select 0.
DMBS1 74 O SDRAM bank select 1.
DB[15:0] 77:82, 85:90, 93:96 I/O DRAM data bus.
DCS[1:0]# 97,100 O SDRAM chip select (active-low).
DQM 101 O Data input/output mask.
DSCK 102 O Output clock to SDRAM.
DCLK 105 I Clock input to PLL.
RESERVED 106, 108, 113 — Reserved.
VREF 107 I Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor.
COMP 109 I Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
RSET 110 I DAC current adjustment resistor input.
ADVEE 111 P Analog power for video DAC.
ADVSS 112 G Analog ground for video DAC.
VDAC 114 O Composite video output for OSD.
AUX3[2:0] 117:119 I/O Aux3 data I/O.
AUX1[5:0] 122:127 I/O Aux1 data I/O.
AUX1[6] I/O Aux1 data I/O.
128
VFD_DOUT O VFD data output.
AUX1[7] I/O Aux1 data I/O.
131
VFD_DIN I VFD data input.

ESS Technology, Inc. SAM0490-102902 5

 ES4008 DATA SHEET
ES4008 PIN DESCRIPTION

Table 1 ES4008 Pin Description (Continued)

Name Pin Numbers I/O Definition
AUX2[0] I/O Aux2 data I/O.
132
VFD_CLK I VFD clock.
AUX2[1:6] 133:137, 140 I/O Aux2 data I/O.
AUX2[7] I/O Aux2 data I/O.
141
IR I IR remote control.
AUX4[1:0] 142, 143 I/O Aux4 data I/O.
AUX4[7] 144 I/O Aux4 data I/O.
AUX3[5] 145 I/O Aux3 data I/O.
AUX3[3] 146 I/O Aux3 data I/O.
AUX4[5:6] 149, 150 I/O Aux4 data I/O.
AUX3[4] 151 I/O Aux3 data I/O.
AUX3[7:6] 152, 153 I/O Aux3 data I/O.
AUX4[4:2] 154, 155, 158 I/O Aux4 data I/Os.
AUX[0] I/O Auxiliary port 0 (open collector).
160
I2CDATA I/O I2C data I/O.
AUX[1] I/O Auxiliary port 1 (open collector).
161
I2C_CLK I/O I2C clock I/O.
AUX[2:7] 162, 165, 166:169 I/O Auxiliary port.
LOE# 170 O RISC port output enable (active-low).
LCS[3:0]# 173:176 O RISC port chip select (active-low).
178:182,
LD[15:0] I/O RISC port data bus.
185:191,194:197
LWRLL# 198 O RISC port low-byte write enable (active-low).
LWRHL# 199 O RISC port high-byte write enable (active-low).

6 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
ES4008 DEVICE INTERFACES

ES4008 DEVICE INTERFACES

Table 2 lists the device interfaces for the ES4008.
Table 2 ES4008 Device Interfaces
Name Pin Numbers I/O Definition
32 O Audio transmit frame sync output [TWS].
33, 36, 37, 38 O Audio transmit serial data outputs [TSD[3:0]].
39 I/O Audio DAC master clock [MCLK].
40 O Audio transmit bit clock output [TBCK].
Audio Port Interface
41 O Sony/Philips Digital Interface audio output [S/PDIF].
45 I Audio receive serial data input [RSD].
46 I Audio receive frame sync input [RWS].
47 I Audio receive bit clock input [RBCK].
Auxiliary Port Interfaces
Basic Auxiliary 160, 161 I/O Open collectors [AUX [1:0]].
Port Interface 162, 165:169 I/O Primary auxiliary port I/Os [AUX [7:2]].
Auxiliary Port 1
122:128, 131 I/O Auxiliary port 1 data bus I/Os [AUX1[7:0]].
Port Interface
Auxiliary Port 2 132:137,
I/O Auxiliary port 2 data bus I/Os [AUX2[7:0]].
Port Interface 140, 141
Auxiliary Port 3 117:119, 145,
I/O Auxiliary port 3 data bus I/Os [AUX3[7:0]].
Port Interface 146, 151:153
142:144, 149,
Auxiliary Port 4
150, 154, 155, I/O Auxiliary port 4 data bus I/Os [AUX4[7:0]].
Port Interface
158
24 I System reset input [RESET#].
29 I TDM clock input [TDMCLK].
32, 33, 36, 41 I Clock frequency select PLL outputs [SEL_PLL [3:0]].
39 I/O Audio DAC master clock [MCLK].
40 O Audio transmit bit clock output [TBCK].
Clock Interface 47 I Audio receive bit clock input [RBCK].
and Reset 49 I 27-MHz crystal clock input [XIN].
50 O 27-MHz crystal clock output [XOUT].
102 O Output clock [DSCK] to video memory (SDRAM).
105 I Clock input [DCLK] to PLL.
132 I VFD clock input [VFD_CLK].
161 I/O I2C bus interface clock I/O [I2C_CLK].

ESS Technology, Inc. SAM0490-102902 7

 ES4008 DATA SHEET
ES4008 DEVICE INTERFACES

Table 2 ES4008 Device Interfaces (Continued)

Name Pin Numbers I/O Definition
2:7, 10:16, 19:23, O RISC port address bus [LA [21:0]] to EPROM or Flash memory.
204:207
25 I LCS3 ROM boot data width select input [RSEL].
170 O RISC port output enable [LOE#] to EPROM and Flash memory.
EPROM/Flash ROM 173:176 O RISC port chip select outputs [LCS [3:0]] to EPROM or Flash memory.
and RISC Port 178:182, I/O RISC port data bus [LD [15:0]] to EPROM or Flash memory.
Interface 185:191, 194:197
198 O RISC port low-byte write enable output [LWRLL#] to EPROM or Flash
memory.
199 O RISC port high-byte write enable output [LWRHL#] to EPROM or Flash
memory.
Filter and Reference 107 I Video DAC reference voltage input [VREF].
Voltage Interface 109 I Compensation input [COMP].
128 I Front panel data output [VFD_DOUT] to LED unit.
Front Panel 131 I Front panel data input [VFD_DIN] to LED unit.
Display Interface 132 I Front panel clock input [VFD_CLK].
141 I Infrared remote control input [IR].
160 I/O I2C data I/O [I2C_DATA].
I2C Bus Interface
161 I/O I2C clock I/O [I2C_CLK].
1, 18, 27, 59, 68,
75, 92, 99, 104,
130, 148, 157, P I/O power supply [VEE].
159, 164, 183,
193, 201
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120,
129, 138, 147, G Ground [VSS].
Power and Ground
156, 163, 171,
177, 184, 192,
200, 208
9, 35, 44, 83, 121,
P Core power supply [VCC].
139, 172
51 P PLL analog power supply [AVEE].
52 G PLL analog ground [AVSS].
112 G Video DAC analog ground [ADVSS].

8 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
ES4008 DEVICE INTERFACES

Table 2 ES4008 Device Interfaces (Continued)

Name Pin Numbers I/O Definition
53:58, 61:66 O DMA address bus [DMA [11:0]].
69 O Memory column address strobe output [DCAS#].
70 O Memory output enable [DOE#]; memory clock enable output [DSCK_EN].
71 O Memory write enable output [DWE#].
72 O Memory row address strobe output [DRAS#].
System Memory 73 O Memory bank select 0 output [DMBS0].
Interface 74 O Memory bank select 1 output [DMBS1].
77:82, 85:90, I/O Memory data bus [DB [15:0]].
93:96
97, 100 O SDRAM chip select outputs [DCS [1:0]#].
101 O Memory data I/O mask output [DQM].
102 O Output clock to SDRAM [DSCK].
25 O Transmit data output [TDMDX].
28 I Receive data input [TDMDR].
TDM Interface 29 I Clock input [TDMCLK].
30 I Frame sync input [TDMFS].
31 O Output enable [TDMTSC#].
Video DAC Interface 114 O Composite video output for OSD [VDAC].

SYSTEM BLOCK DIAGRAM

A system block diagram for the ES4008 design is shown
in Figure 2.

OSD

ROM/Flash ADC / Audio

S/PDIF-IN

Audio
4/16 MB ES4008 Speakers
DAC
SDRAM Digital Audio
S/PDIF-Out A/V Receiver
EEPROM
VFD VFD Panel
Driver IR Remote

Figure 2 ES4008 System Block Diagram

ESS Technology, Inc. SAM0490-102902 9


LICENSING REQUIREMENTS
Dolby Digital Licensing
Dolby Digital audio enabling software is provided with the
ES4008 series of DVD processors. Dolby is a trademark
of the Dolby Laboratories. Supply of this implementation of
Dolby Technology does not convey a license or imply a
right under any patent, or any other Industrial or
Intellectual Property Right of Dolby Laboratories, to use
this implementation in any end-user or ready-to-use final
product.
Companies planning to use this implementation in
products must obtain a license from Dolby Laboratories
Licensing Corporation before designing such products.
Additional per-chip royalties may be required and are to be
paid by the purchaser to Dolby Laboratories, Inc. Details
of the OEM Dolby Digital license may be obtained by
writing to:
Dolby Laboratories Inc.
Dolby Laboratories Licensing Corporation
Attn.: Intellectual Property Manager
100 Potrero Avenue
San Francisco, CA 94103-4813
10 SAM0490-102902
ES4008 DATA SHEET
LICENSING REQUIREMENTS
SRS Labs, Inc. TruSurround Licensing
SRS TruSurround provides 5.1 virtual surround sound
from two speakers or headphones and is supported in
ESS DVD processors to let users take advantage of multi-
channel formats without needing to have a home theater
system. Companies planning to implement TruSurround in
their products must obtain a separate license agreement
from SRS Labs. Details of license agreement with SRS
Labs may be obtained by contacting:
SRS Labs, Inc.
2909 Daimler Street
Santa Ana, CA 92705
(949) 442-1070
http://www.srslabs.com
ESS Technology, Inc.
ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION

FUNCTIONAL DESCRIPTION
Figure 3 shows the internal block diagram for the ES4008
home theater digital audio processor.

GPIO VDAC
TV-Encoder
LA[21:0]
LCS#[3:0]
LD[15:0] 32-Bit
SRAM/ROM
LWRHL# RISC
Interface OSD
LWRLL# Processor
LOE#
Controller
16 K Cache

TDMCLK Gateway
TDMDR
TDMDX TDM Transport +
TDMFS Interface
TDMTSC# DMA
Controller
DSCK_EN
DSCK
DQM
DCS#[1:0]
RSD DRAM DMA[11:0]
RWS Huffman Interface DWE#
RBCK Serial Audio Decoder DOE#
SPDIF DRAS#[2:0]
Interface
TBCK DB[I5:0]
MCLK DCAS#
TSD[3:0]
TWS SIMD
DSP

ROM

RAM

Figure 3 ES4008 Block Diagram

Device Architecture parser, and the RISC processor. There is a separate

channel for memory refresh. To improve memory
The ES4008 includes a RISC processor, transport stream
bandwidth utilization, internal gateway FIFOs are used
parser, dedicated SRAM and DRAM DMA controllers, and
extensively.
an on-screen display (OSD) controller.
DMA Controller ESS RISC Processor
Embedded in the ES4008 is the 32-bit data pipelined ESS
The DMA controller controls multiple DMA channels for
RISC processor, with a combined 16 kb instruction and
the transfer of 16-bit data between the display interface,
data cache subsystem. The ESS RISC contains a
the audio interface, the Huffman decoder, the transport
program count unit, instruction decode unit, execution

ESS Technology, Inc. SAM0490-102902 11

 ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION

unit, and register file. The program count unit generates an The Programmable Multimedia Processor (PMP) includes
instruction address signal that identifies the location of a the proprietary single instruction, multiple data (SIMD)
32-bit program instruction. DSP, which can handle four 16-bit-wide data streams. Also
included in the device are a screen display controller, a
Program instructions, such as load and store instructions,
digital video encoder, FIFOs and DMA controllers.
include source and destination information, which are
passed on to the instruction decode unit. The instruction RISC Interrupts
decode unit generates specific signals which select their Approximately nine events can cause interrupts to the
targeted registers in the register file. The decoded ESS RISC. Each event has a status bit to indicate the
instruction has its data sent to the program count unit, occurrence of the event and an enable bit to mask it from
where it is incremented to the next data instruction, or, in interrupting the ESS RISC. Table 3 lists the ESS RISC
the case of a branch instruction, changes the data if a interrupts and the conditions that cause them.
branch condition is met.
Table 3 ESS RISC Interrupts
The instruction decode unit generates specific signals Caused By
which select their targeted registers in the register file. The Interrupt Group How To Clear
Condition
decoded instruction has its data sent to the program count
Timer 0 Timer register wraps Writing1 to
unit, where it is incremented to the next data instruction,
from 3FFFFh to ‘clrirq’ register
or, in the case of a branch instruction, changes the data if 00000h bit 3
a branch condition is met.
BCDW 0 DMA Bus Controller Reading the
The execution unit contains a shifter, an arithmetic logic Data is waiting to be ‘rlatch’ register
unit, and a multiplier/divider. The execution unit generates read after DBUS
signal outputs from the respective data signals found in READ command
the register file. These outputs, in turn, are either re-stored H En Idle 1 Huffman Encoder Writing 1 to
in the register file, or asserted as address signals for load state machine goes ‘clrirq’ register
and store operations. idle bit 2
Instruction Cache H De Idle 1 Huffman Decoder Writing 1 to
state machine goes ‘clrirq’ register
The instruction cache of the RISC core is an on-chip
idle bit 1
memory array configured to a size of 8 kB. The cache is
virtually indexed and physically tagged, allowing the Data 1 Either Host-to-RISC TRE cleared
virtual-to-physical address translation to occur in parallel Transfer Data TRE or RISC-to- when RISC
Host DW reads data; DW
with the cache access rather than having to wait for the
(Host can select) cleared when
physical address translation.
RISC writes
Data Cache data
The data cache of the RISC core is an on-chip memory Block 1 After DMA controller Write any data
array configured to a size of 8 kB. Like the instruction Done has read six blocks of to ‘clrhmade’
cache, the data cache is also virtually indexed and RLAs from SIMD register
physically tagged and handles the virtual-to-physical DSP to DRAM
address translation process the same way as the Debug 2 DEBUGIRQ pin goes DEBUGIRQ pin
instruction cache. high goes low
Cache Line Operation FIFO 2 Either Encoder Writing 1 to bit 8
Level Output FIFO or of ‘mipctlreg’
Before cache line operation, the writeback operation may
Decoder Input FIFO register
be performed if the cache content and main memory reach certain fullness.
contents are different. The ESS RISC performs all power
Host to 2 Host sets Host-to- Writing 1 to bit 0
management and system configuration functions.
RISC RISC interrupt bit 7 of of ‘mipctlreg’
‘HostControl0’ register
register (Host
address 2)

12 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION
STALL# Flag Operation
The Stall function of the ES4008 is enabled externally via
the AUX7 port when the AUX7_IS_STALL flag (bit 8) in the
RIFACE_AUX2 register is set. This flag defaults to 0.
When set, AUX7 I/O pin 169 becomes the STALL# pin.
STALL# is asserted active-low prior to the rising edge of
CPU_CLK. The CPU cycle will be stalled at the next cycle.
During a DMA transfer, the DMA controller selects the
enabled and ready channel that has the highest priority,
and asserts STALL# to prevent the ESS RISC core from
using the SRAM data bus during the next clock cycle. The
DMA controller is limited to asserting STALL# every other
clock cycle, making the ESS RISC core operate at least at
half of its clock speed.
Figure 4 depicts the STALL# flag operation.
CPU_CLK
Aux7/STALL#
STALL#
asserted
here Stall cycle
initiated here RISC cycle
resumes here
Figure 4 STALL# Flag Operation
When the ESS RISC core is stalled, one word of data is
transferred to the SRAM data bus between its storage
location in memory, as indicated by the pointer field of the
channel. After the data is transferred, STALL# is
deasserted. The respective values in the pointer and
count fields are either incremented or decremented, as
applicable. When the count field reaches zero, the DMA
controller asserts an interrupt to indicate that a DMA
transfer request to the ESS RISC core is complete.
The STALL# input is typically used for busy-holdoff
operations, such as pipeline overruns. When the ES4008
is accessing a slower microprocessor which is not ready
to accept data transfers, the external device cannot be
accessed at the zero wait state, since there is a 1-cycle
latency before the stall takes effect.
Invoking the STALL# function allows the ES4008 to handle
pipeline overruns by inserting an appropriate number of
wait states until the interlock condition is resolved. When
the interlock condition is resolved, the restart sequence
inserts the correct information received from the external
processor, allowing the data I/O transfers to resume.
ESS Technology, Inc.
Gateway
The gateway works as a FIFO buffer between the data bus
and specific internal components of the ES4008. The
internal components include the audio, RISC and TDM
interfaces, and the transport parser.
Huffman Decoder
The Huffman decoder is a high-speed engine that
decodes variable length codes (VLC), using built-in VLC
tables. A high-level Huffman table, which controls the
automatic switching from one VLC table to the next, is
programmable. The input VLC data is transferred from
DRAM to the Huffman decoder via a DMA channel. The
resulting Zero-Run-Length-Amplitude (RLA) tokens are
transferred on the DRAM bus to the core.
On-Screen Display Controller
The ES4008 incorporates an On-Screen Display (OSD)
controller into the device architecture for on-screen menu
and front panel display support in an A/V receiver. The
OSD controller provides the dedicated circuitry that allows
different speaker types to be selected as part of the home
theater audio setup.
Transport Stream Parser
The transport stream parser performs parsing of all
packetized elementary streams (PESs) and selects the
destinations for all of the audio elements in a given bit
stream for processing by the ESS RISC engine. Each PES
has a packet ID (PID) table, which includes a 4-bit
destination field.
The transport stream parser determines the destination of
the elements so that the ESS RISC engine knows where
to send the final data output after processing. After
processing, the transport stream parser also performs
data flushing of all the buffer FIFOs in the device.
Device Interfaces
Audio Interface
The audio interface is a bidirectional serial port that
connects to an external audio ADC/DAC for the transfer of
pulse code modulated (PCM) audio data in I2S format. The
audio interface supports 16-, 24-, and 32-bit audio framing.
No external master clock is required.
The ES4008 offers four audio interface modes:
1. Stereo mode using TSD0 on pin 33.
2. Dolby Digital (AC-3) and DTS 5.1 channel mode
using TSD[2:0] on pins [37, 36, and 33].
3. DTS ES discrete 6.1-channel mode using TSD[3:0]
pins, [38, 37, 36, and 33].
4. Dolby Digital (AC-3) and DTS 5.1 channel mode
using S/PDIF on pin 41.
SAM0490-102902 13

The ES4008 audio mode configuration is selectable,
allowing it to interface directly with low-cost audio DACs
and ADCs. The audio port provides a standard I 2 S
interface input and output and S/PDIF (IEC958) audio
output.
Stereo mode is in I2 S format while 5.1-channel Dolby
Digital and DTS 5.1-channel audio output can be
channeled through both the I2S interface and the S/PDIF.
The S/PDIF interface consists of a bi-phase mark encoder,
which has low skew.
The transmit I2S interface supports the 128, 192, 256, 384,
and 512 Fs sampling frequency formats, where sampling
frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz,
or 192 kHz. The audio samples for the I 2 S transmit
interface can be 16, 18, 20, 24, and 32-bit samples.
For Linear PCM audio stream format, the ES4008
supports 48 kHz and 96 kHz. Dolby Digital and DTS audio
only supports 48 kHz. The ES4008 incorporates a built-in
programmable analog PLL in the device architecture in
order to generate a master audio clock.
The MCLK pin is for the audio DAC clock and can either
be an output from or an input to the ES4008. Audio data
out (TSD) and audio frame sync (TWS) are clocked out of
the ES4008 based on the audio transmit bit clock (TBCK).
Audio receive bit clock (RBCK) is used to clock in audio
data in (RSD) and audio receive frame sync (RWS).
Audio Decoding Features
The ES4008 incorporates software support for rich audio
decode features, such as Dolby Digital (AC-3), Dolby Pro
Logic, Dolby Pro Logic II, DTS Surround and SRS
TruSurround.
Dolby Digital (AC-3) Audio Decoding
Dolby Digital uses proprietary AC-3 data compression to
deliver up to 6 independent soundtrack channels. An AC-
3 serial coded audio bitstream is comprised of a sequence
of sync frames. Each frame represents 256 new audio
samples.
Figure 5 shows a typical AC-3 sync audio data frame.
SI BSI
SI BSI
C
AB 0 AB 1 AB 2 AB 3 AB 4 AB 5 Aux R
C monitored through the decoding cycle. The compressed
Sync Frame
Figure 5 Typical Dolby Digital AC-3 Sync Audio Framing
14 SAM0490-102902
ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION
The beginning of each frame starts with the Sync
Information (SI) header. The IS header is followed by the
Bit Stream Information (BSI) header and Audio Blocks
(AB) 0 through 5.
The audio blocks may be followed by an auxiliary (Aux)
data field. At the end of each frame is an error check field
that includes a CRC word for error detection. An optional
CRC word may also be added in the SI header, if desired,
for greater accuracy and enhanced error detection in the
decoding process.
During AC-3 decoding, the compressed AC-3 data is input
into the ES4008 at 384 kbps, and contains 5.1 channels of
audio data. The five channels represent five full-frequency
range channels of stereo audio data, while the.1 channel
represents one low frequency effects (LFE) channel of
audio data, usually processed as subwoofer-type audio.
Once the audio is decompressed into its native 5.1
channel format, the audio data can be sent directly to the
speakers only if the required number of speakers for each
channel are available. If the required number of speakers,
the ES4008 will downmix the six channels of audio data
into fewer channels automatically.
Dolby ProLogic and Pro Logic II
Dolby ProLogic is actually four channels of sound,
typically 2-channel Dolby Surround-encoded analog
soundtracks, that are decoded and reproduced through
five speakers. The four channels are: left, center, right and
the left/right surround channels.
While both Dolby Digital and DTS require 5.1-channel
encoded software in order to produce 5.1-channel
surround sound, Dolby Pro Logic II can create a 5.1-
channel sound effect from any 2-channel software. Dolby
Pro Logic II also has a phantom mode that simulates the
center speaker so that a quasi 5.1-channel soundscape
can be reproduced from the standard speakers of an audio
system.
DTS Multi-Channel Decoding
The ES4008 supports DTS multi-channel decoding and
audio post-processing, including bass management.
Separate downloads can be used to support stereo to 5.1
channel effects processing. The DTS 6-channel decoder
operates in real time and allows the channels to be
data output is on a single AES-EBU channel and is
clocked synchronously by the digital audio inputs.
The decoding algorithm does not involve calculations that
are of importance to the quality of the decoded audio. After
synchronization, the decoder unpacks the compressed
audio bitstream, detects and corrects any transmission-
induced errors and demultiplexes the data into individual
audio channels.
ESS Technology, Inc.
ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION
Dolby Digital Surround EX
Dolby Digital Surround EX adds a rear surround channel
to Dolby Digital 5.1 movie soundtracks. The rear surround
channel can be reproduced by speakers positioned
directly behind the viewer.
Dolby Digital Surround EX soundtracks contain a digital
flag which can automatically activate the EX decoding. To
maintain compatibility, the rear surround channel is matrix-
encoded onto the left and right surround channels of an
otherwise conventional Dolby Digital 5.1 mix, so that no
information is lost when the film is played in conventional
5.1-channel format.
DTS Surround
DTS Surround uses scalable data compression to deliver
up to 6 independent channels of multi-channel film
soundtrack or multi-channel music reproduction. The
scalable compression rate allows performance to be
maximized for any software delivery platform.
DTS Extended Surround (DTS-ES)
DTS Extended Surround adds a center-surround channel
to the existing 5.1-channel array. DTS-ES is fully
compatible with all types of multi-channel audio systems.
The center surround information can be carried as either a
separate discrete channel, or it can be combined with
existing surround sound channels via 6.1-channel matrix
decoding. All sounds will be heard, whether played back
as discrete, matrix or on a 5.1-channel system.
HDCD Decoding
Both HDCD process decoding and filtering are used in
audio playback modes during playback of HDCD-encoded
audio data. The HDCD decoding function of the ES4008 is
automatically activated when HDCD process information
is detected in the audio input data.
HDCD code is similar to the packet type of data sent in the
Ethernet network protocol. During quantization, the packet
of HDCD code is inserted into the LSB of the 16-bit audio
word during encoding. The ES4008 reduces the decoded
average signal level of the HDCD process information in
the audio input, allowing increased overhead for the
expanded dynamic range.
SRS TruSurround
SRS TruSurround is a Dolby-certified technology that
allows for a virtualized surround sound experience from
any two-speaker playback system using any multichannel
audio source such as Dolby Digital, Dolby Surround or
Dolby Pro Logic. In TruSurround, the six discrete channels
of digital AC-3 audio are processed into two channels for
surround sound-compatible output. The TruSurround
feature allows for a completely immersive sound
experience which provides the sensory perception that
additional "phantom" speakers are present.
ESS Technology, Inc.
Private DMA Bus Interface
The Private DMA Bus interface sets the priorities for
handling data transfers. The ES4008 makes data transfers
between the TDM interface the highest priority because
devices connected to these interfaces, such as CD-ROM
drives and DVD loaders, typically require specific timing
for data transfers.
Both CD-ROM drives and DVD loaders use the TDM
interface as the physical path for data transfers between
the drive/loader mechanism and the memory interface.
Data transfers have intermediate priority, because the
resources that perform these data transfers are both
inter nal to the E S4008 and have flex ible timi ng
requirements.
System SRAM Interface
The system SRAM interface controls access to optional
external SRAM which can be used for RISC code, stack,
and data. The SRAM bus supports four independent
address spaces, each having programmable bus width
and wait states. The interface can support not only SRAM
but also ROM/EPROM and memory-mapped I/O ports for
standalone applications.
The ES4008 inserts from 1 to 32 wait states into each
cycle, with each wait state being one clock cycle long.
When switching from a low speed bank to a high speed
bank, the turnoff delay of the low speed bank can overlap
the first access of the high speed bank. To prevent data
corruption, the bank select delay time is programmable for
each SRAM bank from 0 to 3T states.
The signals for the SRAM bus are generated from the
internal RISC clock and are timed in integer multiples of
clock cycles, except for the write strobe, which is delayed
by one-half cycle from the address setup and advanced
one-half cycle from the start of the next access cycle.
The on-chip SRAM also allows the ESS RISC to download
subroutines for the SIMD DSP. The ESS RISC core
activates the SIMD DSP by selecting a subroutine either
from the external EPROM, flash memory or by the
SDRAM interface.
SDRAM Interface
The ES4008 provides a glueless 16-bit interface to
SDRAM devices. The maximum amount of memory
supported is 16 MB of SDRAM. The memory interface is
configurable in depth to support 128-Mb addressing.
The memory bus interface generates all the control
signals to interface with external memory. The ES4008
supports different configurations using specific memory
configuration bits.
SAM0490-102902 15
 ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION

Table 4 lists the typical SDRAM configurations used by the Table 5 SDRAM Configurations and Signal Pins
ES4008. Size Memory
SDRAM 0 SDRAM 1 SDRAM2 SDRAM3
Table 4 Typical SDRAM Configurations (MB) Type
DCAS# DCAS# DCAS# DCAS#
Bit Order DRAS0# DRAS0# DRAS0# DRAS0# 1Mx8x2
Size 8.0
Memory Configuration DCS0# DCS0# DCS1# DCS1# (16 Mb)
(MB)
SD64M SD8BIT SDCFG1 SDCFG0
DB[0:7] DB[8:15] DB[0:7] DB[8:15]
2.0 0 0 0 1 1 pc: 512Kx16x2 (16 Mb) DCAS#
DRAS0# 1Mx16x4
4.0 0 0 0 0 2 pcs: 512Kx16x2 (16 Mb) 8.0 — — —
DCS0# (64 Mb)
DB[0:15]
4.0 0 1 0 1 2 pcs: 1Mx8x2 (16 Mb)
DCAS# DCAS#
8.0 0 1 0 0 4 pcs: 1Mx8x2 (16 Mb) DRAS0# DRAS0# 1Mx16x4
16.0 — —
DCS0# DCS1# (64 Mb)
8.0 1 0 X X 1 pc: 1Mx16x4 (64 Mb) DB[0:15] DB[0:15]

16.0 1 0 X X 2 pc: 1Mx16x4 (64 Mb) DCAS# DCAS#

DRAS0# DRAS0# 2Mx8x4
16.0 — —
16.0 1 1 X X 2 pc: 2Mx8x4 (64 Mb) DCS0# DCS0# (64 Mb)
DB[0:7] DB[8:15]
16.0 1 1 X X 1 pc: 2Mx16x4 (128 Mb)
DCAS#
DRAS0# 2Mx16x4
16.0 — — —
The memory interface controls access to both external DCS0# (128 Mb)
DB[0:15]
SDRAM or EDO memories, which can be the sole unified
external read/write memory acting as program and data
memory as well as various decoding and display buffers.
TDM Interface
SDRAM Considerations
The ES4008 implements a high-speed, bidirectional serial
The ES4008 uses SDRAM with a programmed CAS# bus known as a TDM interface that supports a number of
latency of three clocks (CL=3) and sequential burst of full high-speed serial protocols. The TDM interface can also
page length. Performance based on SDRAM is double act as a general-purpose 16-Mbps serial link when not
that of EDO. SDRAM must be software configured before constrained by TDM protocols.
any memory access. The programmable SDRAM refresh
period can be modified to meet any desired configuration. The TDM interface provides an easy connection between
the ES4008 and available communications chips. The
SDRAM Address Mapping TDM interface is a time-division-multiplexed bus that
The memory address (LA) is mapped to the DMA address, multiplexes byte data on up to 64 channels. Time slot 0
which is formed by ADDR in the BUSCON_DMA_ADDR starts after N (which can be set in the XMT/RCVDELAY
registers. The result is then converted into the DRAM register) clocks after the frame starts.
control signals using specific configuration bits in the
Each slot is eight clock periods long, and either transmits
BUSCON_DMA_CONTROL register.
or receives byte data during a write cycle or a read cycle.
SDRAM Configuration Requirements Immediately after slot 0 completes, slot 1 starts and so on.
Table 5 lists the SDRAM memory size configurations, each Each channel is allocated a different time slot on the bus,
with its corresponding signal pins. and the ES4008 can be set to send and receive data in any
combination of different time slots.
Table 5 SDRAM Configurations and Signal Pins Data is assumed to be ordered by time slot; e.g., if time
Size Memory slots 6, 8, and 17 are used, the first DMA byte sent to
SDRAM 0 SDRAM 1 SDRAM2 SDRAM3
(MB) Type memory would be in time slot 6, followed by time slots 8
DCAS# and 17 in order. All DMA byte reordering is done in
DRAS0# 512Kx16x2 software. The interface consists of frame sync signal
2.0 — — —
DCS0# (16 Mb)
DB[0:15] TDMFS, data transmit and receive signals TDMDX and
DCAS# DCAS#
TDMDR, external buffer enable signal TDMTSC# and bit
DRAS0# DRAS0# 512Kx16x2 clock signal TDMCLK.
4.0 — —
DCS0# DCS1# (16 Mb)
DB[0:15] DB[0:15] The timing of the data transfer is externally controlled. The
DCAS# DCAS#
TDM interface can support a number of different timings.
DRAS0# DRAS0# 1Mx8x2
4.0 — —
DCS0# DCS0# (16 Mb)
DB[0:7] DB[8:15]

16 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
FUNCTIONAL DESCRIPTION

The TDM interface can transfer data at a maximum rate of by the software for supporting the control and format
16 Mbps, with a more typical configuration supporting a functions in the first access, and enables the interface in
data rate of up to 4.096 Mbps with a frame sync frequency the second access.
of 8 kHz. The TDM interface programmability includes
The VFD_DATA register, along with the AUX_MODE
independent receive, transmit, and frame sync clock edge
register, both act as containers for an external VFD device
selection and independent receive and transmit data
to read data from it and write VFD clock and data to it
offsets.
during normal operations. The SYS_STATUS register and
Vacuum Fluorescent Display Controller Interface the IR_DIFF register provide additional hardware support
for remote control operations.
The ES4008 provides hardware support for the vacuum
fluorescent display (VFD) controller interface in DVD
player designs. The VFD_CTRL register is programmed

ESS Technology, Inc. SAM0490-102902 17

 ES4008 DATA SHEET
REGISTERS

REGISTERS
Host Interface Host Side Registers Bits Name Description
This section describes the host interface (host side) 3:1 ISEL Select which TRE and DW bits are sent to the
registers of the ES4008. HWRREQ (write request) pins.

H_HOSTDMAPORT (0x0, R/W) HWRREQ =

(DMA_TRE and ISEL_0) or
HOST INTERFACE (DMA PORT) DATA (VCX_TRE and ISEL_1) or
15:0 (DBG_TRE and ISEL_2).
0 CLR_ RISC-to-Host IRQ Clear.
The Host Side DMA Port register contains memory and I/O RIRQ
data transferred to and from the RISC. After reset, this Writing a 1 to this bit clears the RISC To Host
register initializes to 0x0000. IRQ.

H_HOSTMASK (0x4, R/W)

H_HOSTVCXPORT (0x1, R/W) ENDN_ DBG_ DBG_ DMA_ DMA_ VCXI VCXI R2R_
HOST INTERFACE (COMMAND PORT) DATA SEL TRE DW TRE DW _TRE _DW IRQ

7:0 7 6 5 4 3 2 1 0

The Host Side Command Port register contains control The Host Side Interrupt Mask register initializes to 0x00
and status data transferred to and from the RISC. After after reset.
reset, this register initializes to 0x00. Bit Definitions:
Bits Name Description
H_HOSTDBGPORT (0x2, R/W)
7 ENDN_ Host Side Endian Select. When set, this bit
HOST INTERFACE (DEBUG PORT) DATA SEL switches the upper and lower bytes of data sent
7:0 as writes to the Host Interface DMA Port
register.
The Host Side Debug Port register transfers data to and
from the RISC during debugging. After reset, this register 1 = switch upper/lower bytes.
initializes to 0x00. 6 DBG_ Host To RISC Debug Transmit Register Empty
TRE Flag.
H_HOSTCTL (0x3, R/W) 5 DBG_ RISC To Host Debug Data Waiting Flag.
DW
H2R_IRQ OSEL ISEL CLR_RIRQ
1 = Host ready to read debug data from ESS
7 6:4 3:1 0 RISC.
4 DMA_ Host To RISC DMA Transmit Register Empty
The Host Side Control register enables and disables the TRE Flag.
host-to-RISC and RISC-to-host interrupt capabilities of the
ES4008. After reset, this register initializes to 0x00. 1 = Host ready to send DMA data to ESS RISC.
Bit Definitions: 3 DMA_ DMA data waiting.
Bits Name Description DW
1 = Host waiting to read data from ESS RISC.
7 H2R_IRQ Host to RISC IRQ Enable.
2 VCXI_ VCXI transmit register empty.
Writing a 1 to this bit sets the host to RISC TRE
IRQ flag. 1 =Host ready to send data to ESS RISC.
6:4 OSEL Select which TRE and DW bits are sent to the 1 VCXI_ VCXI data waiting.
HRDREQ read request pins. DW
1 = Host waiting to read data from ESS RISC.
HRDREQ = 0 R2R_ Interrupt flag.
(DMA_DW and OSEL_0) or IRQ
(VCX_DW and OSEL_1) or 1 = Set by ESS RISC as Ready To Receive
(DBG_DW and OSEL_2). signal to the host.

18 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
REGISTERS

H_HOSTIRQSTAT (0x5, R) Bit Definitions:

H2R_IR DBG_ DBG_ DMA_ DMA VCXI_ VCXI_ R2H_ Bits Name Description
Q TRE DW TRE DW TRE DW IRQ
15:13 — Reserved.
7 6 5 4 3 2 1 0
12:0 OSD_ OSD horizontal ending address value.
HEND
The read-only Host Side Host Interrupt Status register
reads the status of Interrupts from the ESS RISC to the
host (1 = IRQ present, 0 = No IRQ present). VID_SCN_OSD_VSTART (0x20001118h, R/W)
— OSD_VSTART
Bit Definitions: 15:13 12:0
Bits Name Description
7 H2R_ Host To RISC Interrupt Flag. Set by the host as The OSD Video Screen Vertical Start Address register
IRQ a signal to the RISC to generate an interrupt. contains the 13-bit vertical starting address value for the
6 DBG_ Host To RISC Debug Transmit Register Empty OSD, as referenced from the active video display.
TRE Flag. When set, host sends data to the RISC. Bit Definitions:
5 DBG_ Host To RISC Debug Data Waiting Flag. When
Bits Name Description
DW set, host can read data from the RISC.
15:13 — Reserved.
4 DMA_ Host To RISC DMA Transmit Register Empty
TRE Flag. When set, host sends data to the RISC. 12:0 OSD_ OSD vertical starting address value.
VSTART
3 DMA_ Host To RISC DMA Data Waiting Flag. When
DW set, host reads DMA data from the RISC.
2 VCXI_ VCXI transmit register empty (OK for host to VID_SCN_OSD_VEND (0x2000111Ch, R/W)
TRE send data to the RISC). — OSD_VEND
1 VCXI_ VCXI data waiting (host needs to read data from 15:13 12:0
DW the RISC).
0 R2H_ Interrupt flag set by the RISC as a signal to the The OSD Video Screen Vertical End Address register
IRQ host. contains the 13-bit vertical ending address value for the
OSD, as referenced from the active video display.
Bit Definitions:
On-Screen Display Controller Registers
Bits Name Description

VID_SCN_OSD_HSTART (0x20001110h, R/W) 15:13 — Reserved.

12:0 OSD_ OSD vertical ending address.
— OSD_HSTART
VEND
15:13 12:0

The OSD Video Screen Horizontal Start Address register VID_SCN_OSD_MISC (0x20001124h, R/W)
contains the horizontal starting address value for the OSD, LAT_INT RESET_OVERLAY PAL_INDEX INTEN LDMD MODE
as referenced from the active display window. 7 6 5:4 3 2 1:0

Bit Definitions:
The OSD Video Screen Miscellaneous register contains
Bits Name Description the control logic and status bits for the OSD controller.
15:13 — Reserved.
Bit Definitions:
12:0 OSD_ OSD horizontal starting address value.
HSTART Bits Name Description
7 LAT_INT Latched interrupt. Read-only.
VID_SCN_OSD_HEND (0x20001114h, R/W) 6 RESET_ Reset overlay section (set to 1 at reset).
OVERLAY
— OSD_HEND
5:4 PAL_ Upper 2 bits of palette address when in
15:13 12:0
INDEX 2-bit/pixel mode.
The OSD Video Screen Horizontal End Address register 3 INTEN Interrupt enable.
contains the 13-bit horizontal ending address value for the 2 LDMD Enable palette load.
OSD, as referenced from the active video display.

ESS Technology, Inc. SAM0490-102902 19

 ES4008 DATA SHEET
REGISTERS

Bits Name Description Bits Name Description

1:0 MODE 0 0 = Bypass (initializes to 00 at reset). 2 VFDCLK_ VFD Clock Output Select.
0 1 = 2 bit/pixel. OUT 1 = VFD Clock output selected.
1 0 = 4 bit/pixel. 0 = AUX2[0] selected.
1 1 = 8 bit/pixel. 1 AUX2_2 AUX2_2 Select.
1 = Reserved.
VID_SCN_ 0 = AUX2[2] selected.
OSD_PALETTE (0x20001140h–0x2000117Ch, R/W) 0 IRQ_OUT Interrupt Output Select.
Y V U BLND_ON/OFF BLND 1 = Interrupt Output selected.
15:12 11:8 7:4 3 2:0 0 = AUX2[3] selected.

These 16 registers contain the OSD palette. VFD_CTL (0x200013CCh, R/W)

— VFDCLK_FSEL VFD_MODE VFDK_SEL VFD_EN
Bit Definitions:
7:4 3 2 1 0
Bits Name Description
15:12 Y Upper 4 bits of luminance data (lower 4 The VFD Control register contains the control logic for the
bits are 0). VFD interface. This register initializes to 0x00h after reset.
11:8 V Upper 4 bits of V chrominance data Bit Definitions:
(lower 4 bits are 0).
Bits Name Description
7:4 U Upper 4 bits of U chrominance data
(lower 4 bits are 0). 7:4 — Reserved.
3 BLND_ Blending/Transparency Enable. 3 VFDCLK_ VFD Clock Frequency Select.
ON/OFF 1 = Blending off; transparency on. FSEL 1 = 844 kHz clock selected.
0 = Blending on; transparency off. 0 = 422 kHz clock selected.
2:0 BLND Blending value: 2 VFD_ VFD Mode Select.
value blnd value blnd MODE 1 = Write.
0 1/8 4 5/8 0 = Read.
1 2/8 5 6/8 1 VFDK_ VFD Sampling Clock Edge Select.
2 3/8 6 7/8 ESEL 1 = Falling edge selected.
3 4/8 7 8/8 0 = Rising edge selected.
finalpixel = blnd x palette value + (1 - 0 VFD_EN VFD Interface Enable.
blnd) x original pixel. 1 = Enabled.
0 = Disabled.
For mode 3 (8-bit/pixel) the upper 4 bits of the pixel are the
blend information, the lower 4 bits are the palette index
IRQ_CTL (0x200013D4h, R/W)
and the blend information in the palette is ignored.
SPORT IR_ SPORT_
— — — — IR_MSK
_DET DET MKS
AUX_MODE (0x20001340h, R/W)
7 6 5 4 3 2 1 0
VFDDATA_ VFDCLK_ IRQ_
— AUX2[7:4]_SEL AUX2_2
OUT OUT OUT
The System Interrupt Control register contains the control
7:5 4 3 2 1 0
logic for the ES4008. This register initializes to 0x00h after
reset.
The Aux Pins Mode register contains the control logic for
the Aux2 port and the VFD interface. Bit Definitions:

Bit Definitions: Bits Name Description

Bits Name Description 7 — Reserved.

7:5 — Reserved. 6 SPORT_ Interrupt edge detect for Serial Port.

DET 1 = Falling edge.
4 AUX2[7:4] Aux2[7:4] Select. 0 = Rising edge.
_SEL 1 = Select AUX[7:4].
0 = Select AUX2[7:4] (default). 5 — Reserved.

3 VFDDATA VFD Data Output Select. 4 IR_DET Interrupt edge detect for IR
_OUT 1 = VFD data output selected. 1 = Falling edge.
0 = AUX1[6] selected. 0 = Rising edge.
3 — Reserved.

20 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
REGISTERS

Bits Name Description Bit Definitions:

2 SPORT Interrupt mask for Serial Port. Bits Name Description
_MSK 1 = SPORT IRQ for UART masked. 15:11 — Reserved.
1 — Reserved. 10 DBGMODE Debug mode:
0 IR_MSK Interrupt mask for IR. 0 = Save power from outside pins
1 = IR IRQ masked. toggling.
1 = riscaddr and riscbus are seen from
the SRAM address/data.
Host Interface RISC Side Registers Default is 1 after reset.
9 CACHEFLS Cache Flush. When set to 1, the
This section describes the host interface RISC side
memory cache is flushed. Default is 1
registers.
after reset.
1 = Flush cache.
0 = Normal operation.
R_HOSTDMAPORT (0x20003000h, R/W)
8 CACHE Cache Disable.
HOST INTERFACE RISC SIDE DMA PORT
DISABLE 0 = Cache enabled.
15:0 1 = Cache bypassed.
Default is 1 after reset.
The RISC Side DMA Port register contains data 7:5 DIV Clock Divisor.
transferred to and from the host via the DMA port. After
4 B3W Bank 3 Width
reset, this register initializes to 0x0000.
1 = 16 bits wide.
0 = 8 bits wide (default).
R_HOSTVCXPORT (0x20003004h, R/W)
3 B2W Bank 2 Width
HOST INTERFACE RISC SIDE COMMAND PORT 1 = 16 bits wide.
7:0 0 = 8 bits wide (default).
2 B1W Bank 1 Width
The RISC Side Command Port register contains data 1 = 16 bits wide.
transferred to and from the host via the command port. 0 = 8 bits wide (default).
After reset, this register initializes to 0x00. 1:0 B0W Bank 0 Width [1:0]
00 = 8-bit wide (default).
Host Interface RISC-SRAM Interface Registers 01 = 16-bit wide.
10 = Map Bank 0 to DRAM.
This section describes the RISC-SRAM interface registers
11 = Undefined.
associated with the host interface of the ES4008.

RIFACE_WIDTH (0x20004000h, R/W) RIFACE_WAIT_STATE (0x20004004h, R/W)

CACHE — BANK3 BANK2 BANK1 BANK0
DBG- CACHE-
— DIS- DIV B3W B2W B1W B0W 31:20 19:15 14:10 9:5 4:0
MODE FLS
ABLE
15:11 10 9 8 7:5 4 3 2 1:0
The RISC-SRAM Interface Wait State register contains the
logic for the total number of possible external wait states
The RISC-SRAM Interface Width register contains the that can be inserted per access for SRAM banks 3:0. Up
logic for establishing the width of the bus to external to 32 wait states can be inserted if desired.
memory, and controls the internal cache. The value of the
TDMDX pin is sampled at the rising edge of RESET# and Table 7 gives the hexadecimal value for each number of
the RIFACE_WIDTH register is programmed according to possible wait states:
the bit settings listed in Table 6. Table 7 Hex Values for Wait States
Hex Wait Hex Wait Hex Wait Hex Wait
Table 6 ROM Width Selection Options
Value State Value State Value State Value State
TDMDX/RSEL Selection 1F 1 17 9 0F 17 07 25
1 8-bit ROM. 1E 2 16 10 0E 18 06 26
1D 3 15 11 0D 19 05 27
0 16-bit ROM.
1C 4 14 12 0C 20 04 28
1B 5 13 13 0B 21 03 29

ESS Technology, Inc. SAM0490-102902 21

 ES4008 DATA SHEET
REGISTERS

Table 7 Hex Values for Wait States (Continued) Bit Definitions:

Hex Wait Hex Wait Hex Wait Hex Wait Bits Name Description
Value State Value State Value State Value State
15:9 — Reserved.
1A 6 12 14 0A 22 02 30
8 AUX7_IS_ RISC Cycle Stall.
19 7 11 15 09 23 01 31 STALL
18 8 10 16 08 24 00 32 (default) 7:4 T Tri-stateable controls.
3:0 P Tri-stateable pads.
RIFACE_AUX1 (0x2000402Ch, R/W)
— 0 T3 T2 P3 P2 P1 P0 When this register is read, the values read are the values
15:10 9:6 5 4 3 2 1 0 at the pin. Default values for tri-state controls are 0 (tri-
state) at reset.
This register is a general I/O port for interfacing with
external devices. Bus Controller Registers
Bus Controller (Memory Controller) Registers
Bit Definitions:
This section describes the Memory Controller registers of
Bits Name Description the Bus Controller module in detail.
15:10 — Reserved.
9:6 — Reserved. Always 0. BUSCON_DRAM_CONTROL (0x20008100h, R/W)
5:4 T3,T2 Tri-state controls. SEL SD SD8 BIG SD SREF REF RAS RAS SPD
—
SCLKEN 64M BIT EDO CF EN EN — PRE DEL EDO
1 = I/O state selected.
31:17 16 15 14 13 12:11 10 9 8:6 5:4 3:2 1:0
0 = Tri-state selected.
3:2 P3, P2 Tri-stateable pins. The Bus Controller DRAM Control register contains the
1:0 P1, P0 Open collector pins. control logic for the video memory interface. This register
initializes to 0x0000 after reset.
When this register is read, the values read are the values
Bit Definitions:
at the pin. The two open collector pins allow I 2 C bus
communication and require an external pull-up resistor. Bits Name Description
The default value is for P3:P2 to be tri-state, and P1:P0 to 31:17 — Reserved.
be disabled (i.e., P1, P0 = high (logic 1), and T3, T2 = low 16 SEL SDRAM Clock Enable.
(logic 0)). SCLK 1 = Pin 70 is SDSCLKEN
EN 0 = Pin 70 is DOE#
RIFACE_AUX2 (0x20004030h, R/W) 15 SD64M SDRAM Type Select.
1 = Use 64 Mb SDRAM
— AUX7_IS_STALL T P 0 = Use 16 Mb SDRAM
15:9 8 7:4 3:0 14 SD8 SDRAM 8-Bit Select.
BIT 1 = SDRAM is x 8.
This register is a second general-purpose I/O port with 0 = SDRAM is x 16.
four tri-state channels. 13 BIG EDO DRAM Select.
EDO 1 = EDO is 1M x 16
0 = EDO is 256K x 16

22 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
REGISTERS

Bits Name Description Audio Interface Registers

12:11 SDCF SDRAM/EDO Memory Configuration. This section describes all the registers controlling the
audio section, and serves as a reference for both
Size SD SD8 SD SD Memory hardware and firmware engineers who need to
(MB) 64M BIT CFG CFG Configuration understand the internal workings of the ES4008.
1 0
2.0 0 0 0 1 1 pc 512kx16x2 AUDIOCTL (0x2000D008h, R/W)
(16 Mb)
AIEN AMS AREN AXEN ABEN DM SRST —
4.0 0 0 0 0 2 pc 512kx16x2
7 6 5 4 3 2 1 0
(16 Mb)
4.0 0 1 0 1 2 pc: 1Mx8x2 This Audio Control register enables the corresponding
(16 Mb) functions and clocks. After reset, it is initialized to 0x00.
8.0 0 1 0 0 4 pc 1Mx8x2
Bit Definitions:
(16 Mb)
Bits Name Description
8.0 1 0 — — 1 pc: 1Mx16x4
(64 Mb) 7 AIEN Audio interrupt enable.
The corresponding port must be enabled for
16.0 1 0 — — 2 pc 1Mx16x4
proper interrupt status.
(64 Mb)
0 = disabled.
16.0 1 1 — — 2 pc 2Mx8x4 1 = enabled.
(64 Mb) 6 AMS Audio master clock selection:
16.0 1 1 — — 1 pc 2Mx16x4 0 = external MCLK.
(128 Mb) 1 = internal MCLK.
5 AREN Audio receive enable.
0 = disabled.
10 SREF SDRAM Refresh Enable. 1 = enabled.
EN 1 = Refresh logic for SDRAM enabled. 4 AXEN Audio transmit enable. The DMA must be
9 REF EDO Refresh Enable. started before enabling the transmit port.
EN 1 = Refresh logic for EDO DRAM enabled. 1 = Audio transmit enabled.
8:6 — Reserved. 0 = Audio transmit disabled.
5:4 RAS RAS Precharge Time Control for EDO. 3 ABEN Audio bit clock generator enable (used only
PRE when internal MCLK is selected).
3:2 RAS RAS to CAS Delay Time. 2 DM Data input (either from pri_bus or risc) debug
DEL mode:
0 = data from pri_bus.
1:0 SPD EDO DRAM Speed Select. 1 = data from risc_bus.
EDO
1 SRST Soft reset, this bit will self-reset when a 1 is
written.
BUSCON_DRAM_SREFTIME (0x20008114h, R/W)
0 — Reserved.
INTVAL
7:0
AUDIOXMT (0x2000D00Ch, R/W)
The Bus Controller DRAM Refresh Time register controls TLSB TDGE TDFS TDM TCF TFM ITFS TBCS AM TBCF
the SDRAM refresh period for the system, and contains 15 14 13 12:10 9:8 7:6 5 4 3:2 1:0
the refresh interval value. After reset, it is not initialized.
Bit Definitions: This Audio Transmit Format register is used for setting up
the format for the transmit port. After reset, the register is
Bits Name Description
initialized to 0x0000.
7:0 INTVAL SDRAM refresh interval value.
Bit Definitions:
Bits Name Description
15 TLSB Transmit LSB Select.
1 = LSB first.
0 = MSB first.

ESS Technology, Inc. SAM0490-102902 23

 ES4008 DATA SHEET
REGISTERS

Bits Name Description Bits Name Description

14 TDGE Transmit Bit Clock Edge Select. 14 RDGE Receive Data Bit Clock Edge Select.
1 = Output data on falling edge of clock. 1 = Input data sampled on falling edge
0 = Output data on rising edge of clock. 0 = Input data sampled on rising edge.
13 TDFS Transmit Data Frame Sequence Select. 13 RDFS Receive Data Frame Sequence.
1 = Last bit sent on last cycle. 1 = Last bit sent on last cycle
0 = First bit sent on first cycle. 0 = First bit sent on first cycle.
12:10 TDM Transmit Data Frame Mode Select. 12 — Reserved.
000 = 16-bit data frame. 11:10 RDM Receive Data Frame Select
001 = 18-bit data frame. 00 = 16-bit data frame.
010 = 20-bit data frame. 01 = Reserved.
011 = 24-bit data frame. 10 = Reserved.
100 = 32-bit data frame. 11 = Reserved.
101 = Reserved.
9:8 RCF Receive Cycle Frame Select
11x = Reserved.
00 = 16-bit cycle frame.
9:8 TCF Transmit Cycle Frame. 01 = 24-bit cycle frame.
00 = 16-bit cycle frame. 10 = Reserved.
01 = 24-bit cycle frame. 11 = Reserved.
10 = 32-bit cycle frame.
7:6 RFM Receive Frame Mode Select.
11 = Reserved.
00 = Reserved.
7:6 TFM Transmit Frame Mode 01 = Philips I2S format.
00 = Reserved. 10 = Normal frame mode.
01 = Philips I2S format. 11 = Reserved.
10 = Normal frame mode.
5 IRFS Inverse Receive Frame Sync Select.
11 = Reserved.
1 = Enabled.
5 ITFS Inverse audio transmit frame sync. 0 = Disabled.
1 = Enabled.
4 RBCS Receive Bit Clock Select.
0 = Disabled.
1 = Reserved. Driven by external ADC.
4 TBCS Audio Bit Clock Select 0 = Use external bit clock.
1 = Use internal bit clock and output bit clock.
3:2 — Reserved.
0 = Use external bit clock.
1:0 RBCF Receive Bit Clock Frequency.
3:2 AM Audio Mode Select
Reserved. Driven by external ADC.
00 = Stereo L-R channel.
01 = 5.1 channel.
10 = 7.1 channel. AUDIOAPLLM (0x2000D014h, R/W)
11 = Reserved. M
1:0 TBCF Audio Transmit Bit Clock Frequency Select 7:0
00 = MCLK/8.
01 = MCLK/2. This register is the Analog PLL Frequency Divider register.
10 = MCLK/4. After reset, it is initialized to 0x4Ah.
11 = MCLK/1.
Bit Definitions:
AUDIORCV (0x2000D010h, R/W) Bits Name Description
RLSB RDGE RDFS — RDM RCF RFM IRFS RBCS — RBCF 7:0 M Audio frequency divider M.
15 14 13 12 11:10 9:8 7:6 5 4 3:2 1:0
AUDIOAPLLN (0x2000D018h, R/W)
This is the audio receive format register. After reset, it is FS OD M8 N
initialized to 0x0000. 7 6 5 4:0
Bit Definitions:
This register is the Analog PLL Frequency Multiplier
Bits Name Description register. After reset, it is initialized to 0x1Fh.
15 RLSB Receive LSB Select.
1 = LSB first.
0 = MSB first.

24 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
REGISTERS

Bit Definitions: Bits Name Description

Bits Name Description 0 SOE SPDIF output enable:
7 FS Sampling Frequency Select. 1 = Enabled.
1 = 384 sample frequency selected. 0 = Disabled.
0 = 256 sample frequency selected.
6 OD Output Divider. SPDIF_CSD1:6 (0x2000D020h:0x2000D034h, R/W)
5 M8 Bit 8 of M Divider Value. CDS1:6
4:0 N Audio frequency multiplier N. 31:0

S/PDIF Interface Registers The S/PDIF Channel Status 1:6 registers initialize to
This section describes the S/PDIF audio interface 0x0000 0000 after reset.
registers. Bit Definitions:
Bits Name Description
31:0 CDS1:6 SPDIF channel status data.
SPDIF_CTL (0x2000D01Ch, R/W)
SPDIF_ AUDIOIMASK (0x2000D038h, R/W)
— SPDIF_RST SPDIF_CLK SFRMDB — SOE
SFRMV
MSSE MSCSE MSTRE MSUE MACS MAUE MATRE MADW
7 6 5:4 3 2 1 0
7 6 5 4 3 2 1 0

The S/PDIF Control register contains the control logic for

This register is the Audio Interrupt Mask register. After
the S/PDIF output function of the ES4008. This register
reset, it is initialized to 0x00. Write a “1” to the
initializes to 0x00 after reset.
corresponding bit to mask the interrupt.
Bit Definitions:
Bits Name Description Bit Definitions:
7 — Reserved. Bits Name Description
6 SPDIF S/PDIF Soft reset. 7 MSSE Mask for SPDIF channel swap error.
RST 6 MSCSE Mask for SPDIF channel status empty.
5:4 SPDIF S/PDIF Bit Clock Frequency Select. 5 MSTRE Mask for SPDIF transmit register empty.
_CLK 00 = SPMCLK/8 (n=8)
01 = SPMCLK/4 (n=2) 4 MSUE Mask for SPDIF underflow error.
10 = SPMCLK/2 (n=4) 3 MACS Mask for audio channel swap error.
11 = SPMCLK/16 (n=16) 2 MAUE Mask for audio underflow error.
3 SPDIF_ S/PDIF Subframe Validity Select. 1 MATRE Mask for audio transmit register empty.
SFRMV
0 MADW Mask for audio data waiting interrupt.
2 SFRM User data bit for subframe.
DB
1 — Reserved. Always 0.

ESS Technology, Inc. SAM0490-102902 25

 ES4008 DATA SHEET
AUDIO INTERFACE TIMING

AUDIO INTERFACE TIMING

The audio transmit and receive timing diagrams for the
ES4008 are shown in Figure 6 through Figure 10.

TBCK/RBCK

TWS

TSD[3:0]/RSD

Figure 6 Right Justified Mode / 16-Bit Cycle Frame / 16-Bit Data Frame / MSB First

TBCK/RBCK

TWS

TSD[3:0]/RSD

Figure 7 Right Justified Mode / 24-Bit Cycle Frame / 16-Bit Data Frame / MSB First

TBCK/RBCK

TWS

TSD[3:0]/RSD

Figure 8 Right Justified Mode / 32-Bit Cycle Frame / 24-Bit Data Frame / LSB First

26 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
AUDIO INTERFACE TIMING

TBCK/RBCK

TWS

TSD[3:0]/RSD

Figure 9 Left Justified Mode / 32-Bit Cycle Frame / 24-Bit Data Frame / MSB First

TBCK/RBCK

TWS

TSD[3:0]/RSD

Figure 10 I2S Mode

ESS Technology, Inc. SAM0490-102902 27

 ES4008 DATA SHEET
SDRAM INTERFACE TIMING

SDRAM INTERFACE TIMING

The SDRAM interface timing diagrams for the ES4008 are
shown in Figure 11 through Figure 14.

Burst Length = 4, DCAS# Latency = 3

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

DSCK
tCK3

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

DMA[10] RAw RAz

DMA[9:0] RAw CAw CAx RAy RAz CAz

DQM

Hi-Z
DB[15:0] Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3

Activate Read Read Read Precharge Activate Read

Command Command Command Command Command Command Command
Bank A Bank A Bank A Bank A Bank A Bank A Bank A

Figure 11 SDRAM Random Column Read Timing

28 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET

Burst Length = 4, DCAS# Latency = 3

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

DSCK
tCK3

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

DMA[10] RBw RBz

DMA[9:0] RBw CBw CBx RBy RBz CBz

DQM

Hi-Z
DB[15:0] DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1

Activate Read Read Read Precharge Activate Read

Command Command Command Command Command Command Command
Bank B Bank B Bank B Bank B Bank B Bank B Bank B

Figure 12 SDRAM Random Column Write Timing

ESS Technology, Inc. SAM0490-102902 29

 ES4008 DATA SHEET

Burst Length = 8, DCAS# Latency = 3

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

DSCK
tCK3

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

DMA[10] RBx RAx RBy

DMA[9:0] RBx CBx RAx CAx RBy CByz

tRP
tAC3
tRCD
DQM

Hi-Z
DB[15:0] Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Axy By0

Activate Read Activate Read Precharge Activate Read Precharge

Command Command Command Command Command Command Command Command
Bank B Bank B Bank A Bank A Bank B Bank B Bank B Bank A

Figure 13 SDRAM Random Row Read Timing

30 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

DSCK
tCK3

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

RBx RAx RBy

DMA[10]

RBx CBx RAx CAx RBy CByz

DMA[9:0]

tRCD tDPL tRP tDPL

DQM

Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
DB[15:0]

Activate Write Activate Write Precharge Activate Write Precharge

Command Command Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank A Bank A Bank A Bank B

Figure 14 SDRAM Random Row Write Timing

ESS Technology, Inc. SAM0490-102902 31

 ES4008 DATA SHEET

Table 8 SDRAM Interface Timing

Symbols Parameters Minimum Maximum Unit Notes

tRRD (min) Row active to Row Active Delay 18 —

tRCD (min) DRAS# to DCAS# Delay 24 —

ns 1
tRP (min) Row precharge time 24 —

tRAS (min) 54 —
Row active time
tRAS (max) — 100 µs —

tRC (min) Row cycle time 90 — ns 1

tCDL (min) Last data in to new column address delay 1 —

tRDL (min) Last data in to row precharge 1 — 2

CLK
tBDL (min) Last data in to burst stop 1 —

tCCD (min) Column address to column address delay 1 — 3

Number of valid output data (CAS latency = 3) 2 — ea 4

NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time,
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.

Table 9 Operating AC Characteristics

Parameters (CAS Latency = 3) Symbols Minimum Maximum Unit Notes

CLK cycle time tCC 9 — ns 1

CLK to valid output delay tSAC — 7 ns 1, 2

Output data hold time tOH 2.5 — ns 2

CLK high pulse width tCH 3 — ns 3

CLK low pulse width tCL 3 — ns 3

Input setup time tSS 2 — ns 3

Input hold time tSH 0.5 — ns 3

CLK to output in low-Z tSLZ 1 — ns 2

CLK to output in Hi-Z tSHZ — 7 ns —

NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1 ns, (tR/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tR & tF) = 1ns. If tR and tF are both longer than 1 ns, transient time
compensation should be considered, that is, [(tR + tF)/2 - 1] ns should be added to the parameter.

32 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
SRAM INTERFACE TIMING

SRAM INTERFACE TIMING

The SRAM Interface read and write timing diagrams for
the ES4008 are shown in Figure 15 and Figure 16.

tSRAM_AT tBS_DT tSRAM_AT

LA[21:0] Address Address Address

LCS[3:0]#

LWRxx#

LOE# tRC_DSTDL tRC_DHTDL tRC_DSTDL tRC_DHTDL

LD[15:0] rd0 rd1 rd0

n Waitstate Bank Select n Waitstate

Symbols Parameters Minimum Typical Maximum Unit

tDRAM_IOSS DRAM interface output signal skew 0 — 3

tRC_DSTDL Read cycle data setup time to data latch 6 — — ns

tRC_DHTDL Read cycle data hold time to data latch 2 — —

tSRAM_AT SRAM access time 2 — 33

Internal CPU clock cycle
tBS_DT Bank Select delay time 0 — 3

Figure 15 SRAM Read Timing

ESS Technology, Inc. SAM0490-102902 33

 ES4008 DATA SHEET
SRAM INTERFACE TIMING

tSRAM_AT tBS_DT tSRAM_AT

LA[21:0] Address Address Address

LCS[3:0]#

LWRxx# tA_STWS tA_STWS tA_HTWS

tA_HTWS
tW_STWL
LOE#

LD[15:0] Data Data Data

Symbols Parameters Minimum Typical Maximum Unit

tSRAM_IOSS SRAM interface output signal skew 0 — 3 ns

tSRAM_AT SRAM access time 2 — 33

tBS_DT Bank Select delay time 0 — 3

tA_STWS Address setup time to write strobe 0.5 — 0.5 Internal CPU clock cycle

tA_HTWS Address hold time to write strobe 0.5 — 0.5

tW_STWL Write strobe pulse width low 1 — 31.5

Figure 16 SRAM Write Timing

34 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
TDM INTERFACE TIMING

TDM INTERFACE TIMING

The TDM interface timing diagram for the ES4008 is
shown in Figure 17.

tTDMCLK_P
tTDM_RD Recv Channel 0 Recv Channel 1

TDMCLK
tTDMFS_HT
TDMFS
tTDMDR_ST
tTDMFS_ST
TDMDR 0 1 2 3 4 5 6 7
tTDMDR_HT
TDMTSC#
tTDM#_COD

TDMDX 0 1 2 3 4 5 6 7
tTDMDX_DOD

tTDM_TD Transmit Channel 0

Symbols Parameters Minimum Typical Maximum Unit

tTDMCLK_P TDM clock period 62.5 — —

tTDM#_COD TDMTSC# control output delay to TDMCLK 0 — 2

tTDMFS_ST TDMFS setup time to TDMCLK 4 — —

tTDMFS_HT TDMFS hold time to TDMCLK 2 — — ns

tTDMDR_ST TDMDR data setup time to TDMCLK 4 — —

tTDMDR_HT TDMDR data hold time to TDMCLK 2 — —

tTDMDX_DOD TDMDX data output delay to TDMCLK 0 — 2

tTDM_RD TDM receive delay to TDMFS 0 — 8

Internal CPU clock cycle
tTDM_TD TDM transmit delay to TDMFS 0 — 8

Figure 17 TDM Interface Timing

ESS Technology, Inc. SAM0490-102902 35

 ES4008 DATA SHEET
ELECTRICAL SPECIFICATIONS

ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Storage temperature range
Operating temperature range
Voltage range on any pin
Power dissipation
Recommended Operating Conditions
Operating temperature range
WARNING: Stress beyond those listed under the Absolute
Maximum Ratings may cause permanent damage to the device.
–65° C to 150° C This is a stress rating only, and functional operation of the device
0° C to 70° C at these or any other conditions beyond those indicated in the
Recommended Operating Conditions section of this specification
–0.5 V to + 5.5 V
is not implied. Exposure to the Absolute Maximum Ratings
1.8 W conditions for extended periods may affect device reliability.
WARNING: Electrostatic Discharge (ESD) can damage this
device. Proper procedures must be followed to avoid ESD when
0° C to 70° C handling this device.

Supply voltage VCC 2.80V±150 mV; Electrical characteristics for the ES4008 are listed in Table
415 mA nominal 10 through Table 11.
Supply voltage VEE 3.60V±150 mV;
60 mA nominal
Supply voltage AVEE 3.60V±150 mV;
10 mA nominal
Supply voltage ADVEE 3.60V±150 mV;
150 mA nominal

DC Electrical Characteristics
Table 10 DC Electrical Characteristics
Symbol Parameter Minimum Maximum Unit Comments

VIH High-level input voltage 2.0 5.5

All inputs TTL levels except CLK
VIL Low-level input voltage –0.3 0.8

VCLKH CLK high-level input 2.0 VEE +0.25

V TTL level input
VCLKL CLK low-level input –0.3 0.8

VOH High-level output voltage 3.0 — IOH = 1 mA

VOL Low-level output voltage — 0.45 IOL = 4 mA

ILI Input leakage current — ±15

µA N/A
ILO Output leakage current — ±15

CIN Input capacitance — 10

pF
CO Input/output capacitance — 12 fc = 1 MHz

CCLK CLK capacitance — 20 pF

36 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET
ELECTRICAL SPECIFICATIONS

AC Electrical Characteristics
Table 11 VFD Interface Characteristics
Parameter Minimum Typical Maximum Unit

VFD Clock Frequency — — TBD MHz

VFD Clock Pulse Width 500 — —

VFD Data Setup 50 — —

ns
VFD Data Hold 50 — —

VFD Data Output Delay — — 5

Device Clock Characteristics

Device clock characteristics are shown in Figure 18.

t1, t6

t2, t7

Clock
t4, t9 t3, t8 t5, t10

Symbol Parameter Minimum Typical Maximum Unit Comments

Audio Master Clock Timing
t1 tACLK_P Audio clock period 40 — — ns
t2 tACLK_LT Audio clock low time 9 — — ns
t3 tACLK_HT Audio clock high time 9 — — ns T = 1/192 kHz X 128
t4 tACLK_RT Audio clock rise time — — 6 ns
t5 tACLK_FT Audio clock fall time — — 6 ns
TDM Clock Timing
t6 tTDMCLK_P TDM clock period 40 — — ns
t7 tTDMCLK_LT TDM clock low time 14 — — ns
t8 tTDMCLK_HT TDM clock high time 14 — — ns T = 1/96 kHz X 256
t9 tTDMCLK_RT TDM clock rise time — — 6 ns
t10 tTDMCLK_FT TDM clock fall time — — 6 ns

Figure 18 Audio Master Clock and TDM Interface Clock Timing

ESS Technology, Inc. SAM0490-102902 37

 ES4008 DATA SHEET
MECHANICAL DIMENSIONS

MECHANICAL DIMENSIONS
The mechanical dimensions for the ES4008 are shown in
Figure 19.

D1

A2 A1

E E1 ES4008F
208-Pin PQFP e e1
L b L1

Millimeters
Symbol Description
Minimum Nominal Maximum
D Lead to lead, X-axis 30.25 30.60 30.85
D1 Package’s outside, X-axis 27.90 28.0 28.10
E Lead to lead, Y-axis 30.25 30.60 30.85
E1 Package’s outside, Y-axis 27.90 28.00 28.10
A1 Board standoff 0.25 0.33 0.42
A2 Package thickness 3.17 3.37 3.67
b Lead width 0.13 0.17 0.27
e Lead pitch — 0.50 —
e1 Lead gap 0.20 — —
L Foot length 0.35 — 0.75
L1 Lead length — 1.30 —
— Foot angle 0° — 7°
— Coplanarity — — 0.102
— Number of leads in X-axis — 52 —
— Number of leads in Y-axis — 52 —
— Total number of leads — 208 —
— Package type — PQFP —

Figure 19 208-pin Plastic Quad Flat Package (PQFP)

38 SAM0490-102902 ESS Technology, Inc.

ES4008 DATA SHEET

ESS Technology, Inc. SAM0490-102902 39


ORDERING INFORMATION
Part Number Description
ES4008F Home Theater Digital Audio Processor
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
40 http://www.esstech.com
No part of this publication may be reproduced, stored in a retrieval
system, transmitted, or translated in any form or by any means,
electronic, mechanical, manual, optical, or otherwise, without the prior
written permission of ESS Technology, Inc.
ESS Technology, Inc. makes no representations or warranties
regarding the content of this document.
All specifications are subject to change without prior notice.
ESS Technology, Inc. assumes no responsibility for any errors
contained herein.
U.S. patents pending.
© 2002 ESS Technology, Inc.
ES4008 DATA SHEET
ORDERING INFORMATION
Package
208-pin PQFP
MPEG is the Moving Picture Experts Group of the ISO/IEC. References
to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee
draft ISO 11172 dated January 9, 1992.
Dolby is a trademark of Dolby Laboratories, Inc. TruSurround is a
trademark of SRS Labs, Inc. All other trademarks are trademarks of
their respective companies and are used for identification purposes
only.
H.261 refers to the International Standard described in
recommendation H.261 of the CCITT Working Party 15-1.
SAM0490-102902