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Design of Impedance Measuring Circuits Based on Phase-Sensitive Demodulation Technique

Dixiang Chen, Wuqiang Yang, Senior Member, IEEE, and Mengchun Pan
AbstractImpedance measuring circuits play a crucial role in an electrical impedance tomography system, in which capacitance and resistance need to be measured accurately at a high speed. Several impedance measuring circuits based on phase-sensitive demodulation (PSD) have been designed, tested, and presented in this paper. The measurement error is analyzed, and the mismatch of the measured capacitance and resistance is considered to be the main cause of the measurement error. A new impedance measuring circuit with dual-frequency PSD has been designed to solve this problem. It has been proven by experiment that this circuit can be used to measure both capacitance and resistance with an uncertainty of less than 0.5%. Index TermsAnalog multiplier, dual frequency, dual mode, electrical impedance tomography (EIT), phase-sensitive demodulation (PSD).

Fig. 1.

Basic impedance measuring circuit.

Several multimode EIT systems have been reported with two sets of single-mode electrodes and their combinations [10][13]. Some drawbacks for a simple combination of singlemode electrodes are as follows [14]. 1) Two sets of single-mode electrodes result in complicated measurement channels and additional errors by the multiplexer. 2) If the capacitance electrodes used for ECT and the resistance electrodes used for ERT are positioned on the same cross section, the information of capacitance and resistance must be obtained sequentially since the coupling effect between two excitation signals has to be avoided by time sharing. 3) If the capacitance electrodes and resistance electrodes are positioned on two different cross sections, the information on details of a fast ow, which is obtained by the tomography system, may be invalid because of the time difference. An analytical model of sensors has been proposed for EIT [14], which can be used to obtain the information of both the conductivity distribution and permittivity distribution of a cross section of a pipe. In that paper, some details of the measuring circuit were given. Although phase-sensitive demodulation (PSD) circuits have been widely used in ECT and ERT systems [15][17], they have not been applied to achieve a dual-mode EIT system. This paper presents a new design of a dual-mode EIT system based on a PSD circuit, which should measure capacitance and resistance from an EIT sensor accurately at a high speed. Note that the primary objective of the work presented in this paper is to measure the capacitance and loss conductance. II. M EASUREMENT P RINCIPLES Fig. 1 shows a basic impedance measuring circuit, in which the measured capacitance Cx and resistance Rx are in parallel, Rf is a feedback resistance, Vi is a sine-wave input voltage, and Vo is the output of the measuring circuit.

I. I NTRODUCTION LECTRICAL impedance tomography (EIT) has been developed for industrial and clinical applications during the past decades as a visualization and measurement technique [1][6]. It can be used to reconstruct images of an industry process or part of a human body by determining the permittivity and/or conductivity distribution and, hence, material distribution over a cross section based on the electrical measurements. Compared with traditional tomography techniques, such as X-ray and -ray, EIT has several advantages, e.g., low cost, rapid response, portability, nonradiation, nonintrusiveness, and robustness [7], [8]. In most cases, EIT is based on the measurement of a single electrical property, i.e., permittivity for electrical capacitance tomography (ECT) or conductivity for electrical resistance tomography (ERT). However, the need for real-time imaging of complex processes involving multiphase components has motivated the development of tomography systems to exploit multiple electrical properties, resulting in multimode tomography systems [4], [9].

Manuscript received June 6, 2010; revised July 20, 2010; accepted August 21, 2010. Date of publication November 9, 2010; date of current version March 8, 2011. The work of D. Chen was fully supported by the China Scholarship Council for the academic visit at The University of Manchester in the U.K. The Associate Editor coordinating the review process for this paper was Dr. Theodore Laopoulos. D. Chen and M. Pan are with the School of Mechatronics Engineering and Automation, National University of Defense Technology, Changsha 410073, China. W. Yang is with the School of Electrical and Electronic Engineering, The University of Manchester, M13 9PL Manchester, U.K. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIM.2010.2084770

0018-9456/$26.00 2010 IEEE

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Fig. 2.

Switching-based PSD circuit.

In Fig. 1, the stray capacitance has been grouped together as Cs1 and Cs2 . Because stray capacitance Cs1 is driven directly by the voltage source, with a very small output impedance, it will not affect the impedance measurement. Because stray capacitance Cs2 is kept as virtual earth by the op-amp with no potential difference across it, it also has no effect on the impedance measurement. Therefore, this measuring circuit is stray immune [9]. The output of the circuit Vo consists of two components, one being in-phase and the other being quadrature-phase, i.e., with 90 phase shift [18] Vo = where Vin-phase Vquad-phase Rf = Vi Rx = Rf Cx Vi . Rf + jRf Cx Vi = Vin-phase + jVquad-phase Rx (1)

two complementary square-wave signals from a single square wave. It consists of a TTL buffer and an inverter. The driving TTL signal is synchronized to the input signal Vi . The two complementary square-wave signals drive either switches S2 and S3 to be closed (on) and switches S1 and S4 to be open (off) or switches S2 and S3 to be open (off) and switches S1 and S4 to be closed (on). When S2 and S3 are closed (on) and S1 and S4 are open (off), the PSD circuit functions as a unity-gain noninverting amplier. This is equivalent to multiplying the input signal by +1. When S1 and S4 are closed (on) and S2 and S3 are open (off), the PSD circuit functions as an inverting amplier. This is equivalent to multiplying the input signal by 1. When the input voltage Vi is a sine wave, the output of the op-amp Vo can be described by Vo = Vi = A sin(t + ), 0 < t < Vi = A sin(t + ), < t < 2 . (6)

(2) (3)

Obviously, the in-phase component Vin-phase represents the unknown resistance Rx , and the quadrature-phase component Vquad-phase represents the unknown capacitance Cx . If Vin-phase and Vquad-phase can be measured by a PSD unit, then Rx and Cx can be determined by Rx = Rf Vin-phase Vquadrature-phase Cx = . Rf Vi Vi (4) (5)

When a low-pass lter (LPF) with a sufciently low cutoff frequency is used, the average output of the PSD circuit can be calculated by 2 1 o = Vo dt + Vo dt V 2 1 = 2 =
0 2

A sin(t + )dt

A sin(t + )dt
0

2A cos .

(7)

A. Switching-Based PSD There are basically two types of PSD circuits, namely, switching-based PSD and analog multiplier-based PSD. Fig. 2 shows a detailed circuit of switching-based PSD. It consists of an op-amp and a switch-driving circuit. The op-amp is congured as a differential amplier. Four CMOS switches in a single IC (e.g., ADG412) are used to control the demodulation process. The switch-driving circuit is used to provide

This result indicates that the output of the PSD circuit is a function of not only the amplitude of the input sine-wave signal A but also the phase between the input sine-wave signal and the reference square wave. Fig. 3 shows the overall diagram of an impedance measurement circuit with switching-based PSD. In Fig. 3, the basic impedance measuring circuit is the same as in Fig. 1. The phase shifter can be adjusted to produce 0 and 90 phase shifts alternatively. An optimally designed

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Thus, the output of the analog multiplier can be expressed by VoR = kVo Vf R kA2 Rf kA2 Rf Cx sin(2t) = [1 cos(2t)] 2Rx 2 (14) VoC = kVo Vf C kA2 Rf 1 = sin(2t) kA2 Rf Cx [cos(2t) + 1] 2Rx 2 (15) where k is the proportional coefcient of the analog multiplier. When the passband gain of the LPF is 1, the dc output of the impedance measuring circuit can be expressed by oR = kA Rf V 2Rx
2 oC = kA Rf Cx V 2 2

Fig. 3. Impedance measuring circuit with switching-based PSD.

Fig. 4. Impedance measuring circuit with analog multiplier-based PSD.

fourth-order Butterworth LPF can provide 60-dB attenuation with 14-s settling time when the frequency of the sine-wave input is 500 kHz, and thus, only the dc component is remained. When the phase shift is 0 , the dc output of the measuring circuit is the in-phase component Vin-phase . When the phase shift is 90 , the dc output of the measuring circuit is the quadrature-phase component Vquad-phase . When the passband gain of the LPF is 1, Rx and Cx can be determined by Rx = Cx = 2ARf Vin-phase Vquadrature-phase . 2ARf (8) (9)

(16) (17)

oR represents the unknown resistance Rx and V oC where V represents the unknown capacitance Cx . Thus, Rx and Cx can be determined by Rx = Cx = kA2 Rf oR 2V oC 2V kA2 Rf (18) . (19)

B. Analog Multiplier-Based PSD Although the switching-based PSD can be used to measure the impedance, it is sensitive to the phase error. Inevitably, the CMOS switches have a time delay when they switch from on to off or from off to on, which will affect the accuracy of the impedance measurement. An analog multiplier-based PSD unit usually has better performance than a switching-based PSD unit. Fig. 4 shows the overall diagram of the impedance measuring circuit with analog multiplier-based PSD. In Fig. 4, the basic impedance measuring circuit is the same as in Fig. 1. The phase shifter can be adjusted to produce 0 and 90 phase shifts alternatively. Let us assume that the output of the function generator is Vi = A sin(t). (10)

C. Dual-Frequency PSD Due to the diversity and variability of the measured object, the measured resistance Rx and capacitance Cx would change in a large range. To achieve accurate measurements, a dualfrequency approach has been adopted [19][21]. Because the impedance of a capacitor will change with frequency, it is difcult to obtain accurate measurements of both the reactive and resistive components at a single frequency. In some measurement systems, only the resistive part of the impedance is recovered [19], and some useful information is lost. Fig. 5 shows a new impedance measuring circuit with dualfrequency PSD, in which two function generators are used to generate sine waves with different angular frequencies 1 and 2 , where is the initial phase. An adder is used to produce a composite waveform and then send it to the basic impedance measuring circuit. The output is sent to two analog multipliers at the same time. The in-phase reference voltage signal with angular frequency 2 is sent to the upper analog multiplier to produce the resistive component. A quadrature-phase reference voltage signal with angular frequency 1 is sent to the lower analog multiplier to produce the reactive component. This circuit can be used to measure the capacitance and resistance in parallel at the same time. The input of the basic impedance measuring circuit in Fig. 5 can be expressed by Vi = A1 sin(1 t) + A2 sin(2 t + ). (20)

According to (1), the output of the impedance measuring circuit can be expressed by Vo = ARf sin(t) ARf Cx cos(t). Rx (11)

The other input signal as a reference signal of the analog multiplier can be expressed by (12) and (13) when the phase shifter is adjusted to produce 0 and 90 phase shifts, respectively Vf R = A sin(t) Vf C = A cos(t). (12) (13)

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Fig. 5.

Impedance measuring circuit with dual-frequency PSD.

According to (1)(3), the output of the basic impedance measuring circuit can be expressed by Vo = Rf [A1 sin(1 t) + A2 sin(2 t + )] Rx (21)
Fig. 6. circuit. Input and output voltage waveforms of the switching-based PSD

Rf Cx [1 A1 cos(1 t) + 2 A2 cos(2 t + )] .

The reference voltage signal of two analog multipliers can be expressed by Vf R = A2 sin(2 t + ) Vf C = A1 cos(1 t). The output of the upper analog multiplier is VoR = kVo Vf R kA2 Rf = Rx (22) (23)

A1 cos(1 t 2 t ) 2 A1 cos(1 t + 2 t + ) 2 A2 A2 cos(22 t + 2) + 2 2 1 A1 sin(1 t + 2 t + ) kA2 Rf Cx 2 1 A1 + sin(1 t 2 t ) 2 2 A2 sin(22 t + 2) . + (24) 2

Fig. 7. Input and output voltage waveforms of the analog multiplier.

oC can be obtained by another LPF with Its dc component V the passband gain of 1
2 oC = kA1 1 Rf Cx . V 2

(27)

oR can be obtained by an LPF with the Its dc component V passband gain of 1 oR V kA2 2 Rf = . 2Rx (25)

Thus, the unknown resistance Rx and capacitance Cx can be determined by Rx = Cx = kA2 2 Rf oR 2V oC 2V kA2 1 1 R f (28) . (29)

The output of the lower analog multiplier is VoC = kVo Vf C = kA1 Rf Rx A1 A2 sin(21 t) + sin(1 t + 2 t + ) 2 2 kA1 Rf Cx A2 sin(1 t 2 t ) 2

It can be seen from (28) and (29) that the measurement results are independent to either the initial phase or the angular frequency 2 . III. E XPERIMENTAL R ESULTS AND E RROR A NALYSIS Several combinations of capacitors and resistors were measured by the impedance measuring circuits. Their true values were calibrated by an impedance analyzer HP4192A. A. Experimental Results With Switching-Based PSD and Analog Multiplier-Based PSD

1 A1 1 A1 cos(21 t) + 2 2 + 2 A2 cos(1 t + 2 t + ) 2 2 A2 cos(1 t 2 t ) . + 2

(26)

The impedance measuring circuits with switching-based PSD and analog multiplier-based PSD were tested under the

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TABLE I E XPERIMENTAL R ESULTS W ITH S WITCHING -BASED PSD

TABLE II E XPERIMENTAL R ESULTS W ITH A NALOG M ULTIPLIER -BASED PSD

following conditions. 1) The peak value of the input sine-wave voltage A is 5 V. 2) The frequency f is 1 kHz. 3) The feedback resistance Rf is 10 k. 4) The proportional coefcient of the analog multiplier k is 0.1. The input and output voltage waveforms (before the LPF) of the switching-based PSD circuit and the analog multiplier are shown in Figs. 6 and 7, respectively (the above is the input, and the following is the output). LPFs are designed to extract their average, which are dc signals. The input signals are generated by two function generators HP33120A. The dc output voltage of the impedance measuring circuit is measured by a multimeter HP34401A. The experimental results of the two impedance measuring circuits are shown in Tables I and II, respectively, in which Rx and Cx are the true values of the measured resistance and capacitance, Rm and Cm are the measured values, and Er and Ec are the relative errors of the resistance and capacitance, respectively. B. Experimental Results With Dual-Frequency PSD The resistance Rx and capacitance Cx with the true values of 9.93 k and 0.93 nF were measured by the impedance measuring circuit with dual-frequency PSD when the feedback resistance Rf is 1 k. Fig. 8 shows the output voltage waveforms of two multipliers when the frequencies of two input signals f1 and f2 are 10 and 1 kHz, respectively. Table III shows the experimental results when the peak values of the

Fig. 8.

Output voltage waveforms of two multipliers.

input sine-wave voltage A1 and A2 are 1 and 5 V, respectively. Table IV shows the experimental results when both A1 and A2 are 5 V. The dynamic range of this impedance measuring circuit is determined by the amplitude and frequency of two sine-wave input signals, which should be adjusted according to the measured impedance. Their full amplitude range is 10 Vp-p with a frequency range from 1 kHz to 1 MHz. The full-scale output range of the measuring circuit is dc 10 V. C. Error Analysis As commonly understood, the accuracy of the impedance measuring circuit with switching-based PSD is inuenced by the phase error, which is mainly caused by the time delay

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TABLE III E XPERIMENTAL R ESULTS W ITH D UAL -F REQUENCY PSD AND F IXED f1

TABLE IV E XPERIMENTAL R ESULTS W ITH D UAL -F REQUENCY PSD AND F IXED f2

Fig. 9.

Relative measurement error of the resistance.

Fig. 10. Relative measurement error of the capacitance.

of the CMOS switches and the inuence of the input capacitance of the op-amp in the basic impedance measuring circuit. The accuracy of the impedance measuring circuit with analog multiplier-based PSD is inuenced by the nonlinearity and accuracy of the analog multiplier. However, a simulation of the impedance measuring circuit with switching-based PSD reveals that the main reason of the impedance measuring error is the mismatch of the measured resistance and capacitance in parallel. The relative measurement errors of the resistance (Er ) and capacitance (Ec ) are shown in Figs. 9 and 10, respectively, in which R and XC are the impedances of the resistor and capacitor, respectively. It can be seen from Figs. 9 and 10 that the relative measurement errors of the resistance and capacitance reach the minimum at the same time when the ratio of resistance and

capacitance is one, and it will increase sharply with this ratio. Because the resistor and capacitor are in parallel, a smaller current will ow through the bigger impedance; then, there will be a bigger error because of the nonideality of the opamp. The dual-frequency PSD can be used to overcome this problem by changing frequency f1 (used for the measurement of the capacitance) to adjust the ratio of resistance and capacitance. Although frequency f2 (used for the measurement of the resistance) can be as low as 5 Hz in this impedance measuring circuit, an LPF with a lower cutoff frequency should be designed to eliminate the harmonics and measure the dc component. Because the data acquisition rate of an impedance measuring system is affected by the time constant of the LPF, f2 should be larger than 1 kHz.

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IV. C ONCLUSION Several impedance measuring circuits based on PSD have been designed and tested, aiming to construct a dual-mode EIT system. Although a more complex impedance model and some other error sources such as common-mode voltage should be considered in an EIT system, these impedance measuring circuits have the potential to measure the resistance and capacitance accurately at a high speed for industrial and clinical applications. Having analyzed their measurement errors, it has been found that the mismatch of the measured resistance and capacitance is the main source of impedance measurement error. In the impedance measuring circuit with dual-frequency PSD, two signals with different frequencies can be synthesized to excite the resistor and capacitor in parallel, and their impedance can be demodulated independently by the corresponding reference signals with different frequencies; thus, a suitable impedance ratio between the resistor and capacitor can be achieved. When the capacitance is measured, a higher frequency is used to reduce the impedance of the capacitor, which can improve the measurement accuracy of the capacitance. When the resistance is measured, a lower frequency is used to enlarge the impedance of the capacitor, which can improve the measurement accuracy of the resistance. This impedance measuring circuit can be used to measure both the capacitance and resistance with an uncertainty of less than 0.5% as conrmed by experiment. R EFERENCES
[1] T. York, Status of electrical tomography in industrial applications, J. Electron. Imaging, vol. 10, no. 3, pp. 608619, Jul. 2001. [2] J. W. Lee, T. I. Oh, S. M. Paek, J. S. Lee, and E. J. Woo, Precision constant current source for electrical impedance tomography, in Proc. 25th Annu. Int. Conf. IEEE EMBS, Cancun, Mexico, Sep. 2003, pp. 10661069. [3] K. Primrose and C. Qiu, Performance and application studies of an electrical resistance tomography system, in Proc. 1st World Congr. Ind. Process Tomography, Buxton, U.K., Apr. 1999, pp. 133139. [4] Q. Marashdeh, L. S. Fan, B. Du, and W. Warsito, Electrical capacitance tomographyA perspective, Ind. Eng. Chem. Res., vol. 47, no. 10, pp. 37083719, Jan. 2008. [5] J. B. Jia, M. Wang, H. I. Schlaberg, and H. Li, A novel tomographic sensing system for high electrically conductive multiphase ow measurement, Flow Meas. Instrum., vol. 21, no. 3, pp. 184190, Sep. 2010. [6] J. C. Gamio, W. Q. Yang, and A. L. Stott, Analysis of non-ideal characteristics of an ac-based capacitance transducer for tomography, Meas. Sci. Technol., vol. 12, no. 8, pp. 10761082, Aug. 2001. [7] K. G. Boone and D. S. Holder, Current approaches to analogue instrumentation design in electrical impedance tomography, Physiol. Meas., vol. 17, no. 4, pp. 229247, Nov. 1996. [8] F. Dickin and M. Wang, Electrical resistance tomography for process applications, Meas. Sci. Technol., vol. 7, no. 3, pp. 247260, Mar. 1996. [9] W. Q. Yang, Hardware design of electrical capacitance tomography systems, Meas. Sci. Technol., vol. 7, no. 3, pp. 225232, Mar. 1996. [10] G. A. Johansen, T. Froystein, B. T. Hjertaker, and O. Olsen, A dual sensor ow imaging tomographic system, Meas. Sci. Technol., vol. 7, no. 3, pp. 297307, Mar. 1996. [11] B. L. Wang, Z. Y. Huang, and H. Q. Li, Design of high-speed ECT and ERT system, in Proc. 6th Int. Symp. Meas. Tech. Multiphase Flows, J. Phys.: Conf. Ser. 147 , Jul. 2009, pp. 17. [12] B. T. Hjertaker, Static characterization of a dual sensor ow imaging system, Flow Meas. Instrum., vol. 9, no. 3, pp. 183191, Sep. 1998. [13] G. Steiner, Application and data fusion of different sensor modalities in tomographic imaging, Elektrotech. Inftech., vol. 124, no. 7/8, pp. 232 239, Aug. 2007. [14] Z. Cao, H. X. Wang, W. Q. Yang, and Y. Yan, A calculable sensor for electrical impedance tomography, Sens. Actuators A, Phys., vol. 140, no. 2, pp. 156161, Nov. 2007.

[15] R. W. M. Smith, I. L. Freeston, B. H. Brown, and A. M. Sinton, Design of a phase-sensitive detector to maximize signal-to-noise ratio in the presence of Gaussian wideband noise, Meas. Sci. Technol., vol. 3, no. 11, pp. 10541062, Nov. 1992. [16] C. S. Koukourlis, G. A. Kyriakou, and J. N. Sahalos, Differential synchronous demodulation for electrical impedance tomography, Clin. Phys. Physiol. Meas., vol. 13, no. A, pp. 3134, Dec. 1992. [17] A. V. Korjenevsky and T. S. Tuykin, Phase measurement for electric eld tomography, Physiol. Meas., vol. 29, no. 6, pp. S151S161, Jun. 2008. [18] W. Q. Yang, Teaching phase-sensitive demodulation for signal conditioning in lab to 2nd year undergraduate students, Amer. J. Phys., vol. 78, no. 9, pp. 909915, Sep. 2010. [19] A. McEwan, G. Cusick, and D. S. Holder, A review of errors in multifrequency EIT instrumentation, Physiol. Meas., vol. 28, no. 7, pp. S197 S215, Jul. 2007. [20] T. I. Oh, K. H. Lee, S. M. Kim, H. Koo, E. J. Woo, and D. Holder, Calibration methods for a multi-channel multi-frequency EIT system, Physiol. Meas., vol. 28, no. 10, pp. 11751188, Oct. 2007. [21] T. I. Oh, E. J. Woo, and D. Holder, Multi-frequency EIT system with radially symmetric architecture: KHU Mark1, Physiol. Meas., vol. 28, no. 7, pp. S183S196, Jul. 2007.

Dixiang Chen received the B.Eng., M.Sc., and Ph.D. degrees from the National University of Defense Technology, Changsha, China, in 1992, 1995, and 2005, respectively. He is currently an Associate Professor with the National University of Defense Technology. He has published over 70 scientic papers. His main research interests include advanced test systems, intelligent instruments, and nondestructive testing.

Wuqiang Yang (SM05) received the B.Eng., M.Sc., and Ph.D. degrees from Tsinghua University, Beijing, China, in 1982, 1985, and 1988, respectively. After being a Lecturer for three years at Tsinghua University, he joined the University of Manchester Institute of Science and Technology (now The University of Manchester), Manchester, U.K., where he is currently a Professor with the School of Electrical and Electronic Engineering. He is a Referee for over 30 professional journals, a Subject Advisor to the British Council Advisers College, a Science Advisor to the Chinese Academy of Sciences, a Visiting Professor at four universities, and a Qualied Expert in Intota (USA). He has published over 250 scientic papers, including review articles. His main research interests include industrial process tomography, particularly electrical capacitance tomography, image reconstruction, sensing and data acquisition systems, electronic circuit design, instrumentation, and multiphase ow measurement. Prof. Yang became a member of the Institution of Electrical Engineers (IEE) in 1997 and a fellow of IEE in 2004. He is a Chartered Engineer, an Editorial Board Member of four journals, a Guest Editor of two journals, and a Panel Member of the Natural Science Foundation of China. He is currently an IEEE Instrumentation and Measurement Society Distinguished Lecturer. He was the recipient of the 1997 IEE Measurement Prize, the 1997 Honeywell Prize from the Institute of Measurement and Control, and the 2000 IEE Ayrton Premium and was a 2009 IET Innovation Award Finalist. His biography has been included in Whos Who in the World, Whos Who in Science and Engineering, and Whos Who in America since 2002. He is recognized by the International Center for Scientic Research (France) as one of the top 30 technology researchers in the world.

Mengchun Pan received the M.Sc. and Ph.D. degrees from the National University of Defense Technology, Changsha, China, in 1992 and 2009, respectively. He is currently a Vice Director of the Department of Instrument Science and Technology, National University of Defense Technology. He has published over 100 scientic papers. His main research interests include advanced test systems, intelligent instruments, and nondestructive testing.