Getting Started With The XILINX Foundation F2

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GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

Contents
Design Flow Overview Types of Devices: FPGA and CPLD Project Manager Starting a new project: Schematic Entry a. Open a new project b. Schematic entry i. Placing symbols ii. Adding I/O Buffers, Pads or I/O terminals iii. Drawing lines iv. Adding pin locations v. Adding name, title and date vi. Netlist and integrity test vii. Saving schematic viii. Adding the schematic to project Entering a design with ABEL Entering a design with VHDL Simulating a design a. Functional simulation b. Timing simulation Macros and Hierarchical Schematics a. Macro from a schematic b. Macro with ABEL o c. Macro with VHDL d. Top level schematic Draw buses Bus Taps State Editor Design implementation User constraint file: Constraint Editor Configuring the device a. Using the Xilinx Demoboard b. Using the XC40 board FPGA EEPROM c. Using the X95 board Most common mistakes Board descriptions: FPGA Demoboard XS40 XS95 Pin outs: XC4000 - 84 pins XC9500 The Xilinx foundation (TM) CAE system is a development tool that consists of an integrated set of programs to create, simulate and implement digital designs in a FPGA or CPLD target device. All the tools use a graphical user interface (GUI) that allows all programs to be executed from toolbars, menus or icons. On-line help is available from most windows. This write-up is intended to get you started with the Foundation tools. It gives a quick overview of how to create a design, simulate it and download it into a FPGA or CPLD. For more detailed information please consult the on-line XILINX documentation and tutorials. The Foundation 2.1i User Guide is available on line.
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1.1 Design Flow Overview The design flow for CPLDs or FPGAs consists of three main steps as is illustrated in Figure 1. The design process can be broken down in (a) Design entry, (b) design implementation and (c) design verification.
Designs can be entered in two basic modes: Schematic and HDL (Hardware Description Language) mode. A hardware description language allows you to describe the behaviour of a system rather than as individual gates. There are several popular hardware description languages such as VHDL, Verilog and ABEL. The schematic flow mode allows you to create a design that consists of either a top-level schematic or top-level ABEL file. It can contain underlying schematic diagrams, state machine macros, instantiated HDL (ABEL, VHDL or Verilog) macros, LogiBLOX, CORE Generator modules. The HDL flow mode can contain a VHDL (or Verilog) or a schematic top-level design with underlying VHDL, Verilog, schematic modules, as well as LogiBLOX, CORE Generator and Finite State Machine modules. Notice that for a top level ABEL-based design, you will need to use the Schematic mode. In order to create VHDL or Verilog designs you will need the Synopsis FPGA Express package which comes with the Foundation Base Express and Foundation Express tools. Figures 2 and 3 show a more detailed view of the different steps involved in the creation of a design in the schematic flow mode and HDL flow mode, respectively. Notice the extra Synthesis step that is required in case of a HDL flow design. Also, the target device and the top-level module is specified during the synthesis step in the HDL flow mode. The implementation tools fit the entered design into the target device architecture. The tools compile a design file into a configuration file that is optimized in terms of use of logic gates and interconnections for the targeted device. Downloading of the bitstream can be done easily from a PC into a FPGA (using the Xilinx demoboard, the XS40 or XSV boards) or into a CPLD (on the XS95 board). Both devices can also be programmed in-the-system (ISP) by connecting a JTAG or XChecker cable to the device's programming pins. Design verification includes functional simulation, in-circuit testing, and timing simulation. Functional simulation can be done after the design entry to verify the proper operation of the circuit. However, functional simulation does not provide timing information, such as delays, race condition, set-up and hold-time violations. This information is obtained from the static timing simulator and is done after the design has been compiled for the target device. Figure 2 shows the design flow for a Schematic Flow project.
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Figure 3 shows the design flow for a HDL Flow project. The top-level module and the target device aren't specified until the Synthesis step as shown in the figure below.
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Figure 3: Overview of the design and implementation sequence of a HDL Flow project. [2]. 1.2 Types of Devices: FPGA and CPLD
There are two types of programmable logic devices. One is called a field programmable gate array (FPGA) and the other a complex logic device (CPLD). The CPLD XC9500 device has a PAL-like architecture and is non-volatile. It gives relatively good performance (up to 250 MHz) and is well suited for combinational logic circuits and control logic of medium complexity (up to about 10,000 logic gates). The FPGA device (ex. XC4000 series) has an array-like architecture and is volatile (SRAM based). It makes use of lookup tables (stored in the SRAM memory) to implement logic functions. It is good to realize complex logic functions that contain both combinational and sequential circuits. Its capacity is usually limited by the number of input/output pins and not by its complexity. FPGAs can currently implement up to 1 million logic gates and operate up to 150 MHz. The XC4000XL and XC9500XL are 3.3V devices with a 3.3V Vcc but with 5V tolerant I/Os. The devices come in a variety of packages. The ones used on the FPGA demoboard or the XS40 and XS95 boards are packaged in an 84 pin PLCC and have the following part names: XC4010EPC84, XC4005XLPC84 and XC95108PC84 . To find out which device you will be using, check the board you have available in the lab. Detailed information on these devices is given in the Xilinx
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Programmable Logic Data Book. The pin outs of the XC4000 and the XC9500 84-pin devices are available on the tutorial webpage. 1.3 Project Manager
When you launch the Foundation tools, the Project Manager window will open as is shown in Figure 4 for a Schematic Flow project. The Project Manager gives you access to all the tools that are needed to design, simulate and implement a project. From the Manager you can also create a new project, open an existing project or delete projects. You can launch the Xilinx Project Manager by going to the START/PROGRAMS/Xilinx Foundation Series 2.1i menu. You can also click on the Project Manager icon at the bottom toolbar.
When you create a new project e.g. MyProj, the Foundation tools will create the following files: a project configuration file (PDF), called Project Description File (myproj.pdf), and three library files, the project library file (myproj), the simulation library file (simprims) and the device library (xc4000x) files. The libraries are shown in the left window pane (called the Hierarchy browser) of the Project Manager. A project must always have one or more top level design files. In case the top-level cell is a schematic, the file will be shown in the hierarchy browser with an extension .sch (e.g. myproj.sch) as can be seen in Figure 4 above. The foundation tools will create additional folders and files during different stages of the project design/implementation.
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The right window pane in the Project Manager has several tabs. The Flow tab graphically shows the different steps involved in the design of a project as was shown schematically in Figure 2. You can click on the icons to access a particular tool as will be shown later on. The bottom window pane gives status and error or warning messages. The different features of the Project Manager will become clear later on when doing the tutorial exercises. For more information, go to the HELP -> PROJECT MANAGER HELP TOPICS menu. In case a library is missing (e.g. the device library), the tools will give you a warning. This will also show up when you try to open the schematic, as symbols will be missing or blanked out. If that happens, you can add the library to the project. In the Project Manager, go to FILE ->PROJECT LIBRARIES. This will open the Project Libraries window, shown in Figure 5. The left side panel shows the "Attached Libraries" and the right side windows the Project Libraries, such as myproj, xc4000x and simprims. If any of these are missing, you can add them from the list in the left side window. Scroll until you find the right library (e.g. XC4000X) and click the ADD button.
If the required library does not show up in the left side window, you need to attach the library first. Click the Lib Manager button to open the Library Manager. Go to the LIBRARY -> ATTACH menu to open the Attach Library. You can now select the required library and click the OK button. The systems' libraries are usually found in the c:\fndtn\active\syslib directory. The newly selected library will appear in Attached Library list. You can now add the library to your project. Notice that libraries which are already attached will not be displayed in the Libraries list. 1.4 Creating a new project: Schematic Entry
The design entry is the first step in the process of creating a new design. Design can be entered either as a schematic or as a text-based entry (ABEL, VHDL or Verilog). An overview of the overall process of creating a design in the Schematic Flow mode is shown in Figure 2 of the introduction section. In this tutorial you will learn how to create a new project and enter a design using the Schematic Editor in the Schematic Flow mode. In later sections you will learn how to create more complicated projects using macros and hierarchies. For now let us assume you want to build a really simple circuit, as shown in Figure 1, using the Schematic Editor. This circuit will be used in a car to generate a warning signal when "The Ignition key is in the lock AND the door is open OR the seatbelt is not used". The corresponding Boolean expression is: F = IGNITION.(DOOR' + SBELT')
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1.4.1
. Open a new project
To start the Xilinx Foundation tools (click on the icon on the desktop or go to the window's START menu -> Programs -> Xilinx Foundation Series F2.1i-> Project Manager). First, a small window will pop up asking to open an existing project or to create a new one. Select "New Project". This will bring up the new project window
Fill out the name of the project, the directory where you want to store the project, and the Type. Let's give it the project Name: EasyProj . The project name is not case sensitive. Do not use more than 8 characters in the project name. Directory: Select the proper directory (folder) where you want to save your project. Use the Browse button to change the directory. For the type select F2.1i. Under Flow, select Schematic flow since we will use the Schematic editor to create our design. The three pulldown boxes at the bottom of the New Project window refer to the device family, the part and the speed grade. The family refers to the device family. If you are using a FPGA, select XC4000E (for the FPGA demoboard) or XC4000XL (for the XS40 board); if you are using a CPLD, select XC9500 (for the XS95 board).
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The second box is for the part which refers to the specific target device. Check the type of device you have on the board. The XS40 FPGA board will probably be populated with the XC4005XL-3PC84C; the XC95 board with a a 95108PC84 CPLD; the FPGA Demoboard with a 4010EPC84. Select the proper Part depending on the device you work with. You can change the target device at a later time by going to the FILE -> PROJECT TYPE in the Project Manager window (Figure 3). The speed refers to the speed specification of the device and can be found on top of the device following the "-" after the device name (ex. XC4010E - 3 indicates a speed 3).
The Project Manager window will open as shown inFigure 3. This window shows the design flow as well as the associated tools.
Figure 3: Xilinx Foundation Project Manager window (Schematic Design Entry) (Screen clip from Xilinx (TM) Foundation software) The project will have a .PDF extension. Other project files such as schematics, netlists, macros, etc., will be stored in a subdirectory with the project name. A project can have only one top schematic (or HDL source file). Sub-schematics can be added to the project as macros. For more information about the Project Manager, use the online help function by selecting HELP -> PROJECT MANAGER FOUNDATION HELP CONTENTS in the Project Manager window. To access the Foundation 2.1i User Guide, go to the HELP ->ONLINE DOCUMENTATION menu. Next, click on the WEB BOOKS button and on Foundation Series 2.1i Software link. 1.4.2 b. Schematic Entry
To create the circuit of Figure 3.1 using the Schematic editor, click on the Schematic editor icon in the Project Manager window or select the TOOLS menu -> DESIGN ENTRY -> SCHEMATIC EDITOR. A Schematic Capture window will appear as in Figure 4.
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Figure.4: Xilinx Foundation Schematic Capture window with blank schematic (Screen clip from Xilinx (TM) Foundation software) i. Placing symbols You can add the logic symbols by clicking on the Symbol Toolbox (Symbols icon) on the toolbar on the left. An SC Symbols Toolbox will pop up. You can scroll down the list and select AND2 or type the symbol name at the bottom box of the list. Notice that a brief description of the selected symbol appears at the bottom. You can now place the gate with your cursor on the schematic by clicking the mouse. To place another AND gate just click on the previous one and a second gate will be attached to the cursor. Every time you click another gate of the same type will be placed in the schematic until you press the Escape (ESC) key.. Place two 2-input NAND gates. Next, select OR2 from the SC Symbol Toolbox and drop one OR gate. Figure 5 shows the schematic with the symbols added.
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Figure 5: Xilinx Foundation Schematic Capture window with Symbols added (Screen clip from Xilinx (TM) Foundation software). You can mirror a symbol by pressing Ctrl+M keys or rotate it by pressing the Ctrl+L keys. To redraw the screen press the F10 function key.
Side note: The FPGA (not the CPLD) comes with an on-chip oscillator of 8 MHz. This can be used by placing the symbol OSC4 in the schematic (or HDL code). An internal divider makes the following signals available: 8MHz, 500 kHz, 16 kHz, 490 Hz and 15 Hz. The frequencies are not very well defined and can vary between -50% and +25%. ii. Adding I/O buffers, pads and I/O terminals FPGAs and CPLDs have input/output blocks that act as an interface between the internal circuitry and the pins which connect to the external world. The I/O block can be configured by the user. It consists of input and output buffers (designated by the library symbols IBUF and OBUF), tri-state output buffer (OBUFT) and flip-flops (edge-trigger D flip flop (IFD) or a latch (ILD)). Buffers: Buffers are needed for input and output signals which go to a pin of your device (FPGA or CPLD). Place the buffers on the schematic in a similar fashion as you did for the other symbols. For the input buffers select the IBUF symbol and for the output buffer select OBUF from the SC Symbol list. In case you would like to add a tri-state buffer, you can select OBUFT. Do not forget to add buffers or your schematic will not compile later on! Pads: You will also need to add I/O pads to the input and output buffers. These pads represent the actual pins on the XILINX device. A pad is a physical component in the Xilinx Unified Library and is placed like any other component (ex. AND, NAND, etc.). The names of pads are IPAD (input), OPAD (for output), IOPAD (bi-directional), IPAD4 and OPAD4, etc. All device pins MUST be represented with one of these I/O pads! Pads should be given a name and possibly a pin number (pin location). This can be done by double clicking on the pad to bring up the Symbol Properties window (see Adding pin locations below). Output pads are pulled-high or pulled-low through a pull-up or pulldown resistor of about 10 kOhm, respectively, when not in use to prevent floating outputs. During normal operation, the pull-up/down is deactivated.
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Pins An I/O terminal (pin: ), which is available by clicking on the I/O Terminal button at the bottom of the left-hand side toolbar or at the top of the SC Symbols window, is not a physical device and cannot be used as an I/O pad (although, sometimes the software may treat it as an I/O pad, but there is no guarantee). I/O terminals should only be used to provide connections between levels of hierarchy in the design. Thus they are used in macros to connect signals to the corresponding pins on the macro symbol. However, signals that span multiple pages of a flat design do not require terminals or off-page connectors. To indicate device pins on the top-level schematic in a hierarchical design, one should not use I/O terminals but pads to indicate device pins. If the schematic is going to become a cell or macro that will be used later on in a larger schematic you need to use I/O terminals to indicate the terminals of the device. As explained above you can add an I/O terminal (pin) by clicking on the Hierarchy Connector icon and entering the name of the terminal. For macros, you don't need to place buffers in the schematic (IBUF or OBUF) since the inputs and outputs will not be connected to a physical pin of the FPGA or CPLD. For macros or hierarchical design, see the section on "Macros and Hierarchical Schematics". iii. Drawing lines and naming wires To connect one gate to the other, use the Draw Wire feature. This can be done by clicking on the wire symbol just below the Symbol Toolbox icon of the left side toolbar. All symbols must be connected with wires. Nets (wires) should be user-defined for readability and documentation purposes. You can name a wire by clicking on the "Name Wire Icon" just below "bus" icon on the vertical toolbar. Type in a name in the Net Name window and put the cursor over the location of the wire. Make sure you point to the wire that you want to name, otherwise the name will not be connected to anything. A shortcut to naming nets is double clicking on the net. You can now fill out the net name between the pads and buffers for the three inputs (DOOR, IGNITION AND SBELT) and the output (BUZZER). Net names should appear in blue (green names indicate that the name is not connected to a net). iv. Adding pin locations You can assign pin numbers to each input and output pad. If you don't do this, the compiler will assign the pin numbers for you. There are two ways you can assign pin numbers. First, you can place the pin numbers on the schematic using the LOC or Description property. This is done by double clicking on the PAD symbol. In the pop-up Symbol Properties window (Figure 6), go to the Parameters section and enter as Parameter Name: LOC, and for the Parameter Description: P#, in which # represents the pin number as shown in Figure 6 (the letter P is required in front of the number). Click on the ADD button. To display the pin location, double click on the LOC=P44 until two diamonds appear next to it. When finished click OK. The name can be moved by double clicking on the pad until the Symbol Properties window appears. Select LOC=P# and select MOVE. You can now move the pin location label around.
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Figure 6: Symbol Properties window to assign pin locations (Screen clip from Xilinx (TM) software window) An alternative way is to not assign pins on the schematic, but specify the pin numbers later, before compiling the design. This can done by creating a User Constraint File (see constraint editor section). The advantage of the latter method is that the schematic is more generic and you can easily change pins without having to modify the schematic (or the HDL code). When using the Demoboard, the XS40, or the XS95 boards, certain pins have been pre-assigned and some are connected to LEDs and switches for ease of testing (consult the descriptions of the Demoboard, XS40 or the XS95 boards). Assign the pin numbers so that you can make use of these devices. The pinouts of the 84 pin PLCC XC4000 and XC9500 devices are available on the web. In case you are using the XS40 board, you can connect the inputs "DOOR", "IGNITION" and "SBELT" to the pins of the parallel port connector (e.g. pins 44, 45 and 46, respectively - see Table 1 of the XS40 board description) and the output to one of the LED segments (e.g. segment "a" or pin 19). Figure 7 shows the finished schematic.
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Figure 7: Schematic of the finished circuit including pin numbers locations (Screen clip from Xilinx (TM) Foundation software. v. Add your name, title of project and date It is good practice to label the schematics clearly. There is a standard way of doing so. Go to the bottom of the page and fill out the small rectangle. If the box has a predefined name, you can change this by going to the FILE->TABLE SETUP. You can now change the address, Name, Description, Date, etc. vi. Netlist and Integrity Test You will need to generate a netlist which is in a format that is readable by the compiler. This is done by going to the OPTIONS menu-> CREATE NETLIST. When finished, it is always a good idea to check that the schematic has no electrical design rule errors. This is done from the OPTIONS menu > INTEGRITY TEST. You can now also generate a EDIF netlist by going to the OPTIONS menu -> EXPORT NETLIST. If you don't do this, do not worry - the system will prompt you later to do so. vii. Save your schematic Go to the FILE menu -> SAVE or click the floppy disk icon on the top toolbar. Give your schematic a name with the extension .SCH (ex. EASYPROJ.sch). When finished with the schematic, exit the Schematic capture program which will bring you back to the Foundation Program Manager window (Figure 3.3). viii. Adding the schematic to the project If the created schematic is not listed in the Project Manager window under the Project you created (ex. easyproj1.sch), you have to go to the DOCUMENT menu -> ADD in the Project Manager window. A window with a list of files will appear. To show only the type "Schematic" display *.SCH in the dialog window. Then select the schematic (EASYPROJ.sch) you would like to add to your project (EasyProj). ix. Copy your project to another disk. If you want to save your project on another disk (e.g. floppy disk) you can to do this from within Xilinx. Go to the Project Manager. Open the FILE->COPY PROJECT menu. Give the name of the Drive and directory to which you would like to copy your project.
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You can also archive your project as a ZIP file. In the Project Manager, go to FILE -> ARCHIVE PROJECT. This will open the Archive Project Wizard window. The zip file is convenient when you need to email your project or when the file is too large to store on a disk. The next step is to simulate or compile (implement) the circuit. For more information, go to the HELP -> SCHEMATIC EDITOR HELP CONTENTS menu in the Schematic Editor window. You can also read the "Design Methodologies - Schematic Flow" in the Foundation Series 2.1i User Guide. Check also the "most common mistakes" section. 1.5 Design Implementation
The implementation tools will translate the netlist (schematic, HDL), place and route (or fit for CPLDs) the design in the target device and generate a bitstream that can be downloaded into the device. The implementation is typically done, after the design has been verified by the functional simulator, as shown in Figure 1 below. Implemenation needs to be done prior to doing a timing simulation, since timing information depends on a specific target device and the way the design has been placed and routed on the device (See Figures 2 and 3 of the introduction).
Figure 1: Overview of the Design Flow. a. Implementation Go back to the Project Flowchart in the Project Manager window. If this is the first time you implement the design, click on the Implementation icon in the flow section of the Project Manager window. This will open the Implement Design window, shown in Fig. 2 below. If you have implemented earlier an earlier version and would like to create a new revision or new version, go to the PROJECT -> CREATE REVISION or CREATE VERSION menu. This will open the Create Revision or Version window, similar to the Implement Design window shown in Fig. 2. The Implement Design Window lets you specify the target device and speed grade. In case you get a message saying "Schematic Netlist is older than the Schematic. Update netlist from Schematic Editor?", click the YES button. The target device is already specified as 4005XLPC84 as this is the one we selected when the project was created. If needed, you can change the target device. The Revision and Version name is automatically filled in with rev1 and ver1. You can change the name if you want to. The implementation options allow you to specify how the design is optimized, mapped, placed, routed and configured. In general, the default settings should be good enough for introductory lab exercises. When you click on the SET button, the Settings dialog box will open. This allows you to specify control files such as a specific Constraint, Guide or Floorplan files. The default settings are usually fine. In case you are using the HDL Flow mode for your project, the Implementation Settings window will open. Click on the RUN button to start the implementation process.
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Figure 2: Implement Design Window (Screen clip from Xilinx (TM) Foundation software) Note: If you need to switch to another device family, you can do so by going to the FILE -> DEVICE TYPE menu in the Project Manager window. The change Project Type window will pop up. Under Flow, select the new device type (ex. XC9500 in case want to switch to a CPLD device). When you click on the RUN button in the Implement Design window, the Flow Engine window will open and display the progress through the different steps in the implementation process. Figure 3 shows the Flow Engine window in case the target device is a FPGA.
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Figure 3: Flow Engine window for a FPGA target device (Screen clip from Xilinx (TM) Foundation software) The first step is the translation of the design file (EDIF file) in a proper format (NGD file - Native Generic Database). This implies that the representation of your schematic (gates) or HDL file is translated into FPGA elements corresponding to the target device (look-up tables, etc). The next step is mapping of the design to the specific target device. The mapper optimizes the logic, trims or "optimizes out" (removes) logic and maps the design in the targetted FPGA device. Next is the Place&Route operation, followed by the generation of the timing information for use by the timing simulator. The final step is the generation of the Bitstream which is a configuration file that can be used to program the FPGA. In case you want to program a PROM, you will run the bitstream through the PROM File Formatter. You can follow the status of each step in the Flow Engine window. When the implementation is complete a small window will pop up informing you that the Flow Engine is Completed Successfully. Click OK. In case errors occurred you should refer to Implementation Log file, in the Project Manager (click on the Reports tap on top of the right window pane), as shown in Figure 4 below. In the hierarchy browser (left pane window) of the Project Manager, click on the Versions tab and you will see the status of the implementation.
Figure 4: Project Manager showing the status of the implemented version and the reports. (Screen clip from Xilinx (TM) Foundation software) In case you are targeting the design for a CPLD device, the Flow Engine looks like the one in Figure 5. The bitstream generates a .jed file..
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Figure 5: Flow Engine window for a CPLD device. (Screen clip from Xilinx (TM) Foundation software) For a CPLD the .jed (bitstream) needs to be first tranlsated into a format that is compatible with the CPLD device before it can be downloaded. This is done as follows. In the Poject Manager, click on the Programming Icon in the Flow section, or go to TOOLS -> DEVICE PROGRAMMING -> JTAG PROGRAMMER. The JTAG Programmer window will open, shown in Fig. 6.
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Figure 6: JTAG Programmer Window (Screen clip from Xilinx (TM) Foundation software) In the JTAG Programmer window, go to OUTPUT -> CREATE SVF FILE. In the SVF Options window, select the " Through Test-Logic-Reset" radio button and click OK. Save the my_proj.svf file. You can save it in any directory, but the easiest is to save it in the directory corresponding to the revision and version of the current project. You will need to remember later where you saved the .svf file for programming the CPLD. Next, go to OPERATIONS -> PROGRAM in the JTAG Programmer window. Select "Erase Before Programming" and click the OK button. When the operation is successfully you will get the following message "All operations were completed successfully". Click OK. button Close the JTAG Programmer window. The .svf file can be used to configure the CPLD.
b. Viewing the Implementation Results You can also view the reports from the Project Manager (Fig. 4). Reports are associated with each version. In the Project Manager, click on the Versions tab in the left-hand pane. Select the version and revision for which you would like to see the reports. You can then click on the Report Browser icon on the top toolbar. Or you can also click on the Reports tab in the right-hand window pane. Next, double click on the Implementation Report Files. This will open the report browser window. In case you are using a FPGA target device, you will see the Translation, Map, Place&Route, Pad reports and others. Click on the Pad report to see the assignments of the I/O pins. You will recognize the same names as the ones you specified on the schematic (Door, Ignition, Sbelt and Buzzer). Check the pin locations. Another interesting report is the Map report which will tell you if logic has been removed (as part of the optimization) or added. The Place&Route report indicates how much of the device has been utilized. It gives also a rough estimate of the average interconnection delay.
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In case you have implemented your design on a CPLD the Translation, Fitting and Post Layout Timing reports will be generated. Open the Fitting report to check the pin locations of the input and output signals. c. Constraint Files: Assigning pins with the user constraint files: Constraint Editor There are two types of constraints: (1) location and (2) timing. In general location constraints allow you to control mapping and positioning of logic elements in the target device, such as the location of the pads (I/O pins). Timing constraints inform the system which paths are critical and need short interconnections (high speed lines) in order to ensure that your design's performance functions properly under worst-case conditions. You can also specify the slew rate (fast or slow) and to use pullup or pulldown resistors for the output pads. We will concentrate on the location constraints. More information can be found from the HELP -> FOUNDATION HELP CONTENTS: Entering Constraints. Constraints can be entered in various ways. One way is to place constraints on the schematic or in the ABEL file, as we have done with the pin location. Other ways are to use the Constraint Editor or edit the user constraint file (projectname.ucf) directly. Constraint Editor If you did not assign pin numbers to the input and outputs in your schematic (or HDL code), you should do it now, before compiling the design. If you don't assign the pins, the compiler will assign them for you. When using the Demoboard, or the XC40 or XC95 boards you should assign the pins yourself to make use of the on board switches and LEDs on the FPGA demoboard, or the XS40 and XS95 boards. The Constraint Editor is a Graphical User Interface that you run after the translate program. Notice that you can access the Constraint Editor only after you have created a version of the project and thus after running the tranlation once. Using the constraint editor can be a littel confusing in particular when you have created different versions. You need to make sure that you are editing and using the right constraint file. Follow the instructions carefully: To open the Constraint Editor, go to TOOLS -> IMPLEMENTATION -> CONSTRAINT EDITOR in the Project Manager window. In case you have created different versions or revision, you should first go to the Version Tab in the left window pane of the Project Manager. Select the version you would like to work with. Then click with the right mouse button and select "Edit Implementation Constraints". The Editor window will open. It consists of a main window and three tab windows, called Global, Ports and Advanced. We are interested in specifying pad locations. Click on the Ports tab which will open the Ports window as shown in Figure 7. At the top of the window you will see a list of all the port names you have specified in the schematic as well as the location (if you specified any). To change the location, or to add a location, click with the right mouse button on the Port Name. A small window will pop up that allows you to type the (new) location as P# (note: use capital P). For our example, the pin location should be BUZZER (P19), DOOR (P44), IGNITION (P45) and SBELT (P46), in case you are using the XS40 board. Don't forget to put "P" in front of each pin number. Alternatively, you can type the pin location directly in the Location column. When finishedentering all the pin locations, go to FILE -> SAVE. When you get a message saying "You must rerun the Translate Step to have your new constraint applied to the design", click OK. For more information about each constraint, use the on-line help in each dialog box or go to the HELP -> HELP TOPICS menu in the Constraint Editor window.
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Figure 7: Constraint Editor window (Screen clip from Xilinx (TM) Foundation software) In order for the system to use the new constraint file you have to re-run the tranlate operation. This is done by going back to the left window pane (versions tab) in the Project Manager and selecting the same Revision and Version for which you have defined the contraints. Place the mouse over the revision/version name and click the right mouse button. Select "Invoke Interactive Flow Engine". This will open the Flow Engine window. You may have to back up to make sure that you redo the translation step (in order to use the modified constraint file). Start the implementation including Translate, Map, etc. When the implementation is successful check the Pad report or Fitting report (corresponding to the version you just implemented) to make sure the pads have been properly placed as specified in the new user constraint file, in case of a FPGA or CPLD, respectively.
When you create a new version or revision a window like the one in Figure 2 will pop up. To make sure you are using the right user constraint file, click on the SET button. When the Settings window opens, you can select the desired user constraint file (ucf) by using the pull-down box for the "Use contraint file from" menu (see Figure 8). Use "custom" to browse the directory. If you do not specify a ucf file, the one corresponding to the last revision will be used.
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Figure 8: Setting window that allows you (Screen clip from Xilinx (TM) Foundation software)
to
specify
specific
user
constraint
file.
You can also use the Constraint Editor to specify whether an output should have a Pullup or Pulldown resistor, and have a Slow or Fast slew rate. You can specify these by clicking on the I/O Configuration Option box. This will add a few columns to the Ports window. You can now specify the Slew Rate and Pullup/Pulldown option using the pull down menus in the corresponding colums. Edit the User Constraint File An alternative way to specify constraints is to edit the user constraint file directly after you have run the translate program once. This file has the same name as the project with a .ucf extension. The easiest way to edit the .ucf file is by using the HDL editor, by clicking on the HDL Editor icon in the Project Manager, or by going to TOOLS -> DESIGN ENTRY -> HDL EDITOR menu. Select "Open Existing Document". The user constraint file is located in the xproj folder, inside the corresponding version/revision folder. You will notice that the existing .ucf file contains a lot of comments explaining how to create a constraint file. Right now we are interested in defining pin locations. Scroll to the bottom of the file and add the pin locations as follows. NET "BUZZER" LOC = "P19"; # output: DOOR NET "DOOR" LOC = "P44"; # input NET "IGNITION" LOC = "P45"; # input NET "SBELT" LOC = "P46"; # input Be careful - the constraint file is case sensitive. Make sure you use exactly the same name in the constraint file as the one you have defined in your schematic or in the HDL file. The "#" is used for comments. When done, save the file. You can now re-run the implementation tools by selecting the version in the left window pane (versions tab) of the Project Manager. Click on the version with the right mouse button and select "Invoke Interactive Flow Engine". Start the Flow Engine. When finished successful, check the Pad or Fitting report to make sure that the right pin locations have been assigned. d. Create Design Version and Implementation version
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If you want to create a new version or new revision, go to the Project Manager. Select PROJECT -> CREATE VERSION or CREATE REVISION. This will bring up the Create Version or the Create Revision window. These windows look similar to the Implement window discussed earlier. You can specify which constraint file to use by clicking on the SET button next to Control File. Use the pull down menu to select a contraint file from a previous version/revision, as shown in Figure 8. If you do not specify a constraint file it will use the constraint file of the last revision. The versions will appear in the left hand window pane of the Project manager, under the Version tab. Once a new version or revision has been created you can run the implemenation program. e. Looking at the Floor Plan You can use the FPGA Editor to look how the device's resources have been use and placed on the FPGA. You can also use this application to place and route critical components before running the automatic place and route tools on your design. To open the FPGA editor, go to the Project Manager, and select TOOLS -> IMPLEMENTATION -> FPGA EDITOR. The Editor allows you to display different levels of details on the FPGA such as short wires, long wires, switch boxes, routing between components, components, etc. The level of detail that is displayed can be controlled by clicking icons on the top level toolbar. Figure 9 shows the FPGA editor window with a view of the FPGA floorplan, around the area where the logic circuit has been placed. The three blue boxes are the I/O blocks of the DOOR, IGNITION and SBELT signals, and the red one is the logic block. The switching network and the routing of the signals to the logic block are shown as well.
Figure 9: FPGA Editor window with view of the floorplan for the logic circuit of Fig.1 (Schematic Entry section). (Screen clip from Xilinx (TM) Foundation software)
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To look at a particular block on the FPGA, you can zoom in by clicking on the maginifying glass on the top toolbar. The bottom left window, labeled World shows a red dot that correspond to the signal that you selected in the List window on top. By moving the white rectangle and placing it on top of the desired signal (red dot) you can zoom into the specific block in the left window, shown as a red rectangle. You can now double click on the red block in the left window to see more details of the selected component. For more information about the FPGA Editor, select HELP -> HELP TOPICS from the FPGA Editor window. In case you are implementing your design on a CPLD, you can use the Chip Viewer to see how the resource inside the CPLD has been used. The ChipViewer tool allows you to examine inputs and outputs, macrocell details, equations, and pin assignments. You can examine both pre-fitting and post-fitting results. To start the tool, go to TOOLS -> IMPLEMENTATION -> CPLD CHIP VIEWER in the Project Manager window. For additional information go to the HELP -> HELP TOPICS menu in the Chip Viewer window. References: 1. "Foundation Series 2.1i User Guide chapters on "Foundation Constraints" and "Design Implementation", available on the Xilinx website. 2. Foundation Series online help, "Entering Contraints" (in the Project Manager go to HELP -> FOUNDATION HELP CONTENTS). 3. D. Van den Bout, "The Practical Xilinx Designers Lab Book", Prentice Hall, Upper Saddle, NJ, 1998
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1.6 Entering a VHDL-based Design
An alternative way to using the Schematic or the ABEL editor is to enter a VHDL/Verilog-based design . In this section you will learn how to enter a VHDL-based design using the HDL-flow mode. If you are not familiar with VHDL, consult the VHDL Reference Guide (on the Xilinx web site) or a textbook on VHDL. Figure 1 shows schematically the different steps involved in the creation of a HDL-based project.
Figure 1: Overview of the design and implementation sequence of a HDL Flow project. In this tutorial you will learn how to enter and synthesize a VHDL based design. Once you have synthesized the VHDL file, the remaining steps of implementation and downloading will be identical as the ones for the Schematic Flow mode. i. Open a Project in the Foundation Project Manager If you are not in the Foundation Project Manager, open it now and create a new project called EasyVHDL. We will create the same logic function as was done before in the Schematic Entry section (circuit of Figure 2). Go to the FILE -> NEW PROJECT menu. In the pop up window, select for flow
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"HDL". The family and part pull down menus will not be displayed, since you will specify this later during the synthesis process (Figure 1 above).
Figure 2: Logic circuit to be implemented as a VHDL file. ii. Create a VHDL Design and assign port names with the HDL Wizard In the Foundation Project Manager, click on the HDL Editor icon or go to the TOOLS -> DESIGN ENTRY ->HDL EDITOR menu. Select HDL Design Wizard. In the Design Wizard window click NEXT and go to the Design Wizard Language window. Select VHDL as the design language. Click on NEXT button which will open the Design Wizard Name window. Enter the name of your design. Lets call it EasyVHDL. You can give it another name, but the name should not be larger than 8 characters. Then click NEXT. The Design Wizard Ports window will appear showing a symbol on the left. Follow the instructions in this window. You can create here the input and output pins (ports). Use the same names as you did for the schematic of Figure 2 (DOOR, IGNITION, SBELT and BUZZER). Click on the NEW button and enter the Name, select as Direction Input or Output, depending on the type of port. For output pins you go to the ADVANCED button which will open the Advanced Port Setting windows. Select STD_LOGIC. When done, click on the FINISH button. The HDL Editor window will open at this point. iii. Create the Source with the VHDL Editor The HDL editor window will open a template which contains the Entity and Architecture section. The Entity section contains the input and output Port declarations made in the previous step. You should verify that all the inputs and outputs are present. The Architecture section contains the logic description of the circuit. Logic descriptions can be entered in a variety of ways: Equations, Truth Tables, and State Description (for sequential circuits). We will be using an equation to define the logic function of Figure 2. Under the Architecture section (<<enter your statements here>> ) type the following equation: BUZZER <= IGNITION and (not DOOR or not SBELT); Figure 3 gives the VHDL source file for the circuit of Figure 2.
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Figure 3: VHDL Editor window for the circuit if Figure 1 (Screen clip from Xilinx (TM) Foundation software) To find out more about the VHDL syntax click on the Language Assistant icon on the top right the toolbar, or select TOOLS -> LANGUAGE ASSISTANT. This will bring up a window with language and synthesis templates. The language templates shows basic language constructs while the synthesis templates give the code of functional blocks such as counters, multiplexers, adders, flip-flops and architectures features such as Boundary Scan and RAM blocks. Figure 4 shows the Language Assistant window.
Figure 4: VHDL Language Assistant window showing the template for a multiplexer. (Screen clip from Xilinx (TM) Foundation software)
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iv. Check Syntax Lets make sure no syntax errors have been made. Go to the SYNTHESIS -> CHECK SYNTAX menu. If successful, a pop-up window will show "Check Successful". Also, the bottom window pane in the Project Manager will display a status of the process or report any errors. To learn more about the errors, open the synthesis report (SYNTHESIS -> VIEW REPORT in the HDL Editor window). v. Add the design to the Project To make the HDL source file part of the Project go to the PROJECT -> ADD TO PROJECT menu in the HDL Editor window. The easyvhdl.vhd file should now appear in the Project Directory on the Project Manager Window (Files tab). You can now exit the HDL editor. You will notice that the right window pane in the Project Manager shows an additional icon for the Synthesis operation (Figure 5). In case you want to create a macro, select PROJECT -> CREATE MACRO (see section on Macros and Hierarchical designs)
Figure 5: Project Manager for the HDL flow mode. (Screen clip from Xilinx (TM) Foundation software) vi. Analyzing and Synthesizing the Design First you will analyze the syntax by going to SYNTHESIS -> ANALYZE ALL SOURCES menu in the Project Manager window. To view warnings or errors click on the HDL Errors, Warnings of Messages Tab at the bottom of the Project Manager. When the files have been successfully analyzed you can translate the design into gates, optimized for the target device.
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You can check the Synthesis Options and change the default settings if needed, by going to the SYNTHESIS -> OPTIONS menu in the Project Manager window. Click OK when done. If it ask you to re-analyze all sources, go to the SYNTHESIS -> FORCE ANALYSIS of ALL SOURCES menu. Click on the Synthesis icon in the Project Manager window (Flow tab). This will open the Synthesis/Implementation settings window, shown below. You can now specify the top level module (in the HDL mode you specify the top-level module during the synthesis operation in contrast to the Schematic flow mode when you specify the top level module when you create your project). In our case we only have one module, called EasyVhdl. However, for more a complicated design you need to specify what the top level design is. The processing will then start from this module and progress through all the underlying designs. Fill out the version name, select the target family and device. If you check "Edit Synthesis/Implementation constraints", you will be able to enter constraints for your design using the Express Constraint Editor. When you "View Estimated Performance after Optimization" you can view the estimated performance results.
Figure 6: Synthesis Settings/Implementation window. (Screen clip from Xilinx (TM) Foundation software) Click on the SET button. In the Setting window you can ask to optimize the synthesis for Area or Speed. You can also specify the target clock frequency. Select Insert I/O pads. This will add input and output pads to the top-level module. When done, click OK.
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Figure 7: Synthesis settings window. (Screen clip from Xilinx (TM) Foundation software) Click RUN to start the synthesis of the design. You can now proceed with a functional simulation by clicking on the Simulation Icon in the Project Manager. Alternatively, you can implement your design. 1.7 Macros and Hierarchical Designs
It is always a good practice to keep a design modular and hierarchical. This is important for designs of moderate and high complexity. Often, you will use a circuit (consisting of different logic gates or HDL code) over and over again. Instead of drawing these logic gates every time you need them, it would be more efficient to make a module or macro out of them with its own symbol. You can then use this macro every time you need it by adding the macro to your schematic. Also, the use of macros keeps the schematic neater and easier to read. A macro does not have to be a schematic, but can be defined by an ABEL, VHDL description, LogiBLOX, CORE Generator module or Finite State Machine module. Macros can be created in both the Schematic and HDL Flow modes. In the schematic flow, macros are added after the creation of the top level schematic, as illustrated in Figure 1a. In case of the DHL flow, the top-level module will be defined at a later stage, during the synthesis step as can be seen in Figure 1b.
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Figure 1: Design and Implementation sequence of a Schematic (a) and HDL flow (b) projet. In this section we will briefly discuss how to create macros in the Schematic Flow mode. You will learn how to create a macro from a schematic, an ABEL and VHDL file, and how to instantiate these macros in a top level schematic. The procedure for creating macros in the HDL Flow mode is very similar. The main difference is the synthesis step as illustrated in Figure 1 above. We will illustrate the creation of macros using a simiple example of a 4-bit comparator that compares two 4-bit words and outputs a logic "1" if the two words are identical, otherwise a logic "0". However, to keep the comparator more general, the X inputs can be selected from two different words (A or B) using a 2:1 multiplexer. If the X (i.e. A or B) and Y signals are the same, the comparator generates a logic "1", otherwise a logic "0". Figure 2 shows the overall schematic. Each comparator compares one bit of each word. If the four comparators outputs Zi are equal to "1", the AND gate will give a "1".
Figure 2: Two 4-bit word comparator We will build this circuit in a modular way, using macros. First, we will create a macro for a 1-bit comparator using the schematic entry tool. We will call this macro "COMP1ME". Then, we will build a
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macro for the 2:1 multiplexer using HDL. Once these two macros are created, we will build the overall circuit schematic (top level schematic). User-defined macros can be created in several ways. A convenient method is using the Symbol Wizard which can be used to create both schematic and HDL based macros. With the Symbol Wizard tool you create the symbol first and the underlying schematic or HDL file later. An alternative way to create a user-defined macro is to create the underlying source file first, such as the schematic or HDL file. If the source file is a schematic, go to HIERARCHY menu -> CREATE A MACRO SYMBOL from the Current Sheet in the schematic editor. In case of a HDL file, go to PROJECT menu -> CREATE MACRO in the HDL Editor. If the underlying macro is a State Machine Diagram, go to the PROJECT menu -> CREATE MACRO. A symbol will be created and placed in the project library in all three cases. We will illustrate these methods in the next example. Lets first create a new project, called "COMP4ME" (go to the FILE menu ->CREATE NEW PROJECT in the Project Manager window). Fill out the Project Name, Directory, select "Schematic Flow", fill out the Device Family (ex. XC400XL), Part (4005XLPC84) and Speed as you did in the section on "Schematic Entry". 1.7.1 a. Create a Macro for the 1-bit comparator using the schematic editor
The Boolean expression for a 1-bit comparator is given by, Z = X.Y + X'.Y' The corresponding schematic is shown in Figure 3. Notice that the 1-bit comparator is actually an XNOR gate. In principle, we can use the XNOR gate to build our 4-bit comparator. However, for the purpose of illustrating the use of macros, we will recreate this 1-bit comparator by using AND gates and inverters as shown in Figure 3.
Figure 3: 1-bit comparator schematic and symbol a1. Using the Symbol Wizard i. Create a Symbol Open the Schematic Entry tool by clicking on the Schematic Entry icon in the Project Manager Window. Lets use the Symbol Wizard tool. In the Schematic Entry window, go to the TOOLS menu -> SYMBOL WIZARD. A Wizard will guide you through by asking several questions. For the Symbol Name, type in the name you want to give to the 1-bit comparator. Lets call it "COMP1ME". Select the Schematic for Contents. Then push the NEXT button. Fill out the name of the input and output port names. When all input and output ports have been defined, push the NEXT button. Follow the instructions. When finished push the FINISH button.
The symbol will now be created and added to the project library. An underlying design file will also be created that has the defined port names. The schematic editor will open showing an empty schematic page for the comparator macro, except for the input and output pins.
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ii. Creating an underlying schematic file for the macro On the schematic of the macro you can now draw the logic gates (Figure 3) for the COMP1ME macro. Creating the schematic is basically the same as explained above in section on "Schematic Entry". However, there are two difference: 1. You do not need to add input or output buffers (IBUF or OBUF) since the cell inputs and outputs will not become routed to the output of the FPGA or CPLD at this point. 2. You do not use IPADs or OPADs for the input and output ports. Use I/O terminals instead to indicate the input and output I/Os. Actually, if you used the Symbol Wizard as outlined above, these I/O terminals would have already been added to the schematic for you. In case you created the macro from an existing schematic you can add an I/O terminal (pin) by clicking on the I/O Terminal icon (hierarchy connector) on the left-hand side of the toolbar or at the top of the SC Symbols window. A pop-up Terminal window will open. Fill out the name of the terminal (ex. X, Y or Z) and indicate whether it is an Input or Output. Be careful to indicate the right direction for the inputs and outputs. Figure 4 shows the completed schematic of the 1-bit comparator.
Figure 4: 1-bit comparator schematic used as a macro (Screen clip from Xilinx Foundation Foundation software). When finished save the schematic. To check if the macro has been created, in the schematic editor go to FILE->OPEN->MACRO. The macro COMP1ME should appear. At this point you can simulate the macro. To simulate the macro, go to the TOOLS -> SIMULATE CURRENT MACRO in the Schematic Editor window of the macro COMP1ME. This will open the simulator. You can now add the signals and stimuli. You can do a functional simulation and verify the operation of the 1-bit comparator. Alternatively, you can first place the macro on the main schematic. You will find the macro in the Symbol Toolbox of the Schematic Editor under the name COMP1ME. Next, go to the simulator by clicking on the SIM icon on the top toolbar. In the Waveform viewer, click on the Add Signals icon (or go to SIGNALS -> ADD SIGNALS). In the middle panel of the Component Selection window, called Chip Selection you will see the name of the macro, COMP1ME. Double click on it. In the right panel, Scan Hierarchy, all the input and output pins will be displayed. Select these pins by double clicking. When done, click the Close button.
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Open the stimulator window and define the stimuli to the input pins using the Binary counter. You can now do a functional simulation and verify the operation.
a2. Using an existing schematic as a macro In case you created a schematic as part of another project and would like to use this schematic as a macro in a new project you can do so. First you will have to add the old schematic to the current (new) project. In the Project Manager window, go to the FILE->ADD DOCUMENT menu. Use the browser to locate the schematic of interest. When done, you will see that the schematic has been added to the project in the left window page (Files tab). Lets assume that the schematic is named TEST1.sch. You may want to modify this schematic, e.g. to change the pin names, replace input PADS (IPADS) by I/O terminals and remove buffers (BUF). Remember that for macros you do not use IPADs or OPADS (these indicate the physical pins of the device) but I/O terminals (see section "Schematic Entry" on I/O pins, Buffers and Pads). Next you need to create a macro from the schematic. This is done as follows: go to HIERARCHY menu -> CREATE MACRO SYMBOL FROM CURRENT SHEET. A window will pop up. You can change the name of the macro, and add a brief description in the comment line. Lets call the macro MACRO1. You can also check the input and output signals. Click OK. When you convert the schematic TEST1.sch into the macro MACRO1, there is no longer any relationship between the schematic TEST1.sch and the project COMP4ME, even though you can still open the schematic TEST1.sch. You can remove the schematic from the project directory using the Windows Explorer.
a3. Creating a Schematic first An alternative way to create the macro, is to create the schematic first and then the symbol. In that case you will open a new sheet and draw the schematic. For the input and output ports you need to use I/O terminals and not IPAD, OPAD, IBUF and OBUF as explained above. When finished with the schematic of the macro, you need to create a symbol. This is done in the same way as above. Go to the HIERARCHY ->CREATE MACRO SYMBOL FROM CURRENT SHEET menu. The Create Symbol window will appear. For the Symbol Name, type in the name you want to give to the 1-bit comparator. Lets call it "COMP1ME2". Make sure that all input and output pins appear in the Pin section of the Create Symbol window. In the comment field, type any comment you like. Click OK. The symbol will be added to the SC Symbols toolbox list. You can now use the newly created macro (symbol) as you would do with any other symbol. You can complete your top level schematic at this point, or create another macro. 1.7.2 b. Create an ABEL macro
Here we will demonstrate how to create a new symbol (or macro) for a 2:1 multiplexer (Figure 2) with ABEL. The symbol for the multiplexer is shown in Figure 5. The MUX selects between two 4-bit words: when S1 is 0, word A will appear at the output; when S1 is 1, word B is connected to the output. We can consider this multiplexer a quad 2:1 MUX. We will now create an ABEL macro for this quad multiplexer. Lets call this macro "MUX4X2ME".
Figure 5: Symbol for the quad 2:1 MUX.
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Lets assume that you have already created a project called COMP4ME of which the macro for the MUX will become part. i. Open the Project: COMP4ME and open the Schematic Editor window. ii. Create new symbol In the Schematic Editor window select TOOLS -> SYMBOL WIZARD. Click NEXT. In the Design Wizard Contents window enter the name of the Symbol: MUX4X2ME. Note: the name of the ABEL macro should not have more than 8 characters. The synthesizer will give an error without saying what caused the error. In the contents section select the HDL and ABEL Radio buttons. Click NEXT. In the Design Wizard Ports window, click on the NEW button to enter the name of the inputs and outputs. Enter S1 in the name field and select Input in the Direction field. Click NEW and enter A[3:0] in the Name field; select Input in the Direction section. Do the same for the B[3:0] input. Next, click on NEW again and enter C[3:0] in the Name field and select Output for the Direction. Go to the ADVANCED button and select the 'combinational' port. Create also the input S1. When finished defining input and outputs, click on NEXT. In the Attribute window fill out a short comments (ex. ABEL code) and long comments (4-bit 2:1 MUX in ABEL). Click the NEXT and FINISH buttons.
You can now place the MUX4X2ME on the new schematic page (COMP4ME1.sch). You will notice that the inputs A[3:0], B[3:0] and output C[3:0] are shown as buses, rather than as individual inputs. This makes the schematic easier to read and less complicated. We will see later how to use buses. (Note: if you created the symbol using the HDL Editor from the Project Manager window, the signals will not be represented as buses but as individual signals A0, A1, A2, etc. This is an annoying feature, particularly when working with wide buses. To prevent this, use the Symbol Wizard in the Schematic Editor window, as outlined above, to create the symbol). In case you want to modify the symbol, such as changing the shape of the symbol, adding, renaming, or removing I/O pins, you can do so. In the Schematic Editor window, select TOOLS -> SYMBOL EDITOR. Or you can also click on the macro symbol on the schematic. The Symbol Properties window will open. Click on Symbol Editor. This will open the HDL Editor window. You can now define the ABEL file in the HDL Editor window as explained next. iii. Create an ABEL macro You still need to define the new macro for which you have created the MUX4X2ME symbol. After placing the symbol on the schematic click the "H" icon (Hierarchy). Next, double click on the MUX4X2ME symbol. The ABEL editor will open its Editor window. You will notice that the pins have already been declared in the HDL Editor window. Make sure that the output pin C3..C0 has been specified as an istype 'com' and not 'reg' because the C is the output of a combinational circuit. In the equation section, type the expression for the 2:1 multiplexer. The expression for the multiplexer output is as follows, according to the Truth Table I. Be careful, input and output names are case sensitive! C = !S1 & A # S1 & B; TABLE I: Truth Table of the 2:1 MUX
S1
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0 1 A B
In order to simplify the expression we made use of sets in the ABEL description (A = [A3..A0], etc.). Each member of the set will undergo the same logic operations (see ABEL Primer - section 5b on Sets). Thus the above expression is equivalent to four individual expressions: C0 =!S1 & A0 # S1 & B0; : C3 =!S1 & A3 # S1 & B3; Figure 6 shows the ABEL editor window. Notice that the sets for A, B and C are already defined. Enter in the equation section the expression for C.
Figure 6: ABEL editor window for the quad 2:1 multiplexer (Screen clip from Xilinx Foundation (TM) Foundation software). When finished, check the syntax (go to the SYNTHESIS->CHECK SYNTAX menu). Exit. When prompted to update the macro, select YES. The synthesis of the macro will now proceed. In the Project Manager window, click on the HDL icon or select TOOLS -> DESIGN ENTRY > HDL Editor. In the HDL Editor window select "Use HDL Design Wizard". Next, click the NEXT button. In the Design Language window, select the ABEL radio button. Then click NEXT. Follow the instructions as outlined above. When the symbol has been created, the HDL Editor will open. Enter the ABEL code.
An alternative way to create an ABEL macro is to open the HDL Editor from the Project Manager:
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When finished with entering the ABEL code, check the synthesis. To create the macro, go to PROJECT menu -> Make MACRO. Give the macro a name. When finished the macro symbol will be added to the project library. As was noted above, this method has the annoying feature that it will expand the buses for the signals A[0:3], B[0:3] etc. which makes the schematic quickly unwealdy, particularly when working with wide buses. 1.7.3 c. Create a VHDL macro
In the previous section we demonstrated how to create an ABEL macro. An alternative way is to define the macro as a VHDL module. In this section we will define the 2:1 MUX as a VHDL file. The procedure is similar to the one for an ABEL macro. i. Open the Project: COMP4ME and open the Schematic Editor window. ii. Create new symbol In the Schematic Editor window select TOOLS -> SYMBOL WIZARD. Click NEXT. In the Design Wizard Contents window enter the name of the Symbol: MUX4X2VH. Note: the name of the VHDL macro should not have more than 8 characters. Click NEXT. In the Design Wizard Ports window, click on the NEW button to enter the name of the inputs and outputs. Enter S1 in the name field and select Input in the Direction field. Click NEW and enter A[3:0] in the Name field; select Input in the Direction section. Do the same for the B[3:0] input. Next, click on NEW again and enter C[3:0] in the Name field and select Output for the Direction. Go to the ADVANCED button and select the 'STD_LOGIC_VECTOR' port. Create also the input S1. When finished defining input and outputs, click on NEXT. In the Attribute window fill out short comments (ex. VHDL code) and long comments (4-bit 2:1 MUX in VHDL). Click the NEXT and FINISH buttons.
You can now place the MUX4X2VH on the new schematic page (COMP4ME1.sch). You will notice that inputs A[3:0], B[3:0] and output C[3:0] are shown as buses rather than as individual inputs. This makes the schematic easier to read and less complicated. We will see later on how to use buses. In case you want to modify the symbol, such as changing the shape of the symbol, adding, renaming, or removing I/O pins, you can do so. In the Schematic Editor window, select TOOLS -> SYMBOL EDITOR. Or you can also click on the macro symbol on the schematic. The Symbol Properties window will open. Click on Symbol Editor. This will open the HDL Editor window. You can now define the ABEL file in the HDL Editor window as explained next. iii. Create a VHDL macro You still need to define the new macro for which you have created the MUX4X2VH symbol. After placing the symbol on the schematic click the "H" icon (Hierarchy). Next, double click on the MUX4X2VH symbol. The VHDL editor will open its Editor window. You will notice that the pins have already been declared in the HDL Editor window. In the architecture section, type the expression for the 2:1 multiplexer. The expression for the multiplexer output is as follows, according to the Truth Table I. Be careful, input and output names are case sensitive! C(0)<= ((not S1) and A(0)) or (S1 and B(0)); C(1)<= ((not S1) and A(1)) or (S1 and B(1)); C(2)<= ((not S1) and A(2)) or (S1 and B(2));
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C(3)<= ((not S1) and A(3)) or (S1 and B(3)); Figure 7 shows the VHDL Editor window.
Figure 7: VHDL Editor window for the 2:1 MUX of Figure 8.4. (Screen clip from Xilinx Foundation (TM) Foundation software). In the HDL Editor window, go to SYNTHESIS -> Check Syntax Select PROJECT -> UPDATE MACRO. Save and exit the editor. In the Project Manager window, click on the HDL icon or select TOOLS -> DESIGN ENTRY > HDL Editor. In the HDL Editor window select "Use HDL Design Wizard". Then click the NEXT button. In the Design Language window, select the VHDL radio button. Then click NEXT. Follow the instructions as outlined above. When the symbol has been created, the HDL Editor will open. Enter the VHDL code. When finished with entering the VHDL code, check the synthesis. To create the macro, go to PROEJCT menu -> CREATE MACRO. Give the macro a name. When finished the macro symbol will be added to the project library. d. Create a top level schematic: 4-bit comparator
An alternative way to create an ABEL macro is to open the HDL Editor from the Project Manager:
1.7.4
A top-level module can be a schematic or an ABEL file. However, it is not recommended to have an ABEL top-level module for a FPGA design. The top-level module can have underlying schematic, ABEL, VHDL or Verilog, LogiBLOXs, Finite State Machine and CORE Generator Modules. In this example we will limit ourselves to a schematic and ABEL or VHDL macro, defined above. We are now ready to design our 4-bit comparator of Figure 2 using the macros for the 1-bit comparator and the quad 2:1 MUX. Go to the Schematic Editor window. The sheet COMP4ME.sch will open.
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i. Adding macro and logic symbols Lets add the 1-bit comparator cells by clicking on the Symbol icon on the left toolbar. Type comp to go to the COMP1ME symbol. Select COMP1ME and place it on the schematic. Then click on the symbol to place multiple copies of it. Next add the quad 2:1 MUX. Add next the 4 input AND gate (AND4). If the symbol name of COMP1 does not show and you want to display it, select the symbol and double click. In the Symbol Properties window, press the Attributes key and select "Show Symbol Name". Lets assume that we want to implement the 4-bit into a FPGA or CPLD. Thus we need to indicate the input and output pads (unless you want to make another macro for the 4-bit comparator; in that case follow the same procedure as above). First you have to add the input buffers. Select IBUF4 in the SC Symbol window and place it on the schematic. Do this for each input A, B and Y (see Figure 8). For the S1 input signal, place a single IBUF. Then add the OBUF. Next, place the input pads (IPAD4) and output pad (OPAD) to indicate the connection to the actual pin of the FPGA or CPLD.
Figure 8: Top level schematic of the 4-bit comparator (Screen clip from Xilinx Foundation (TM) Foundation software). ii. Adding wires and net names Connect the IPADS to the IBUF and the OBUF to the OPAD using the Draw Wire command. Also, connect the output of the AND gate to the input of the OBUF and the output of the four 1-bit comparators to the input of the 4-input NAND gate. Next, we want to label the input, output nets and the compartor outputs. Select the Add Net Names icon on the left toolbar. The Net Name window will pop up. Enter the Net Name A0. To speed up the net naming, select the REPEAT button. Every time you click on a net, a new name will be placed and the name index will be incremented by one. Press the ESC key to finish the command. Do the same
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of the B inputs and the Z outputs of the 1-bit comparators. Don't forget to name the S1 input net. Next, we will use the Draw Buses command to connect the inputs. iii. Draw Buses To connect the IBUF4 outputs to the MUX inputs A[3:0] and B[3:0] we will use the Draw Bus command. Click on the Draw Buses icon or go to the MODE -> DRAW BUSES menu. Click on the input A[3:0] of the MUX and draw the bus as shown in Figure 9. Click to make a corner in the bus. Click on the right mouse button or double click to end the bus. An Add Terminal/Label or Edit Bus window will appear, as shown in Figure 9. If not, double click at the end of the bus. In the window enter in the Name field: ABUS. Select a bus width: from 3 to 0. This bus is not an input or output bus, so the I/O marker should say None. Click OK. Do the same for the B-bus and the C bus and call this bus BBUS and CBUS, respectively.
Figure 9: Edit Bus window (Screen clip from Xilinx Foundation (TM) Foundation software). Bus Taps Now we can connect the inputs of the 1-bit comparators to the buses. This is done by clicking on the Draw Bus Taps icon or going to the MODE menu ->DRAW BUS TAPS. Click first on the bus name ABUS to select the bus you want to tap into. The status line will show that the first bus tap ABUS0 (usually the member with the lowest index) has been selected for placement. Next click the cursor on the A0 output of the first input buffer (IBUF4) (least significant bit). Then, click on A1 outputs of the 2nd, 3rd and 4th buffer. When finished click on the ESC key twice. Repeat the process for the BBUS and CBUS as shown in Figure 8. Make sure that the tap numbers correspond to the numbers of the input signal (A0 connected to ABUS0, A1 to ABUS1, etc.). Note: The default start number for the tap is 0. You can use the up and down arrow keys to select which bus bit will be tapped. If the down arrow key was pressed last, the bus tap numbers will decrease. If you want to connect a single wire to a bus, you need to draw a wire that starts or ends at the bus. Next you will need to label the wire with the name of a bus member to which you want to connect. For instance, you want to access the most significant bit in the carry-cout bus (CBUS). You need to name the wire CBUS3. If you do not name the wire, there will be no connection (a warning will be generated) or if you give it different name from the bus, there will be an error. Complex buses
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To simplify a schematic, you can combine buses and individual wires into a complex bus. This is done by naming the complex bus with a compound label. A compound label consists of several label names (with or without ranges), separated with commas. To enter a compound label, use the following format: NAME[F:L:I],NAME,NAME[F:L],... where F is the first number, L is the last number, and I is the interval between the numbers in the range. If no interval is specified, the interval is 1. As an example we could combine the LED-OUT buses and the Error signal in a complex bus with the name LED_ONE[6:0], LED_TWO[6:0],ERROR or we can use a selected number of wires: LED_ONE[3:0], LED_TWO[4:2],ERROR It is important that each of the bus segments, such as LED_ONE[6:0] have been defined beforehand. For more information about buses, in the Schematic Entry window, select HELP -> SCHEMATIC EDITOR HELP CONTENTS. In the help window select INDEX and type buses. I/O terminals vs. PADS. In case you decide to use this schematic as another macro and do not intend to implement this particular schematic in a FPGA or CPLD, you do not need to add PADS and BUFFERS. In that case, when you draw the input buses to connect the inputs A and B, you will indicate in the Add Terminal/Label window (Figure 5) that the bus is an input (or output, if appropriate). The name of the bus will now be the name of the inputs to the macro. To create a macro from the schematic go to the HIERARCHY ->CREATE MACRO SYMBOL FROM CURRENT SHEET menu. When the schematic is finished save it. iv. Going down the hierarchy To push into a schematic of a macro, select the "H" icon (Hierarchy icon) and double click on the desired macro symbol (ex. comp1). To go back to the upper level schematic, double click on the background of the lower level schematic. v. Netlist and Integrity Test When the schematic is finished you can create a netlist and do an integrity test. This is done by going to the OPTIONS menu-> CREATE NETLIST. When finished, it is always a good idea to check that the schematic has no electrical design rule errors. This is done from the OPTIONS menu -> INTEGRITY TEST. You can now also generate a EDIF netlist by going to the OPTIONS menu -> EXPORT NETLIST. vi. Simulation You can now do a functional simulation of the schematic as was explained in the section on "Simulation". The only difference is the presence of buses. In order to assign signals to the individual inputs of the A and B bus, you need to expand the bus into the individual signals. This is done by selecting the bus A or B in the Waveform Viewer window and then going to the SIGNAL->BUS -> FLATTEN. You can now assign outputs of the binary counter to the individual A and B inputs. You can click on the Bus Expansion Icon on the top toolbar to collapse or expand the bus (after creating it first), or go to the SIGNAL -> BUS -> COMBINE menu after selecting the signals you want to collapse into one bus (in this case, it will be A0, A1, A2 and A3). The signals on a collapsed bus are displayed in HEX notation (unless othewise specified). Other macros: One can add other types of macros to the top-level schematic such as a Finite State Machine (FSM) macro, LogiBLOX or CORE Generator module. The procedure is similar to what was done for an ABEL or VHDL macro. For instance, to create a FSM macro, open the FSM editor by clicking on the State Editor in the Project Manager window. Follow the procedure as explained in the section on the "State Editor".
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1.8 State Editor
Finite state machines can be specified in a variety of ways. One way is to use HDL, such as ABEL or VHDL. The ABEL tutorial explains how the STATE_DIAGRAM, IF-THEN-ELSE or the TRUTH_TABLE construct in ABEL can be used to fine state machines. Examples of both a Mealy and a Moore machine have been discussed. The Xilinx Foundation tools provide an alternative method to specify a state machine. In order to use the State Editor, one must have XABEL or X-VHDL installed. The State Editor allows you to define a state diagram using a graphical description and to convert the graphical description in either ABEL or VHDL. In order to show the use of the State Editor, we will implement the same sequence detector that we used to illustrate the use of ABEL to define a state machine. We will implement two variations of the same sequence detector - one implemented as a Mealy machine and another as a Moore machine. The sequence detector recognizes the following input bit sequence X: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. In case we are implementing a Mealy machine, the output is associated with the transitions as indicated on the following state diagram.
Figure 1: A Mealy machine for a non-resetting sequence detector for the input sequence 1011. In the following sections we will explain how to define the above state diagram using the State Editor. First one has to create a new project (or use an existing project). For help with the State Editor go to HELP -> FOUNDATION HELP CONTENTS -> STATE EDITOR. 1. Creating a State Machine Macro a. In the Project Manager Flowchart, click on the State Editor button or go to TOOLS -> DESIGN ENTRY -> STATE EDITOR. This will open the State Editor window. b. Select "Use the HDL Design Wizard" and click OK. c. In the Design Wizard Language window, select either ABEL or VHDL. We will be using the ABEL language. This implies that the State Editor will convert the graphical description into an ABEL code (or VHDL).
d. Specify the file name. Do not use names which are longer than 8 characters. Click NEXT. e. In the Ports window, define the inputs: X, RST (for reset) and CLK (clock). Define also the output port Z. Click on the ADVANCED button and select the "Combinational" for the output direction in case you are using ABEL or select "STD_LOGIC" when using VHDL. We will assume that the output of the sequence detector is coming from a combinational circuit. We could make the state machine synchronous by selecting "registered" for the output port Z (for ABEL). Notice that one needs to define a clock as one of the input ports. By naming one of the input ports CLK, the state machine determines that CLK is the clock input. We will also provide a reset signal, RST, that will allow us to reset the sequence detector to a known state. When all input and output ports have been defined click on the NEXT button. f. In the "Machines" window, select "One" and click FINISH. The default name for the state register is Sreg0. This will open the State Editor window in which we can
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graphically describe our sequence detector, as shown in Figure 2. The top of the window shows the input and output terminals.
Figure 2: State Editor window used to define the state diagram (Screen clip from XilinxXACTstep(TM) Foundation software) 2. Defining the States a. In the State Editor window, click on the State "S" icon on the left side vertical toolbar or select FSM-> STATE from the menu. This will place a state bubble in the window. You can reshape the bubble by selecting it and dragging the small squares. To rename the state click on the state name in the middle of the bubble and type the new name. Add the three other states as shown in Figure 3.
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Figure 3: The four states of the sequence detector. (Screen clip from XilinxXACTstep(TM) Foundation software) b. A state machine should have a reset so that it powers up in the correct state. This reset will not appear on the schematic but the presence of the reset in the state diagram will direct the HDL compiler to define the state encoding such that the machine starts in the correct state. To add the reset to the state diagram, click on the Reset icon (small triangle) on the left side toolbar or select FSM ->RESET. Place the reset symbol on the diagram. We want the machine to reset to the state S0. This is done by clicking inside the S0 state bubble. The reset can be synchronous or asynchronous. We will make the reset asynchronous. This can be done by right-clicking on the reset symbol and selecting "Asynchronous". 3. Defining the transitions: A state diagram is defined by specifying under what conditions the input signal the machine goes from one state to another. These transitions are indicated by arrows between the state and by labeling the input conditions that causes the transition to occur as is shown in Figure 1 for our sequence detector. We will first define the transitions and then the conditions. c. Click on the Transition icon (icon with the arrow) on the left side toolbar (or select FSM -> Transition).
d. Next, place the cursoor in the state S0 to start the transition. To create a bend in the arrow, place the cursor and click where you want the bend to occur. Then, click inside the state S1 to complete the transition. Do the same for all the transitions shown in Figure 1. 4. Defining the conditions The next step is to define the conditions associated with each transition (arrow). a. Click on the Condition icon (=?) or select FSM -> CONDITION. b. Click on the transition arrow, e.g. the transition between State S0 and S1. A small text box appears
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c. Enter the condition. If you use ABEL, you need to use the ABEL syntax to define the condition. For the transition from S0 to S1, type: X&!RST. Indeed the transition will occur when the input signal is "1" (i.e. X is true AND the Reset signal is negated). If you use VHDL type, X='0'.
d. Do the same for all the other transitions. For instance, the transition between the Reset symbol and State S1 occurs under the condition: RST. Similarly, one stays in State S0 under the condition: !X#RST (i.e. when X=0 or the RST signal has been asserted). Notice that strictly speaking we dont have to include the RST input in all the state transitions because we have included a Reset symbol. We have included it here to illustrate how to specify conditions with more than one input. Figure 4 shows the state diagram with labeled transitions. You can select the conditions and move them around on the diagram.
Figure 4: State diagram of the sequence detector with transitions and conditions using the ABEL syntax. (Screen clip from XilinxXACTstep(TM) Foundation software) 5. Defining the Actions Actions (i.e. output signals) are either associated with transitions as is the case for a Mealy machine, or with a state as is the case for a Moore machine. In the example of our sequence detector (Mealy machine) we will associate actions with a transition. a. Click on the Transition Action icon on the vertical toolbar or select FSM -> ACTIONS > TRANSITIONS. b. Click on the transition arrow. A text box will appear c. Type in the desired action. For the transition from S0 to S1, the output Z should go low. This is specified by typing: ^b0 in the text box, in case you use ABEL (for a VHDL based FSM, type Z<='0';). Do the same for all other transitions except for the transition from S3 to S1 which causes the output to go high: ^b1. In case multiple outputs are present you need to define each output. For intance: OUT1=0; SUM=0; or in case of a bus: OUTPUT_BUS=^b10.
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d. You can specify the clock signal (otherwise the State Editor will use the CLK signal you defined in the wizard. Select FSM -> MACHINE ->Sreg0. This will open the Machine Properties dialog box. Under General you can select the clock signal and specify to use the Rising or Falling edge of the clock. You can use this window to specify the reset signal, and the type of encoding (Symbolic or Encoded such as binary, Gray of Johnson).
Figure 5a: Completed State Diagram of the sequence detector implemented as a Mealy machine using ABEL. (Screen clip from XilinxXACTstep(TM) Foundation software) In the previous example, it is not necessary to add the Reset signal at each transition. The same results would be obtained by only including the Reset signal at the transistion between the Reset icon and the S0 state, as shown in Figure 5b below.
Figure 5b: State Diagram of the (1011) sequence detector implemented as a Mealy machine using ABEL. The signal X is the input string.
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The same sequence detector can also be created using VHDL instead of ABEL. The state diagram of the (1011) sequence detector implemented as a Mealy machine with VHDL is shown in Figure 5c below.
Figure 5c: State Diagram of the (1011) sequence detector implemented as a Mealy machine with VHDL. An example of a Moore machine that implements the same sequence detector is given further on. 6. Generating the HDL code and compiling the state diagram. a. Save the state diagram b. Specify the type of encoding to use for the states. Go to FSM -> MACHINE -> Sreg0. The Machine Properties window will open; select Binary encoding. c. In case you would like to see the ABEL or VHDL code, go to SYNTHESIS -> HDL CODE GENERATION. A window will open showing the HDL Code. The ABEL code of the State Diagram of Figure 5b synthesized with Binary Encoding or Symbolic Encoding can be seen by clicking on the above links. The VHDL code for the state diagram with symbolic encoding can be seen by clicking here.
d. At this point you can create a macro from the state diagram by going to the PROJECT -> CREATE MACRO menu. This will synthesize the state diagram and add it to the symbol libraries. e. When you open the schematic editor you will be able to place the macro from the SC Symbol window. After placing the macro you can simulate it to verify the proper operation. f. In case there are errors, you can view the report by going to SYNTHESIS -> VIEW REPORT. It can also be instructive to check the HDL Code (if you are familiar with specifying a state diagram in ABEL or VHDL).
7. Simulation and Implementation Once you have created a macro or synthesized the state diagram you can do a simulation. The functional simulation of the Mealy machine of the sequence detector is shown in Figure
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6. The output is valid at the end of the state-time which occurs just before the rising edge of the clock. The output is asserted after the sequence 1011. Notice that the output shows some glitches as is typical for an asynchronous Mealy machine.
Figure 6: Functional simulation of the Mealy sequence detector (sequence 1011). (Screen clip from XilinxXACTstep(TM) Foundation software) Graphical Simulation When you use for the encoding "Encoded (e.g. binary) " instead of Symbolic encoding you can follow the state transitions on the State Diagram during simulation. This is a good feature when debugging your state diagram. Start the simulator and define the signals. Next, open the state diagram; this can be done by using the Push Hierarchy button in the schematic editor. Once the State Editor window is open, go to TOOLS -> SIMULATION. This will activate the graphical simulation feature. The best is to have both the Waveform viewer and the State Editor window open so you can follow the state of simulation. The graphical simulation feature does not work for Mealy machines. An example is given below for a Moore Machine sequence detector. When the circuit works properly you can implement it. Go to the Project Manager and click on the Implementation Icon. For more information about implementation consult the tutorial section in implementation. Example of a Moore machine If one wants to eliminate the glitches in the output in the Mealy machine, one can implement the sequence detector as a Moore machine. The state diagram is given in Figure 7 below. One has to add one state, S4, as compared to the Mealy machine.
Figure 7: State diagram of a sequence detector for the sequence 1011, implemented as a Moore machine.
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The corresponding state diagram description using the State Editor is given in Figure 8. The difference with the one of the Mealy machine, is that Actions are now associated with a State. These can be defined by clicking on Action State icon on the left vertical toolbar in the State Editor window (or by selecting FSM -> ACTIONS ->STATE).
Figure 8: Completed State Diagram of the sequence detector implemented as a Moore machine using ABEL (Screen clip from XilinxXACTstep(TM) Foundation software) In order to do a graphical simulation we will use Binary state encoding instead of symbolic encoding. Select FSM -> MACHINE ->Sreg0. In the Machine Properties window select Encode: binary. Click OK. To see the ABEL code, select SYNTHESIS -> HDL CODE GENERATION. To see the ABEL code click here. We will do a functional simulation together with the graphical simulation of the State Machine. Start the simulator from the Project Manager window and select the signals and define the stimulators. Next, open the State Diagram by using the Push Hierarchy (H) button in the Schematic Editor window. From the State Diagram window, select TOOLS -> SIMULATION. The functional simulation of the Moore machine together with the state diagram is shown in Figure 9. The output goes high after the sequence 1011. No glitches are present in the output as compared to the Mealy machine (see Figure 6). Notice that the graphical editor can only be used when the State Editor is opened from the Project Manager or by using the Push Hierarchy in the schematic.
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Figure 9: Functional simulation of the Moore Sequence detector (1011). The top window shows the functional simulation and the bottom one, the state diagram. The State S4 is highlighted after the sequence (1011). (Screen clip from XilinxXACTstep(TM) Foundation software) In the above example we created a Finite State Machine macro as part of a top-level schematic. However, a schematic project can have a top-level ABEL design created with the FSM editor (toplevel ABEL designs are not recommended for FPGA projects). To add a top-level ABEL design to the project, do the following: in the State Editor, select FILE - SAVE; then select PROJECT -> ADD to PROJECT. Next, select SYNTHESIS -> SYNTHESIZE. For more information about the State Editor, go to HELP -> STATE EDITOR HELP CONTENT in the State Editor Window.
Examples: 1.How-to Easily Design an Adder Using VHDL We are going to take a look at designing a simple unsigned adder circuit in VHDL through different coding styles. By doing so, this will get you familiar with designing by different methods and, hopefully, show you to look for the easy solution before attempting to code anything. The specific circuit we are going to model in this how-to is a 4-bit unsigned adder. In the first pass of the design, we will build a 1-bit full adder (or (3,2) counter) slice that will be used to build the full 4-bit
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adder. In the second pass of the design, we are going to build the circuit using the IEEE std_logic unsigned package, a much more code efficient and scalable design. This how-to assumes you have some knowledge of VHDL and understand concepts such as entities, architectures, and signals. If you need further VHDL language references, please check under the tutorials section of Student Resources. Let begin! 1-Bit Full Adder As you know, a 1-bit full adder is characterized by the following equations: sum = x xor y xor cincout = (x and y) or (x and cin) or (x and cout) where x, y, and cin are the two inputs and the carry in, respectively while sum and cout are the sum and carry out. A pictorial representation of the component is listed in figure 1.
Figure 1 - 1-Bit Full Adder Component
The VHDL code for the above component is as follows: library IEEE; use IEEE.std_logic_1164.all; entity add_1_bit is port ( x: in std_logic; y: in std_logic; cin: in std_logic; sum: out std_logic; cout: out std_logic ); end add_1_bit; architecture rtl of add_1_bit is begin sum <= x xor y xor cin; cout <= (x and y) or (x and cin) or (y and cin); end rtl; As you can see, we are using the standard IEEE libraries, which include std_logic, in order to create components that can be synthesized easily to hardware. Using signal types such as bit may not synthesize or produce unpredictable results. Always use the std_logic_1164 library! This is a pretty standard component. In the entity declaration, x, y, and cin are declared as inputs of type std_logic. The outputs are sum and cout of type std_logic. In the architecture section, we define the outputs sum and cout to be concurrent statements based directly off the inputs. Nothing special about this component, I'm sure you have already seen a version of this model. 4-Bit Unsigned Adder using 1-Bit Full Adder Component
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Now we are going to make four copies of the above component to make our 4-bit unsigned adder component, thus producing a ripple-carry adder. This is done through instantiating four copies of the above 1-bit adder component in VHDL. Figure 2 illustrates the connections of this component.
Figure 2 - 4-Bit Unsigned Adder
The inputs to the component are the 4-bit unsigned numbers, x and y, and the carry in that includes cin and the internal ripple carries between each 1-bit block. The 4-bit output sum and cout are shown as outputs of the systems. Listed below is the VHDL code for the component. library IEEE; use IEEE.std_logic_1164.all; entity add_4_bits is port ( x: in std_logic_vector(3 downto 0); y: in std_logic_vector(3 downto 0); cin: in std_logic; sum: out std_logic_vector(3 downto 0); cout: out std_logic ); end add_4_bits; architecture rtl of add_4_bits is component add_1_bit port ( x: in std_logic; y: in std_logic; cin: in std_logic; sum: out std_logic; cout: out std_logic ); end component; signal i_carry: std_logic_vector(2 downto 0); begin cell_1: add_1_bit port map (x(0), y(0), cin, sum(0), i_carry(0)); cell_2: add_1_bit port map (x(1), y(1), i_carry(0), sum(1), i_carry(1)); cell_3: add_1_bit port map (x(2), y(2), i_carry(1), sum(2), i_carry(2));
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cell_4: add_1_bit port map (x(3), y(3), i_carry(2), sum(3), cout); end rtl; You can see that we define the component add_1_bit in the architecture declaration section of the code. Please also notice that this declaration follows VHDL-87 format and NOT the '93 version. This is because the synopsis synthesis tool is VHDL-87 compliant and we need to code to those rules in order to generate valid synthesis results. Coding in '93 will not (currently) work. Four versions of this component are then declared in the body section of the code, with all of the appropriate "glue" between each component. As this point, you must be asking, "isn't there an easy way to do this?". From my perspective, this is a lot of code for just a 4-bit unsigned adder; the point to VHDL is to make it easier to perform operations such as the above. Let's take a look at an easier way. 4-Bit Unsigned Adder Using std_logic_unsigned Using the same entity as above, look at the code below and notice how much and where it has been shortened . library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity add is generic (width: integer:=4); port ( x: in std_logic_vector((width-1) downto 0); y: in std_logic_vector((width-1) downto 0); cin: in std_logic; sum: out std_logic_vector((width - 1) downto 0); cout: out std_logic ); end add; architecture rtl of add is signal i_sum: std_logic_vector(width downto 0); constant i_cin_ext: std_logic_vector(width downto 1) := (others => '0'); begin i_sum <= ('0' & x) + ('0' & y) + (i_cin_ext & cin); sum <= i_sum((width-1) downto 0); cout <= i_sum(width); end rtl; The first thing you will notice, at the top of the code, is the reference to the std_logic_unsigned package, used for unsigned std_logic arithmetic operations. This package contains a procedure called "+" which we use as an addition within the body of the architecture. This "+" takes three unsigned std_logic_vectors and adds them, returning a result. The other should be the use of a generic. A generic lets us produce code that can be changed by the passed parameter. In our case, we let the generic width be the bit width of the two numerands, thus making the code scalable to any width of signals. For this specific example, we take x and y, concatenate a '0' to the beginning (unsigned logic). For cin, we concatenate a vector one less than the generic constant. These are all added with "+" and assigned to the result i_sum. We then split i_sum into the sum and the carry out. This can be done a number of ways but this is one of them and, as you can see, is much simpler than the previous example. Additionally, with the use the generic width, the component becomes much more reusable, a quality always desired by designers.
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I have found that the performance of such code to be better, while easier to code, than other algorithmic techniques. This is probably due to the fact that the synthesis tools will understand what is inferred by the IEEE libraries more than any algorithm you can write. However, be careful of the cin vector. Good synthesis tools will recognize that the cin vector is really only cin padded with zeros, and thus will apply only the cin signal to the input of the cin portion of the fast carry logic for the FPGA. However, others will not; check the output of the synthesis tool to make sure that the fast carry logic was used on the FPGA (assuming such logic exists). Of course performing hand layout methods or using LogicBLOX will produce smaller, faster results. But those methods become technology dependent (i.e. tied to your target device) while this code will not. 2.How-to Easily Design a Multiplexer Using VHDL We are next going to take a look at designing a multiplexer circuit in VHDL through different coding styles. By doing so, this will get you familiar with designing by different methods and, hopefully, show you to look for the easy solution before attempting to code anything. The specific circuit we are going to model is a general multiplexer. In the first pass, we will do a basic 4-to-1mux with 8-bit signal widths. Expanding on the idea, we are going to add in a generic to provide for variable signal widths making our design more reusable. Finally, the last design modification will allow for both variable signal widths and variable number of operands or multiplexed lines. This how-to assumes you have some knowledge of VHDL and understand concepts such as entities, architectures, and signals. If you need further VHDL language references, please check under the tutorials section of Student Resources. Lets begin! Standard 4-to-1, 8-bit Signal Width Mux As you probably know, a multiplexer accepts a number of different signals and routes an appropriate one given by a selection signal. We have the MUX with op_0 to op_3 being the input signals, sel the 2-bit selection signal, and output the routed signal. In this, assume that the input signals are 8-bits in width. Figure 1 illustrates this.
Figure 1 - A 4-to-1 Pictorial Description of a Multiplexer
Thus, for a basic mux, the VHDL coding would be the following : library IEEE; use IEEE.std_logic_1164.all; entity mux_4ops_8bits is port ( sel: in std_logic_vector(1 downto 0); op_0: in std_logic_vector(7 downto 0); op_1: in std_logic_vector(7 downto 0); op_2: in std_logic_vector(7 downto 0); op_3: in std_logic_vector(7 downto 0); output: out std_logic_vector(7 downto 0) ); end mux_4ops_8bits;
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architecture rtl of mux_4ops_8bits is begin mux: process(sel, op_0, op_1, op_2, op_3) begin case (sel) is when "00" => output <= op_0; when "01" => output <= op_1; when "10" => output <= op_2; when "11" => output <= op_3; when others => output <= op_0; end case; end process; end rtl; Again, we are using the IEEE libraries to give the code the best possible chance to synthesize. Notice the use of the case statement instead of an if elsif block. Using an if elsif block infers a level of priority, with the first statement of the if being the highest and the else block containing the lowest priority statements. This is not what describes a multiplexer. The case statement is the best, rigid method instantiating a mux in hardware since it infers no priority among the statements included within the case block. Another key point about this code is the use of the "when others" statement. This end to the case statement is needed in order to synthesize properly but using it wrong could produce unpredictable results based on the synthesis tool. Try to place a default value here, usually one of the various multiplexed signals, to infer correct hardware. Finally, as with any process statement, make sure that you place any signal that is on the right-hand side of the assignment statements in the process sensitivity list. Although not doing so will still generate correct hardware, the simulations can become invalid. Variable Signal Width 4-to-1 Multiplexer A small variant on the above code is to provide a generic statement to provide variable multiplexed signal width. By doing so, the code will become more reusable in later designs. Why reinvent the wheel! This code can be seen below : library IEEE; use IEEE.std_logic_1164.all; entity mux_4ops is generic (width: integer:=8); port ( sel: in std_logic_vector(1 downto 0); op_0: in std_logic_vector((width-1) downto 0); op_1: in std_logic_vector((width-1) downto 0); op_2: in std_logic_vector((width-1) downto 0); op_3: in std_logic_vector((width-1) downto 0); output: out std_logic_vector((width-1) downto 0) ); end mux_4ops; architecture rtl of mux_4ops is begin mux: process(sel, op_0, op_1, op_2, op_3) begin case (sel) is when "00" => output <= op_0; when "01" => output <= op_1; when "10" => output <= op_2; when "11" => output <= op_3;
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when others => output <= op_0; end case; end process; end rtl; The only difference from this code and the previous code is the inclusion of a generic width that makes the multiplexed lines any bit width, a very nice additional feature to have. Please note the use of a default value for the generic (in our case 8 for 8-bits wide). Variable Mux Using a Package To extend the above idea even further to include a variable number of multiplexed signals as well as variable signal width, we need to use a package to define an array of signals. This includes defining constants, types, and subtypes that are needed to define the entity of the component. This package is defined below : library IEEE; use IEEE.std_logic_1164.all; package mux_types is constant mux_sel_width: integer:=2; constant mux_signal_width: integer:=8; subtype mux_sel is std_logic_vector((mux_sel_width-1) downto 0); subtype mux_output is std_logic_vector((mux_signal_width-1) downto 0); type mux_ops is array (0 to (2**mux_sel_width-1)) of std_logic_vector((mux_signal_width-1) downto 0); end mux_types; This package defines the multiplexers signal width and number of signals by constants. These constants are then used to define types and subtypes that make up the entity types that we need to define a completely generic interface. These are then used in our mux code, listed below: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; library WORK; use WORK.mux_types.all; entity mux is port ( sel: in mux_sel; ops: in mux_ops; output: out mux_output ); end mux; architecture rtl of mux is begin output <= ops(CONV_INTEGER(sel)); end rtl; The library WORK is our working library where the package mux_types exist. We reference this by the statement use WORK.mux_types.all; The entity is then defined using the types and subtypes contained in the package. The output is not selected by a case statement, since we do not know how many items are in the case, but by the IEEE function CONV_INTEGER, which converts std_logic_vectors to integers. We then use the integer as an index into the multiplexed signal array, the array defined by the package.
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The choice of mux is up to the designer as they will all, in this specific case, synthesize to the same hardware. I prefer to use the second method and define several versions (2-to-1, 4-to-1, 8-to-1, ect.) that have variable signal widths. This way I can keep the package clear of these types and use it only to define my system-level signals (makes it less cluttered and easier to read). But this choice is up to you.
EXAMPLES THAT GUIDE YOU BY HAND:

1. EXAMPLE #1: A SIMPLE VHDL PROJECT
Here is where I will take the novice who can turn on the computer and find the mouse (nine out of ten times) through a simple VHDL Xilinx project. Below is the schematic I wish to implement. By this time you should be able to identify all of the parts and understand what they do.
VHDL has three styles of implementing designs. You can choose data flow, structural or behavioral. Any decent VHDL book can give you an in-depth study of the differences between them. I have chosen behavioral for this implementation since I believe it will be the easiest for you to interpret into what you are now learning. Below is the code for this project. You should be able to recognize items like: in, out, and the signals (A, B, C, Y) from the picture above. Highlight and copy this code. Copy only the words in RED FEW GATES CODE library IEEE; use IEEE.std_logic_1164.all; entity FEWGATES is port ( A: in std_logic; B: in std_logic; C: in std_logic; Y: out std_logic ); end FEWGATES; architecture behavioral of FEWGATES is begin fcn: process (A, B, C) begin if (A = '0' and B = '0') then Y <= '1'; elsif C = '1' then Y <= '1'; else Y <= '0'; end if; end process; end behavioral;
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On the computer, start the Xilinx project manager from the start programs button. This will bring you to the "Getting Started" menu.
Select "Create a new project" and click ok. Click on the "HDL" option since we are going to code this project in VHDL versus a schematic. For name, pick a name you like and that will be easy for you to identify with this project. I would suggest getting a zip disk to store your work on. For the early labs, it should fit on a 3.5 diskette.
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When you click OK, watch the lower half of the screen. If you see red lines of text, you have a problem with the Xilinx software. Anything you do beyond this point will be in vain. Notify me of the broken machine so I can get it fixed. After a few seconds your project has been created. In the design entry area of the top center section of the screen, click on the HDL paper looking symbol.
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It will bring up the "HDL Editor." Click on the "create empty" section and then "OK." You are now looking at line 1 of the VHDL text editor section where you will type your code. For simplicity, just paste in the sample code listed above entitled "FEW GATES."
You can now see how VHDL and Xilinx treat certain key words like "in and out." The key words are shown in red and this will keep you from using restricted words like "and" in your code. If you have errors in your code you will see red lines under the suspected errors or problem areas. Let's check and see if the code is any good. Go to the Synthesis drop down menu and select "check syntax."
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You will be reminded to save first. Click "OK" and title your code whatever name you like. Once again you should try to use a name that will identify what the code is doing. Click save.
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The program will now begin checking syntax for errors. After a few minutes, you will be rewarded with a "check successful" box. Click "OK." It you have errors identified at this time, delete the code, go back, recopy and repaste. There should be no errors in the code listed above in red. Later you can return to this section and change the code in small ways to see how the software catches and identifies syntax problems. Go to the "Project" drop down menu and select "add to project."
This adds the newly compiled code to our project. Click "X" on the HDL Editor screen to close it. You now see a green check on the Design Entry section which means you are done with that section and are ready to move on.
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Below the Design Entry section is the Synthesis section. Click this section once now. It will bring up the Synthesis Implementation menu.
Look at all the options you have. Again for simplicity, we will use the defaults. Click "Run." The software is now deciding how to best take your design and put it into a logic schematic. When it is done you will see a green check in the section. Scanning down you will see you can now choose between Simulation or Implementation.
Let's do the implementation first. Click Implementation once. You will be brought to the "Synthesis/Implementation" menu. Click Run. The software is now taking your project and deciding how to burn it into a chip. This may take a few minutes. Project manager rewards you eventually by telling you that it completed the process successfully. Click "OK".
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A neat thing to now look at is some of the reports that have been generated. On the top of the screen you will see a reports tab. Double click on some of the reports. Most of it will make very little sense to you at this point but it is kind of neat to see the wealth of information that has been generated by this project. Let's see if the circuit performs as we designed it to.
Go back to the flow tab and click on "Simulation." This will take you to the "logic simulation" section.
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You need to put the inputs and outputs into the page. At the top of the screen click on the "signal" drop down menu. Click on add signals.
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We only care about A, B, C, and Y since we are concerned at this point with our inputs and outputs. The other signals relate to signals within the created chip. Double click on each of them (A, B, C, Y), one at a time. They should have red checks on them meaning that they have been selected. At the bottom left of the screen, click "close". You now see your signals on the left yellow side of the screen. Now we want to make A, B, and C change states (shift from 1 to 0 and back to 1 quickly) and see what our output Y does in response. Select A by clicking once on it. It should turn blue.
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Go up to the signal drop down menu and select "add stimulators." There are many options for you here. I have included an entire page on this web site strictly to simulation. You can refer to it later by clicking here. For now, let's keep it simple
Look for the "Bc" row and select the far right little round yellow dots. You should see a red "B0" appear next to A. For B, select the next yellow dot to the right, which will assign "B1" to B. Select the B2 for C. Click "close" on the stimulation selection screen. This places three clocks of different
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intervals on your three inputs. The screens above and below show BF, BE and BD where yours will show B0, B1 and B2.
Go to the top of the screen and select the options drop down menu. Select "start long simulation." Accept the default of 00:00:10 and click start.
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When this is done, you will now want to look at your results. Never try to print this, as it is several hundred pages long. In the upper left side of the screen you will see something that looks like an upside down comb. It is to the left of the "1us/div" reading. Click the tight/left comb several times and it will shrink your display so you can see your inputs and output. The combs zoom in and out your view so you can look at your results. You get the best view at the 5us/div setting. You can now verify your output changed due to your inputs.
2.
EXAMPLE #2: A SIMPLE VHDL PROJECT-(Contd..)
The only new item of Xilinx that we need to show you for this lab is how to give specific inputs in Xilinx simulation. The benefit of simulation is that it allows you to test your designs before you create your first chip. In all your previous labs, we were only concerned with having enough inputs to allow for a complete collection of all possible combinations of inputs. You did this by selecting the little dots from the stimulator section. For this lab, we will specify our inputs. Input your code just like you did in simple project. Once you have done your syntax check, added your code to your project, and done the synthesis, come here. I will start out with the point where you click on the simulation button. Just like in simple project, click on Simulation and add your input and output signals. Put them in the correct order (inputs go on the top, outputs go on the bottom). Click on add stimulators and you should be looking at a screen like this.
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The difference between clocks and formulas is that clocks continue forever to repeat the sequence you put in. Formulas only continue as long as you tell them. Click on "formula" and then double click on "C1". We are now going to write specific clock function. It is similar to writing a script file. Click on Wizard.
This is where we are going to specify our input for CLK_H. If you look at your required waveform you will see that what is needed is an input that switches between high and low every 25
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nanoseconds. In the formula section, type in what I have typed in above. Basically, this is saying that you want an input that will switch between high and low every 25 nanoseconds. Highlight the text and push the up arrow until you see 15 in the window. Click on repeat. This should be enough pulses to accomplish your goal. When you are done, click ok.
J_H has a more unique waveform. Let's do it this way. Choose C2 for your J_H formula. Use the same steps as before but with different repeat values for this new formula. Now that you have the general idea, look at what waveform you need for K_H (C3) and program it in.
When you get done, it should look something like this. When it does, push Close.
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You can now see that C1-C3 are a different color than C4 indicating that they have been programmed.
Select CLK_H and click on C1. Repeat the process with C2 and C3 until you have the same picture as mine then close the Stimulator Selection area.
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Click on the Simulation Step (looks like footprints to the left of the 200ns window) several times and you should have an output that looks like mine. If you have straight lines or grey boxes, you should click on the upside down rakes to "scrunch" or expand your display.
3. EXAMPLE#3: HERE IS SOMETHING INTERESTING !!

am going to do the sequence recognizer first since I liked it the most. I felt it was neat the way it worked through each state on the state diagram. I wanted to develop a circuit that would give an output when it saw an input of "10010". There are many different ways to do this but I chose the way your text book uses. Here is my state diagram.
Below is the code I developed to perform this action. Take a few minutes to look at the code and you will be able to see the subtle way that it steps through each of the states. --recognizes sequence 10010 library ieee; use ieee.std_logic_1164.all; entity seq_rec is port(CLK, RESET, X: in std_logic; Z: out std_logic); end seq_rec;
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architecture process_3 of seq_rec is type state_type is (A, B, C, D, E); signal state, next_state : state_type; begin state_register: process (CLK, RESET) begin if (RESET = '1') then state <= A; elsif (CLK'event and CLK = '1') then state <= next_state; end if; end process; --step through each state based on state diagram next_state_func: process (X, state) begin case state is when A => if X = '1' then next_state <= B; else next_state <= A; end if; when B => if X = '1' then next_state <= B; else next_state <= C; end if; when C => if X = '1' then next_state <= B; else next_state <= D; end if; when D => if X ='1' then next_state <= E; else next_state <= A; end if; when E => if X = '1' then next_state <= B; else next_state <= A; end if; end case; end process; --output output_func: process (X, state) begin case state is when A => Z <= '0'; when B => Z <= '0'; when C => Z <= '0'; when D => Z <= '0';
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when E => if X = '0' then Z <= '1'; else Z <= '0'; end if; end case; end process; end; The new part here comes in with the testing of this project. It really isn't new, it is just a twist on lab 4 where you had to develop your input sequence instead of just taking one of the prearranged clocks. I am going to introduce you to a new term called a test bench. The basic thought behind a test bench is that a customer (in this case, me) will provide you with an input for your simulation. Create a new project and paste in the above recognizer code. Do the synthesis choosing the following. Target family: SpartanXL, S10XLPC84, speed -5. This is a good selection since it is one of the types of FPGAs we have here at UNM and it is the one you will be doing lab 7 with. Once Synthesis is completed successfully, go to simulation.
Chose the following signals once you are in simulation. It is common practice to put inputs on the top (choose first) and outputs on the bottom (choose last). Choose (STATE4, STATE0) to be on the bottom by choosing it last.
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Once you are done choosing signals and have closed (returned to the simulation page) then you should flatten out the bus like I have done above. It will provide you with a nicer product for this simulation.
Now go into choose stimulators. I want you to program in the following stimulators. For clock 1 (C1) and formula 0 (F0) put in the values from above. Here is the test bench part. For F1, paste in the following test sequence: L150nsH50nsL100nsH50nsL100nsH50nsL100nsH50nsL50nsH50nsL50nsH50nsL 50nsH150nsL100nsH50nsL50nsH238nsL338nsH314nsL203ns When yours looks like mine above, choose close. Assign FO, F1 and C1 as shown below.
Click on the feet enough times for you to get a good simulation like mine above This is a good way to watch your project actually stepping through the different states. Compare this to your state diagram to make sure you are stepping through the states as you predicted in your state diagram.
4.
EXAMPLE #4: COUNTER
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In this part of the project we are going to explore some unique concepts of counters. Start a new project and paste in the counter code below. --4-bit Binary counter with Reset library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count_4_r is port (CLK, RESET : in std_logic; Q : out std_logic_vector (3 downto 0); CO : out std_logic); end count_4_r; architecture behavorial of count_4_r is signal count : std_logic_vector (3 downto 0); begin process (RESET, CLK) begin if (RESET = '1') then count <= "0000"; elsif (CLK'event and (CLK = '1') ) then count <= count + "0001"; end if; end process; Q <= count; CO <= '1' when count = "1111" else '0'; end behavorial;
Synthesis should be performed in the same way you did with the sequence recognizer.
Go to simulation and select the following signals for simulation. When you have selected the signals, go back to the main simulation window. Do not flatten the bus like you did in the first project.
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Code in the following formula for F0. It is going to be used for your reset. Once you have coded in F0, choose Bc (binary counter - little yellow/green dot) zero (far right dot) for your clock.
Now you can see what happens. Your counter is turned off until the reset goes low. Once the reset goes low, your counter starts counting from 1-16(F) in hex. Once it gets to 16, you get an output on CO.
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Getting Started With The XILINX Foundation F2

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Getting Started With The XILINX Foundation F2

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vsdt_Lab_Tute_02

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

. Open a new project

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

Figure 5: Symbol for the quad 2:1 MUX.

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

Figure 1 - 1-Bit Full Adder Component

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

Figure 2 - 4-Bit Unsigned Adder

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

Figure 1 - A 4-to-1 Pictorial Description of a Multiplexer

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

GETTING STARTED WITH THE XILINX FOUNDATION TOOLS: USER MANUAL

EXAMPLES THAT GUIDE YOU BY HAND: