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Challenges Regarding Parallel Connection of SiC JFETs

Dimosthenis Peftitsis, Student Member, IEEE, Roman Baburske, Jacek Rabkowski, Member, IEEE, Josef Lutz, Georg Tolstoy, Student Member, IEEE, and Hans-Peter Nee, Senior Member, IEEE

AbstractState-of-the-art silicon carbide switches have current ratings that are not sufciently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufcient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gatesource reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gatesource reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gatesource reverse breakdown voltages is sufciently large, there might be no possibility for a stable offstate operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver congurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses signicantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed. Index TermsJunction eld-effect transistor (JFET), parallelconnected switches, pinch-off voltage, reverse breakdown voltage of the gate, silicon carbide (SiC).

I. INTRODUCTION ILICON carbide (SiC) JFETs are highly promising for future application in, for instance, hybrid electric vehicles [1][3], converters for photovoltaic power generation [4], power-factor correction circuits [5][7], and high-power applications such as static synchronous compensators, HVDC transmission [8], and high-power or high-power-density motor drives [9][12]. The reasons to the wide area of application are that the SiC JFET can exhibit low on-state losses, low switching losses, and high-temperature capability simultaneously [13][17]. In many applications, high current ratings are required. The available chip sizes at present and in a foreseeable future will, however, not be sufcient for single-chip highcurrent switches. The reason to this is that this would result in very low fabrication yields. Consequently, the only ways to proceed are to build multichip modules [18][21] or to parallelconnect several single-chip components. In both cases, it is essential to keep track of both steady-state and transient current sharing of the parallel-connected chips. There are, basically, four device parameters affecting these issues. The rst one is the on-state resistance, which must have a low spread and a positive temperature coefcient for stable steady-state current sharing. Based on the experience from the measurements presented in the following, however, this does not seem to be a major problem even if the current sharing is inuenced to some extent. The second one is the pinch-off voltage, which determines at what gate voltage the device enters the forward conduction region [22]. Obviously, a spread in this parameter among a set of parallel-connected chips will have a considerable effect on the transient current sharing during the turn-on and turn-off transitions. The third critical parameter is the reverse breakdown voltage of the gate, Vbr,g [23], which is the maximum allowable reverse-bias voltage that can be applied to the gate. If the spread in the two latter parameters is too large, there might be no possibility for a stable off-state operation, as one chip may be driven into gate breakdown before another chip is turned OFF. This problem can be solved, to some extent, by sorting the chips with respect to the relevant parameters, but as will be explained in the following, the spread in the pinch-off voltage may anyway cause signicant variations in switching losses among the parallel-connected chips unless the sorting is very rigorous. Additionally, depending on the device design, the temperature dependence of the breakdown voltage may affect both the sorting criteria and the high-temperature characteristics of the parallel-connected switch. Furthermore, the difference in static transfer characteristics among the devices also counts as an important parameter which affects the performance of the

Manuscript received November 8, 2011; revised March 26, 2012; accepted June 18, 2012. Date of current version October 12, 2012. This paper was presented in part at the International Conference on Power Electronics-Energy Conversion Congress and Exposition Asia 2011, Jeju, Korea, MayJune 2011. Recommended for publication by Associate Editor E. Santi. D. Peftitsis, J. Rabkowski, G. Tolstoy, and H.-P. Nee are with the Laboratory of Electrical Energy Conversion Laboratory, School of Electrical Engineering, KTH Royal Institute of Technology, SE-10044 Stockholm, Sweden (e-mail: dimost@kth.se; rabkow@kth.se; gtolstoy@kth.se; hansi@kth.se). R. Baburske and J. Lutz are with the Faculty of Electrical Engineering and Information Technology, Chemnitz University of Technology, 09126 Chemnitz, Germany (e-mail: roman.baburske@etit.tu-chemnitz.de; josef.lutz@etit. tu-chemnitz.de). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2206611

0885-8993/$31.00 2012 IEEE

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parallel connection. Even if the devices have exactly the same pinch-off voltages, there might be differences in the transfer characteristics, i.e., different transconductances [24]. A fth factor, which is not a device parameter, that affects the parallel connection is the placement of the devices in the circuit layout. In particular, a symmetrical placement of the devices might result in uniformly distributed parasitic inductances not only between the JFETs themselves, but also between the JFETs and other components of the circuit (e.g., diodes, etc.) [25][28]. An investigation on the parallel connection of normally OFF SiC JFETs and SiC bipolar junction transistors is presented in [29]. That study, which is the rst of its kind and a rst approach to shed light on problems with parallel connection of SiC devices, basically focuses on the dependence of various static and dynamic characteristics of the devices on the temperature. In this paper, therefore, an extensive experimental analysis of problems with parallel connection of normally ON SiC JFETs is performed. Additionally, possible remedies to the observed adverse phenomena are suggested. It is well known that gate drivers for power semiconductor devices can profoundly inuence the switching performance of the devices. In this paper, therefore, a recently suggested gate driver [30] is used in two different congurations which potentially could inuence the effectiveness of the parallel connection. The temperature dependence of the pinch-off and the reverse breakdown voltage of the gate and the importance of keeping a safety margin between those two voltages are analyzed in Section II. This section also presents the parameter spread and temperature dependence of the on-state resistance and the I V characteristics of the SiC JFETs. Section III shows the switching performance of the parallel-connected SiC JFETs having the same and different Vbr,g . This was performed using three different main-circuit layouts in order to investigate the inuence of parasitic elements of the main circuit. The switching losses of parallel-connected SiC JFETs are treated in Section IV. Finally, a discussion on problems with parallel connection of normally ON SiC JFETs is given in Section V. Section VI concludes this paper. II. TEMPERATURE DEPENDENCE AND SPREAD OF SiC JFET PARAMETERS Before presenting the switching performance of parallelconnected SiC JFETs, it makes sense to investigate the temperature dependence and spread of different parameters inuencing the parallel connection. First, the temperature dependences of the pinch-off voltage, Vbr,g , and the on-state resistance are investigated. Next, it is shown that there might also be variations in the I V characteristics among different devices. From these investigations, the potential problems regarding parallel connection of SiC JFETs are also identied. For the presented investigation, two types of normally ON SiC JFETs have been used, which both were available in engineering samples at the time when the experiments were performed. The rst one (Supplier 1) is the so-called lateral channel JFET (LCJFET) and a graphical schematic of its structure is shown in Fig. 1. The range of the typical pinch-off voltages of this JFET design is between 16 and 26 V, while Vbr,g equals

Fig. 1.

Graphical illustration of the cross section of the LCJFET.

Fig. 2. Graphical illustration of the cross section of the depletion-mode vertical trench JFET.

approximately 34 V. A nice feature of this structure, especially with respect to the clamping during the blanking time, is the antiparallel body diode which is formed by the p+ source side, the n drift region, and the n++ drain. Nevertheless, the forward voltage drop of the body diode is higher than the on-state voltage drop of the channel, which mainly conducts the current in the reverse direction. The second JFET design (Supplier 2) that has been taken into account in this study is the depletion-mode vertical trench JFET as shown in Fig. 2. This device can be either normally ON or normally OFF depending on the thickness of the vertical channel and the doping levels of the structure. Typically, the pinchoff voltage of this JFET equals 5 V, while Vbr,g is typically between 19 and 29 V. This JFET design has no body diode, but the load current can ow in the reverse direction through the channel [8], [31]. Table I summarizes the basic parameters of the SiC JFETs which have been used for the measurements in the section. A. Temperature Dependence of the Pinch-Off and the Reverse Breakdown Voltage of the Gate It is not only the pinch-off voltage, but also Vbr,g that affect reliable and stable operation of parallel-connected normally ON JFETs. The margin between these two voltages must be large enough in order to ensure that when the negative gatesource

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TABLE I BASIC PARAMETERS OF THE SiC JFETS

Fig. 4. Pinch-off and breakdown voltage margin for two temperatures (a) 23 C and (b) 150 C for devices No. 126 and No. 154.

Fig. 3. Static transfer characteristics of SiC JFET No. 126 for two different temperatures.

Fig. 5. Gate driver of the normally ON SiC JFET showing the solution to the breakdown voltage variations with temperature.

voltage is supplied, the device is properly turned OFF without forcing the gate into reverse breakdown. Since SiC devices potentially have excellent hightemperature properties [20], it makes sense to investigate the temperature dependences of the pinch-off voltage and Vbr,g . From experiments, on the one hand, it is found that the pinchoff voltage is almost temperature independent as shown from the static transfer characteristics in Fig. 3. Vbr,g , on the other hand, might have (depending on the type of the device) a negative temperature coefcient, which means that its absolute value is decreasing when the temperature is increasing. In Fig. 4, experimental results showing the temperature dependence of Vbr,g for two different LCJFETs are presented. It is obvious from Fig. 4 that the safe operating region (indicated with short vertical lines in the graphs) is reduced when the temperature is increased. A serious problem is, therefore, faced when two or more devices with different values of Vbr,g or even different pinch-off voltages are connected in parallel. This problem is accentuated at high temperatures, because the reverse breakdown voltage of the gate is reduced at high temperatures for LCJFETs. As shown in Fig. 4, the operating region in the off-state might be very small or even negative if the parallel-connected devices are unfavorably matched. A solution to this problem could be to use a supply voltage to the gate driver that is more negative

than Vbr,g , and to limit the leakage current through the gate by means of a resistor. A circuit for normally ON SiC JFETs that realizes this method has already been presented in [30]. The operating principle of the circuit is mainly based on the choice of the negative voltage supply Vs and the DRp C parallel network. The parallel network consists of a high-value resistor Rp , a diode D, and a capacitor C . During the on-state of the device, the buffer output voltage Vg equals zero and the JFET is conducting a drain current. When the turn-off process starts, the buffer output voltage Vg is equal to the supply voltage Vs and a high negative gate current peak is provided through the capacitor C and the gate resistor Rg to the gatesource junction of the device. This current is shown with the dashed line in Fig. 5. As the supply voltage Vs is chosen to a more negative voltage than Vbr,g , the parasitic capacitance of the gatesource junction Cg s is charged to a voltage that equals Vbr,g . Simultaneously, the gate capacitor C is also charged and the voltage drop across it equals the difference between the supply voltage Vs and Vbr,g . During steady-state operation in the off-state, a low leakage current is only required in order to keep the JFET OFF. This current is supplied through the resistor Rp as shown with the solid line in Fig. 5. If the value of Rp is chosen with care, it is, therefore, impossible to cause a junction breakdown due to a high continuous negative gate leakage current. Nevertheless,

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-22.2
Reverse breakdown voltage of the gate, V [V] br,g

On-state resistance variation with temperature 200 SiC JFET No1 SiC JFET No2 SiC JFET No3 SiC JFET No4

-22.3

180
On-state resistance [m ]

-22.4

160 140 120 100

-22.5

-22.6

-22.7

80 20
-22.8 20 40 60 80 100 Temperature [ oC] 120 140 160

40

60

80 100 Temperature [oC]

120

140

160

Fig. 6. Measurements of the temperature dependence of the reverse breakdown voltage of the gate of a vertical trench JFET.

Fig. 7. On-state resistance variation with temperature for four different SiC JFET devices.

C. Variation in Static Transfer Characteristics The I V transfer characteristics of the normally ON SiC JFETs might be different among different devices. Fig. 8(a) and (b) shows the static transfer characteristics at various gate source voltages for two different samples of the same type of normally ON SiC JFET. Ideally, the I V waveforms for these devices should be identical when looking at the same gate source voltage. However, comparing two traces in Fig. 8(a) and (b), it is obvious that there is a spread in the I V curves. For instance, for the gatesource voltage Vg s = 5 V, the device shown in Fig. 8(a) is still conducting the current, while the device in Fig. 8(b) has been turned OFF. Moreover, comparing the traces for Vg s = 4 V [heavy-width line in Fig. 8(a) and (b)], it is clear that the characteristics of the two devices are very different, even if both are in the on-state. A certain spread can be observed at every value of Vg s shown in the graphs resulting in different values of transconductance for the SiC JFETs. These dissimilarities affect the effectiveness of the parallel-connected devices, especially during the switching transitions. At turn-on, for instance, the device with the lowest transconductance turns ON slightly slower than the other one. III. EXPERIMENTAL RESULTS Apart from the investigation of the steady-state characteristics at elevated temperatures and generally the various parameters of the devices which play an important role for the feasibility of the parallel connection, it is also important to study the switching performance of the devices when they are parallelconnected. Parallel connection of normally ON SiC JFETs has been experimentally investigated by using the devices listed in Table II. In total, three SiC JFETs have been selected with respect to their reverse breakdown voltages of their gates Vbr,g and they were tested in pairs using a standard double-pulse experimental setup. The reason for choosing Vbr,g as a sorting criterion is that this quantity can be measured easily. In Fig. 9, experimental results indicating that differences in Vbr,g are correlated to differences in the pinch-off voltages of the SiC JFETs are shown. Fig. 9 shows the static transfer characteristics of two devices

it is possible to adjust the switching speed to any desired speed by selecting an adequate value of Rg . For the depletion-mode vertical trench JFETs, Vbr,g is almost unaffected by variations in temperature. In Fig. 6, results from measurements on temperature dependence of Vbr,g for vertical trench JFETs are shown. In this case, the temperature dependence is almost negligible. This means that the margin between the pinch-off voltage and Vbr,g is almost unaffected by variations in temperature. In the opinion of the authors, this is a signicant advantage of the vertical trench JFETs compared to LCJFETs. Due to this fact, and to the unavailability of new versions of LCJFETs, only vertical trench JFETs are considered in the following.

B. On-State Resistance Variation It is not only the reverse breakdown voltage of the gate and the pinch-off voltage of the SiC JFET which affect the effectiveness of the parallel connection. Due to the slightly different doping concentrations and the slightly different channel widths of the devices, there may also be differences on the on-state resistances. This kind of variations among various devices also plays a crucial role when SiC JFETs are connected in parallel. Especially, during steady-state operation, these variations might cause mismatches in the current sharing through the devices which results in different on-state losses and, consequently, different temperature rises among the JFETs. Fig. 7 shows the on-state resistance variations with respect to the temperature for four different SiC JFET devices. As can be seen, the spread of the on-state resistances among the JFETs approximately (but note entirely, see SiC JFETs Nos. 3 and 4) remains constant as the temperature increases. Not surprisingly, the sorting of the SiC JFETs with respect to the on-state resistances seems to be the solution to overcome the mismatches in the steady-state current sharing.

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20 18 16 14 Vgs=0 V Vgs=-1 V Vgs=-2 V Vgs=-3 V Vgs=-4 V Vgs=-5 V

20 18 16 14 Vgs=0 V Vgs=-1 V Vgs=-2 V Vgs=-3 V Vgs=-4 V Vgs=-5 V

Drain current, Id [A]

Drain current, Id [A]

12 10 8 6 4 2 0 -2 0 1 2 3 4 Drain-source voltage, Vds [V] 5 6

12 10 8 6 4 2 0 -2 0 1 2 3 4 Drain-source voltage, Vds [V] 5 6

(a)
Fig. 8.

(b)

Static transfer characteristics at various gatesource voltages for two different SiC JFET devices: (a) device No 21 and (b) device No 50. TABLE II REVERSE BREAKDOWN VOLTAGES OF THE GATE OF THE DUT

200 JFET No. 50, Vbr,g = -28.0 V JFET No. 45, Vbr,g = -21.1 V 150
Drain current [mA]

100

50

0 -6

-5.5

-5 -4.5 Gate-source voltage [V]

-4

-3.5

Fig. 9. Measured static transfer characteristics showing the relevance between the reverse breakdown voltage of the gate and the pinch-off voltage.

having a difference of approximately 7 V in Vbr,g . The corresponding difference in the pinch-off voltages was found to be 0.5 V. The device with the less negative Vbr,g also has the less negative pinch-off voltage. Even if this is not a solid statistical proof of the correlation between the Vbr,g and the pinch-off voltage, it is a strong indication that the Vbr,g can be used as a sorting criterion. Table II shows the reverse breakdown voltages of the gates of the devices under test (DUT). As can be seen from this table, two of the DUTs (Nos. 20 and 50) have approximately the same reverse breakdown voltage of the gates. The

other JFET, No. 21, has a different reverse breakdown voltage of the gate compared to the other two devices. Thus, two sets of measurements have been performed, one using the devices with approximately the same Vbr,g (Nos. 20 and 50), and the other one using devices Nos. 50 and 21, which have different values of Vbr,g . The schematic of the double-pulse setup is shown in Fig. 10. It consists of a direct voltage source Vdc , a SiC Schottky diode, an inductor L, and the two parallel-connected SiC JFETs. Fig. 11 shows a graphical schematic of the circuit layout. A gate driver which was proposed in [30] is used and two different congurations of this driver have been designed and used for the parallelconnected SiC JFETs. The rst conguration uses two separate DRp C parallel networks (each one drives a single JFET), which both are fed from the same power supply as shown in Fig. 10(a). On the other hand, a single DRp C network is employed in the second gate-driver design and it is fed from a single voltage supply as shown in Fig. 10(b). In the second conguration, both parallel-connected JFETs are driven by the same network. The stray capacitances of the two SiC JFETs, which affect their switching performance, are also shown in Fig. 10. Photographs of the double DRp C and the single DRp C gate-driver circuits are shown in Fig. 12(a) and (b), respectively. Table III summarizes the parameters of the experimental setup which are the same for both gate-driver congurations. The parameters of the gate drivers have been adapted in such a way that the switching performance of the drivers themselves will be identical for the double and the single DRp C networks.

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SiC Schoky Diode

CD,par L

CL,par

SiC Schoky Diode

CD,par L

CL,par

Vdc Rp1 D1 Rg1 C1 Cgs,1 Cdg,1 J1 Cds,1 Rg2 C2 Cgs,2 Rp2 D2 Cdg,2 J2 Cds,2

Vdc Cdg,1 J1 Cds,1 Cgs,1 Cgs,2 Cdg,2 J2 Cds,2

IC driver

IC driver

Rp,s Ds Cs Rg,s

-Vs

-Vs

-Vs

(a)
Fig. 10.

(b)

Schematic diagram of the double-pulse test setup (a) with double DR p C networks and (b) with a single DR p C network.

Fig. 11.

Graphical schematic of the test-circuit layout. (a) Top-side view. (b) Front-side view.

This practically means that the gate capacitor for the single DRp C network Cs equals two times the capacitor for the double DRp C network C1 (or C2 ), while the gate resistor for the single one Rg ,s has been adjusted taking into account the internal resistance of the integrated-circuit driver (IC driver) Rdrv , and the resistance of the SiC JFET package Rpac , as well (see Fig. 13). It is therefore obvious that Rg ,s will not be equal to half of Rg 1 (or Rg 2 ). Instead, the total resistance from the IC driver to the gatesource junction of the JFET for the single DRp C equals half of the corresponding one for the double DRp C net-

work. Fig. 13(a) and (b) shows the resistive paths during the turn-on process for the two gate-driver congurations. From these drawings, it is clear that the resistances which are shown inside the dashed line boxes are xed and thus they cannot be adjusted. However, as already analyzed previously, the external gate resistors Rg 1 , Rg 2 , and Rg ,s can be properly adjusted in order to reach a desirable switching performance of the drivers. The parameters of the gate drivers are shown in Table IV. From Fig. 11, it is clear that the physical dimensions of the gate circuits are small because the terminals of the JFETs are

IC driver

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Fig. 12.

Gate-drive circuit prototypes (a) with a double DR p C network and (b) with a single DR p C network.

TABLE III PARAMETERS OF THE EXPERIMENTAL SETUP

IC driver Rdrv Rg2 Rpac

-Vs
(a)

-Vs

Fig. 13. Resistive paths for the two gate-driver congurations (a) with a double DR p C network and (b) with a single DR p C network. TABLE IV PARAMETERS OF THE GATE-DRIVER CIRCUITS

soldered directly to the terminals of the gate-driver printed circuit boards. Moreover, it is clear from Fig. 12(a) and (b) that the paths of the gate current in the two gate-driver designs are quite similar. This leads to the conclusion that 1) the stray inductance of the gate circuit is very low, and 2) no signicant difference in stray inductance for the two gate-driver designs is anticipated. Various experimental results showing the switching performance and the switching losses under the parallel connection are presented in the following. Section III-A deals with the

-Vs 0

IC driver Rdrv Rg1 Rpac

IC driver Rdrv Rg,s

Rpac Rpac

(b)

Fig. 14.

Graphical illustration of the rst circuit layout, L1.

investigation of the DUT with the same Vbr,g and Section IIIB presents the experiments on the DUT with different Vbr,g . Both the double and the single DRp C network gate drivers have been tested in the two different cases of parallel-connected SiC JFETs. Furthermore, the positions of the DUTs have been changed in order to investigate the effect of the parasitic inductances of the circuit layout on the switching performance of the parallel-connected SiC JFETs. In particular, three different circuit layouts regarding the placement of the SiC JFETs and Schottky diode have been used. A graphical illustration of the rst layout, L1, is shown in Fig. 14. The SiC JFET No. 50 is placed closer to the Schottky diode, while the SiC JFET No. 20 (or No. 21 in the case where the JFETs have different breakdown voltages of the gates) is mounted on the right side of No. 50. The second circuit layout L2 is depicted in Fig. 15 where the device No. 20 (or No. 21) is placed closer to the Schottky diode and No. 50 on the right side of the circuit. A symmetrical placement of the devices is shown in Fig. 16 with the third circuit

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30
Currents [A]

Current transients for 50,20 with double DRC (layout L1) 30

SiC JFET No.50

20 10 0 1.35 1.4

Currents [A]

20 10 0

SiC JFET No.20

30
Currents [A]

1.45 1.5 1.55 4 4.05 4.1 4.15 -6 (a) (b) x 10 Current transients for 20,50 with double DRC (layout L2) 30
Currents [A]

4.2

4.25
-6

x 10

SiC JFET No.20

20 10 0 1.05 1.1

20 10 0

SiC JFET No.50

30
Currents [A]

1.15 1.2 1.25 3.7 3.75 3.8 3.85 -6 (c) (d) x 10 Current transients for 50,20 with double DRC (layout L3) 30
Currents [A]

3.9

3.95
-6

x 10

SiC JFET No.20

20 10 0 1 1.1 (e) Time [s] 1.2 x 10

-6

20 10 0 3.65

SiC JFET No.50

Fig. 15.

Graphical illustration of the second circuit layout, L2.

3.7 3.75 (f) Time [s]

3.8

3.85 x 10
-6

Fig. 17. Switching transients for the SiC JFETs having the same reverse breakdown voltage of the gates when a double DR p C network is employed and various circuit layouts are used. (a) Turn-on and (b) turn-off transients using circuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2. (e) Turn-on and (f) turn-off transients using circuit layout L3.

Fig. 16. Graphical illustration of the third circuit layout, L3, showing a symmetrical placement of the devices.

layout L3. The SiC Schottky diode is mounted in the middle of the circuit with the two JFETs placed aside. In this case, it is believed that the parasitic inductances of the circuit are equally distributed among the JFETs, while for the rst two cases the parasitic inductance is lower between the diode and the JFET which is placed closer to it. It must be noted that the inductor L is connected in the middle of the distance between the two DUTs for all three cases. A. DUT With the Same Reverse Breakdown Voltage of the Gate In this section, the parallel connection of two SiC JFET devices having the same Vbr,g is presented. The tests were subdivided into two main sets, one for each gate-driver conguration (single and double DRp C networks), whereas each of these sets is also subdivided into three subcases based on the placement of

the DUTs and diode as explained previously. The JFETs currents have been measured using Rogowski coils (PEMUK CWT06) which are connected on the drain pin of each device. The current waveforms during turn-on and turn-off of the two SiC JFETs having the same Vbr,g , when a double DRp C network is employed and the DUTs are placed according to layout L1, are shown in Fig. 17(a) and (b), respectively. As can be seen from Fig. 17(a), the turn-on transition takes approximately 40 ns for both devices. Even if the two JFETs have approximately the same values of the Vbr,g , there is a signicant difference in the recorded waveforms. The turn-off transients are presented in Fig. 17(b), where turn-off times of approximately 30 ns are observed. Transient current mismatches are obtained both during the turn-on and turn-off transitions. In particular, a current overshoot with higher magnitude is obtained for the JFET No. 50 compared to JFET No. 20 during the turn-on transient, while a similar phenomenon appears during the turn-off process. It is believed that the main reason for this might be the lower onstate resistance of DUT No. 50. Another possible contribution to the difference may be a difference in the static transfer characteristics of the two JFETs (transconductance). The layout of the circuit might also affect the switching performance of the parallel-connected devices due to the different parasitic inductances not only between the JFETs themselves, but also between the JFETs and the SiC Schottky diode. A closer examination of the circuit layout L1 shows that the inductive path (parasitic inductance) from JFET No. 50 to the SiC Schottky diode is shorter than the one from JFET No. 20. Moreover, the parasitic inductances between the JFETs and the connection point

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of the inductor L also affect the switching performance of the JFETs. It is, therefore, necessary to design the circuit layout in such a way that the various parasitic inductances will be equally distributed among the devices. The second subset of measurements was performed by interchanging the positions of the two parallel-connected SiC JFETs, whereas the diode was kept in the same position as in the rst circuit layout, L1. The double DRp C gate driver was also employed in this case. Fig. 17(c) and (d) shows the turnon and turn-off switching transients, respectively. The turn-on time equals approximately 35 ns for both DUTs and the corresponding turn-off time is approximately 30 ns. As can be seen from Fig. 17(c), the switching speed of the two JFETs is approximately the same, while the spread in the current overshoot during the turn-on process has been reduced compared to the case of layout L1. However, the spread in the steady-state current is still large due to the spread in the on-state resistances of the DUTs. Moreover, it is the hypothesis of the authors that the differences in the resistances of the current paths in the circuit layout might also contribute to the differences in current. Even though the turn-off transient looks the same as in the previous layout case [see Fig. 17(b)], the delay between the two currents is smaller in the present case L2. Nevertheless, the current overshoot of No. 50 is still higher than for the JFET No. 20. There is a difference in the currents just before the turn-off process starts. Again, this is believed to be caused by differences in on-state resistances. A closer examination of the current traces of the two JFETs during the turn-off transition reveals a phenomenon which is specic to the parallel connection. One of the JFETs conducts a negative current during approximately 10 ns and the other one has an additional positive component in antiphase with the negative current. The explanation to this is a series resonance between the series connection of the two drain source capacitances of the two JFETs and the series connection of the two stray inductances representing the connections to the JFETs. This phenomenon is observed in several of the gures in the following. The turn-on and turn-off processes of the DUTs when they are symmetrically placed in the circuit (circuit layout L3) are shown in Fig. 17(e) and (f), respectively. The switching speed during the turn-on transient is approximately the same for both JFETs. As in the previous two cases, current mismatches are observed. In particular, a slightly higher current is owing through device No. 50 than No. 20 during the transient period. Moreover, the steady-state current of JFET No. 50 is also higher than JFET No. 20 due to a difference in on-state resistance. It must be noted that in the case of symmetrical placement of the devices, the current overshoot during the turn-on process has been eliminated because the inductive paths between the JFETs and the diode are almost identical. On the contrary, the switching speeds of the two DUTs during the turn-off process are not equal, while there is a time delay between the two currents. Moreover, a resonance is obtained due to the same reason as explained previously. Fig. 18(a)(f) shows the switching transients for the devices having the same reverse breakdown voltages of the gates using three different circuit layouts, when a gate driver with a single DRp C network is employed. The switching transients for both

30
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Current transients for 50,20 with single DRC (layout L1) 30

SiC JFET No.50

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3.95 x 10

4
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Fig. 18. Switching transients for the SiC JFETs having the same reverse breakdown voltage of the gates when a single DR p C network is employed and various circuit layouts are used. (a) Turn-on and (b) turn-off transients using circuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2. (e) Turn-on and (f) turn-off transients using circuit layout L3.

DUTs using the rst circuit layout L1 are depicted in Fig. 18(a) and (b). Even though the transient current sharing during the turn-on process is not good, the turn-off process seems to be improved with respect to current sharing between the JFETs comparing to the corresponding case with the double DRp C gate driver [see Fig. 17(b)]. An improved switching performance of the parallelconnected SiC JFETs comparing to Fig. 18(a) and (b) is obtained when they are placed according to the second circuit layout L2. Fig. 18(c) and (d) illustrates the turn-on and turn-off processes, respectively. In this case, the difference in the currents during the turn-on transient has been reduced. Additionally, the turnoff process is also improved, characterized by fewer oscillations after turn-off. Finally, Fig. 18(e) and (f) shows the switching transients for the parallel-connected JFETs when they are placed in a symmetrical circuit layout (L3). As in the previous case with symmetrical positioning of the DUTs, the current overshoot during turn-on has been eliminated. On the contrary, a difference in the steady-state currents still exists due to the difference in the on-state resistances of the two devices. During the turn-off process, a current overshoot of the currents and a resonance after the turn-off process are obtained, while a delay in the turn-off processes of the two DUTs is also observed in Fig. 18(f). B. DUT With Different Reverse Breakdown Voltages of the Gates The second set of measurements deals with the investigation of parallel-connected normally ON SiC JFETs having a

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Fig. 19. Switching transients for the SiC JFETs having different reverse breakdown voltages of the gates when a double DR p C network is employed and various circuit layouts are used. (a) Turn-on and (b) turn-off transients using circuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2. (e) Turn-on and (f) turn-off transients using circuit layout L3.

Fig. 20. Switching transients for the SiC JFETs having different reverse breakdown voltages of the gates when a single DR p C network is employed and various circuit layouts are used. (a) Turn-on and (b) turn-off transients using circuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2. (e) Turn-on and (f) turn-off transients using circuit layout L3.

difference in Vbr,g of approximately 9 V. Such a high difference in Vbr,g (and consequently in the pinch-off voltages, see Fig. 9) might cause mismatches in the transient currents, and therefore unequal distribution of the switching losses. As in the previous section, the parallel connection of SiC JFETs Nos. 50 and 21 has been investigated using both congurations of the gate drivers and by interchanging the positions of the DUTs according to the graphical illustrations shown in Figs. 1416. Figs. 19 and 20 illustrate the turn-on and turn-off switching transients when a gate driver with a double and a single DRp C network is used, respectively. Similarly to the previous section, where DUTs having the same Vbr,g were employed, the switching performance of devices Nos. 50 and 21 was investigated using the three different circuit layouts. The turn-on and turnoff processes for each circuit-layout case are depicted in a single row in Figs. 19 and 20. Substantial current mismatches are obtained during the turnon transient [see Fig. 19(a)] where the DUTs are placed according to circuit layout L1 and when a double DRp C gate driver is employed. In the opinion of the authors, the main reason for the large current difference are differences in Vbr,g and differences in parasitic inductances. Device No. 21 has a less negative Vbr,g than device No. 50, and therefore, the gatesource parasitic capacitance of JFET No. 21 is charged at a lower (in absolute value) voltage than No. 50. Thus, during the turn-on process, the gatesource capacitance of device No. 21 is discharged faster than of device No. 50. It is obvious that the switching losses dominate for the device which conducts the highest current and a destructive temperature rise might result if the switching frequency is sufciently high.

Even when a symmetrical placement of the DUTs was used, current mismatches were obtained when a double DRp C network was employed as can be seen in Fig. 19(e) and (f). However, an improved switching performance of the parallelconnected devices Nos. 50 and 21 can be observed in Fig. 19(c) and (d) even if the circuit was not symmetrical. It is the hypothesis of the authors that in this case the combination of differences in parasitic inductance and differences in pinch-off voltage was very fortunate. The switching performance of the devices with different reverse breakdown voltages of the gates when they are driven by a single DRp C network is shown in Fig. 20. It is obvious that the turn-on processes in all three circuit-layout cases have been improved compared to the case where a double DRp C network was employed. There is still a small difference in the currents, which might not affect the distribution of the switching losses among the parallel-connected devices. An astonishing improvement in the turn-off processes compared to Fig. 19 is also observed in Fig. 20. The overshoot in the current during the turn-off process has been signicantly decreased, but on the other hand, the oscillations after the turn-off still exist. Considering the gate-driver schematic shown in Fig. 6, the improved performance of the parallel-connected JFETs with different reverse breakdown voltages of the gates when a single DRp C network is used can be analyzed. The gate driver is supplied by a voltage which is more negative than the most negative reverse breakdown voltage of the gates, and at the same time, a high-value resistance Rp limits the gate current in order to avoid avalanche of the gatesource junction. While the parallelconnected devices are kept in the OFF state, the voltage drop

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TABLE V SWITCHING LOSSES FOR THE DUTS WITH THE SAME REVERSE BREAKDOWN VOLTAGE OF THE GATES WHEN A DOUBLE DR p C NETWORK IS USED

TABLE VI SWITCHING LOSSES FOR THE DUTS WITH THE SAME REVERSE BREAKDOWN VOLTAGE OF THE GATES WHEN A SINGLE DR p C NETWORK IS USED

TABLE VII SWITCHING LOSSES FOR THE DUTS WITH DIFFERENT REVERSE BREAKDOWN VOLTAGES OF THE GATES WHEN A DOUBLE DR p C NETWORK IS USED

across the single DRp C network equals the difference between the supply voltage and the least negative reverse breakdown voltage of the gates. Before the turn-on process, the gate voltages of the two parallel-connected devices are identical (as explained previously). As a consequence, the gate voltage will also follow each other during the turn-on process. Similarly to the turn-on process, during the turn-off process, the gate voltages of the two devices will be identical, which enables approximately equal switching times and quite good transient current sharing (see Fig. 20). IV. SWITCHING LOSSES Apart from the switching transients of the parallel-connected SiC JFETs as such, it is also important to investigate the associated switching losses. The switching losses have been determined using measured data for the current and the voltage of the devices. Both gate-driver congurations and the two alternative combinations of the DUTs have been considered. Furthermore, the switching losses have been measured for all three circuit layouts in order to investigate the effect of the positioning of the DUTs on them. Section IV-A presents the switching losses of the parallel-connected SiC JFETs which have the same Vbr,g when both double and single DRp C networks are employed

(see Tables V and VI, respectively). The switching losses for the DUTs having the same Vbr,g are shown in Section IV-B where both double and single DRp C networks are considered (Tables VII and VIII, respectively). It must be noted that the energy that is stored and released from the stray capacitances of the devices also contributes to the measured turn-on and turn-off switching losses shown in the third and the fourth columns of Tables VVIII. Thus, the real switching losses equal the losses shown in these two columns excluding the power transfer of the stray capacitances of the two JFETs. The relation of the power transfer involving the stray capacitances to the actual switching losses is directly related to the switching speed. The stored energy in the stray capacitances depends mainly on the voltage, while the switching loss energy is proportional to the duration of the switching transient. In other words, if the switching speed would be signicantly reduced, Tables VVIII (third and fourth columns) would show the real values of the device switching losses at turn-on and turn-off, respectively. It is, therefore, obvious that a correct estimation of the real switching losses of the devices can only be done if the sum of the switching losses at turn-on and turn-off is studied, and not on the turn-on and turn-off contributions separately. Thus, the actual switching losses per parallel-connected device are shown in the fth column of Table VVIII, while the last

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TABLE VIII SWITCHING LOSSES FOR THE DUTS WITH DIFFERENT REVERSE BREAKDOWN VOLTAGES OF THE GATES WHEN A SINGLE DR p C NETWORK IS USED

column shows the total switching losses caused in the pair of parallel-connected JFETs. A. DUT With the Same Reverse Breakdown Voltage of the Gate The switching losses when two SiC JFETs having the same Vbr,g and they are driven by a gate driver using a double DRp C network are shown in Table V for the three various circuit layouts. As it has already been mentioned previously, studying the turn-on and turn-off losses separately might not be the most accurate way in order to draw any conclusions about the temperature rise in the DUTs. Nevertheless, by looking in the fth column of Table V, where the total switching losses per device are presented, a more clear indication about the loss distribution among the devices can be seen. Even though the total losses of both JFETs are approximately the same when they are placed according to the circuit layouts L1 and L2, the loss distribution among the JFETs differs for these two layouts. When L1 is used, the losses caused in device No. 20 equals half the corresponding losses in device No. 50, which will be hotter especially at higher switching frequencies. On the other hand, an almost uniform loss distribution is obtained in L2. Finally, in the case of L3, the total losses caused in JFET No. 50 are approximately 60% higher than the losses in the device No. 20. However, it is worth to look in the nal column of Table V, where it can be seen that the sum of the losses for both DUTs is lower when the circuit layout L3 is used. This is basically due to the different switching performance of these two devices as shown in Fig. 17. Table VI summarizes the switching losses of the parallelconnected SiC JFET when a single DRp C network is employed and the DUTs have the same Vbr,g . Similar to the previous case, an uneven distribution of the switching losses per device is also obtained when either layout L1 or L3 is used. On the other hand, the total losses for both devices (last column of Table VI) have been reduced at approximately 5%. The reason for this is the improved switching performance that has been obtained when a single DRp C network is used instead of a double one, as shown in Fig. 18 in Section III. B. DUT With Different Reverse Breakdown Voltages of the Gate Tables VII and VIII show the switching losses caused in the parallel-connected SiC JFETs for various circuit layouts when a double and a single DRp C networks are employed, respectively.

Due to the transient current mismatches between the two DUTs which are shown in Fig. 19(a) and (e), a signicantly uneven distribution of the switching losses is also expected for L1 and L3. This can be seen in the fth column of Table VII for the circuit layouts L1 and L3. On the contrary, when the DUTs are placed according to L2, a uniform loss distribution is obtained, but the total losses for both devices are the highest among all the layout cases. In Fig. 20, it was shown that by employing a single DRp C network for the devices with different Vbr,g , the switching performance was improved signicantly. It is, therefore, anticipated that a more even distribution of the switching losses caused in devices Nos. 50 and 21 should be found. This was also found experimentally and the results are shown in Table VIII. The most uniform loss distribution among the parallel-connected SiC JFETs regardless of the circuit layout can be observed in the fth column of this table. Moreover, the total switching losses for both DUTs, which are shown in the last column of the table, have not only been signicantly reduced, but they are also approximately equal for all three circuit-layout cases. From the presented results so far, it can be concluded that for each individual case presented in Tables VVIII, the total switching losses caused in both parallel-connected SiC JFETs are minimized when the DUTs are placed in a symmetrical way (L3). It is believed that the main reason for this is the approximately equal parasitic inductances between the SiC JFETs and the SiC Schottky diode, which leads to an improved switching performance of the DUTs as shown in Figs. 17(e), (f), 12(e), (f), 15(e), (f), and 16(e), (f). The numerical value of the total switching losses when the DUTs are placed according to L3 can be seen in the fourth line in the last column of the tables. On the contrary, the distribution of the switching losses per device is uniform only in the case of devices with different Vbr,g , and when they are driven by a single DRp C gate driver. In such case, the temperature distribution among the parallelconnected DUTs will be more uniform compared to the other three gate-driver cases. It seems that employing a gate driver with a single DRp C network is a solution not only to the larger spread between the Vbr,g and the pinch-off voltage, but also to achieve a more uniform distribution of the switching losses among the DUTs. For instance, in a module which is populated with several SiC JFET chips and where the chips are not sorted with respect to their Vbr,g , using a single DRp C network can drive the JFETs in a more efcient way compared to a double DRp C gate driver. It must be also noted that very low switching losses and a uniform loss distribution are obtained in the case

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of DUTs having different Vbr,g and driven by a single DRp C network regardless of the placement of the JFETs in the circuit layout. V. DISCUSSION Considering the present state of development of SiC JFETs, parallel connection is the only way to reach high current ratings. For the highest current ratings, this might be true in two or three decades. From the previous sections, however, it is clear that several issues must be dealt with in order to be successful. First of all, the spread in on-state resistance might affect the steady-state current sharing among the parallel-connected devices, and hence, an uneven temperature distribution might result. In Fig. 7, it was shown that the spread in on-state resistance among four different devices can be signicant (e.g., device Nos. 1 and 4). Regardless of the spread in on-state resistance, it was found that the temperature coefcient of the on-state resistance is approximately the same (but not identical) for all four devices. Sorting the devices with respect to the on-state resistance is a simple, yet effective, way to overcome the spread in on-state losses. Small differences in on-state resistance are not problematic because of the positive temperature coefcient. The variations in static transfer characteristics of the SiC JFETs might also affect the effectiveness of the parallel connection. In Section II, signicant differences in static transfer characteristics in the active region were observed. The reason to these differences is differences in the transconductance. This basically affects the switching transients, since the device having the highest transconductance will take a higher current than the other ones. Moreover, a slight difference in the pinch-off voltages can be also obtained. Even though the rst device conducts a low current at a gatesource voltage of 5 V, the second one is still kept in the off state. The experimental investigation has shown that even if the two JFETs have the same Vbr,g , their switching performance is not exactly the same. Regardless of the type of the gate driver that is employed, transient current mismatches are obtained due to the parasitic inductances in the circuit layout (see Figs. 17 and 18). On the other hand, any difference in Vbr,g (and consequently in the pinch-off voltage) has a signicant impact on the switching performance and on the distribution of the switching losses among the devices. In particular, in a case when Vbr,g differed approximately 9 V and a double DRp C network was employed, the spread in the transient current is signicant even if the devices are symmetrically placed (see Fig. 19). Even though the difference in the currents is large when the DUTs are turned ON, after a certain time, the steady state is reached [i.e., Fig. 19(a) and (b)]. If very high switching frequencies are used, it might have destructive results for the device carrying the higher current. In the case of the single DRp C network, the switching performance of devices with different Vbr,g was improved regardless of the circuit layout (see Fig. 20). It seems that, by employing a gate driver with a single DRp C network, very substantial mismatches in the transient current can be reduced, while at the same time an approximately uniform switching loss distribution among the devices is obtained (see Table VIII).

This might also be the solution to efciently drive a module populated with several normally ON SiC JFETs in the future. In this case, the sorting of the chips with respect to their Vbr,g might not be necessary since a satisfactory switching performance can be obtained even if substantial device mismatches are present. From Tables VVIII, it is clear that the total switching losses for the devices are the lowest when they are symmetrically placed in the circuit layout. Nevertheless, a closer investigation reveals that the loss distribution among the devices is uniform only in Table VIII, which corresponds to the case of devices having different Vbr,g and driven by a single DRp C gate driver. Considering the other three cases (see Tables VVII) at a rst sight, it may seem that the nonuniformly distributed switching losses may not be a considerable problem, because the sum of the losses for the corresponding cases is not inuenced. A closer investigation, however, reveals that if the loss distribution among the devices is excessively nonuniform, the device that is exposed to the highest losses might get destroyed. Moreover, with the switching speeds considered in this paper, it should be mentioned that it only makes sense to look on either the switching losses per device or the total switching losses and not on the switching losses during the turn-on and turn-off transients separately. Elevated temperatures also contribute in a negative way as shown in Section II. Even though the pinch-off voltage is almost independent on the temperature, Vbr,g is increasing (or decreasing in the absolute value) when the temperature is increasing for the LCJFET design, and thus, the operating gatevoltage region is reduced. To solve this, a special gate-driver design which supplies a narrow voltage range is again required. This problem might become more serious when both Vbr,g and its variations with the temperature differ between the parallelconnected devices. However, in the case of the vertical trench JFET design, Vbr,g is almost temperature independent, and thus, the safety margin between Vbr,g and the pinch-off voltage is also maintained at higher temperatures. The ideal solution would be a sorting of the parallel-connected devices with respect to Vbr,g and the pinch-off voltages. However, as it has been shown from the experimental results, even this will not provide a perfect solution. When it comes to the experiments, even if the devices have exactly the same Vbr,g , they might either have different on-state resistances or different static transfer characteristics. Furthermore, the circuit layout might also affect the switching performance of the perfectly matched devices as it has been already shown in Section III. Hence, the current sharing is not equal among the devices, and consequently, the distribution of switching losses is not uniform. This has been experimentally shown in Sections III and IV. VI. CONCLUSION This paper deals with the challenges regarding parallel connection of normally ON SiC JFETs. The pinch-off voltage and the reverse breakdown voltage of the gate both count as the most crucial parameters affecting the performance of the parallelconnected JFETs. The margin between these two parameters

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might vary among the different devices and if the parameter spread is sufciently large, it may, therefore, be impossible to keep one of the components in the off-state without forcing the other component into reverse breakdown of the gate. However, if individual gate circuits are used, this problem can be solved. A spread in the on-state resistances of the SiC JFETs has been observed, but it does not appear to have any signicant adverse effects on the effectiveness of the parallel connection. Variations, in the static transfer characteristics of the devices, have also been observed together with the associated differences in the switching transients. It was found experimentally that there are substantial mismatches in the switching transients when the parallel-connected devices have a signicant difference in the reverse breakdown voltage of the gates and a gate driver with a double DRp C network is employed (see Fig. 19). This results in an uneven distribution of the switching losses among the devices as shown in Table VII. On the contrary, it has been shown that when a gate driver with a single DRp C network is employed, the switching performance of the devices having different reverse breakdown voltages of the gates has been improved and an adequately uniform distribution of the switching losses among the DUTs is obtained (see Table VIII) regardless of the placement of the JFETs. Slightly different switching performance has also been observed for the SiC JFETs having the same reverse breakdown voltage of the gates. The spread in the switching losses distribution among the parallel-connected devices may be signicant even if the DUTs are symmetrically placed in the circuit layout (see Tables V and VI). Nevertheless, the total losses for both DUTs are the lowest for the symmetrical placement. Finally, it is shown that in order to achieve a similar switching performance of the parallel-connected SiC JFETs is not a trivial issue, but there are four device parameters and the circuit layout itself which are involved. REFERENCES
[1] K. Acharya, S. K. Mazumder, and P. Jedraszczak, Efcient, hightemperature bidirectional DC/DC converter for plug-in-hybrid electric vehicle (PHEV) using SiC devices, in Proc. 24th Annu. IEEE Appl. Power Electron. Conf. Expo., Feb. 1519, 2009, pp. 642648. [2] H. Zhang, L. M. Tolbert, and B. Ozpineci, Impact of SiC devices on hybrid electric and plug-in hybrid electric vehicles, in Proc. IEEE Ind. Appl. Soc. Annu. Meet., Oct. 59, 2008, pp. 15. [3] B. Wrzecionko, J. Biela, and J. W. Kolar, SiC power semiconductors in HEVs: Inuence of junction temperature on power density, chip utilization and efciency, in Proc. 35th Annu. Conf. IEEE Ind. Electron., Nov. 35, 2009, pp. 38343841. [4] O. Stalter, D. Kranzer, S. Rogalla, and B. Burger, Advanced solar power electronics, in Proc. 22nd Int. Symp. Power Semicond. Devices ICs, Jun. 610, 2010, pp. 310. [5] R. L. Kelley, M. Mazzola, S. Morrison, W. Draper, I. Sankin, D. Sheridan, and J. Casady, Power factor correction using an enhancement-mode SiC JFET, in Proc. IEEE Power Electron. Spec. Conf., Jun. 1519, 2008, pp. 47664769. [6] P.-O. Jeannin, D. Frey, J.-C. Podvin, J.-P. Ferrieux, J. Barbaroux, J.-L. Schanen, and B. Rivet, 1 MHz power factor correction boost converter with SiC Schottky diode, in Proc. 39th Ind. Appl. Soc. Annu. Meet. Ind. Appl. Conf., Oct. 37, 2004, vol. 2, pp. 12671272. [7] D. Aggeler, J. Biela, and J. W. Kolar, Controllable du/dt behaviour of the SiC MOSFET/JFET cascode an alternative hard commutated switch for telecom applications, in Proc. 25th Annu. IEEE Appl. Power Electron. Conf. Expo., 2010, pp. 15841590.

[8] D. Peftitsis, G. Tolstoy, A. Antonopoulos, J. Rabkowski, J.-K. Lim, M. Bakowski, L. Angquist, and H.-P. Nee, High-power modular multilevel converters with SiC JFETs, IEEE Trans. Power Electron., vol. 27, no. 1, pp. 2836, Jan. 2012. [9] L. Rixin, F. Wang, P. Ning, D. Zhang, D. Jiang, R. Burgos, D. Boroyevich, K. J. Karimi, and V. D. Immanuel, A high-power-density converter, IEEE Ind. Electron. Mag., vol. 4, no. 4, pp. 412, Dec. 2010. [10] L. Rixin, F. Wang, R. Burgos, D. Boroyevich, D. Zhang, and P. Ning, A shoot-through protection scheme for converters built with SiC JFETs, IEEE Trans. Ind. Appl., vol. 46, no. 6, pp. 24952500, Nov.Dec. 2010. [11] T. Friedli, S. D. Round, D. Hassler, and J. W. Kolar, Design and performance of a 200-kHz All-SiC JFET current DC-link back-to-back converter, IEEE Trans. Ind. Appl., vol. 45, no. 5, pp. 18681878, Sep./Oct. 2009. [12] J. Biela, M. Schweizer, S. Wafer, and J. W. Kolar, SiC versus Si Evaluation of potentials for performance improvement of inverter and DCDC converter systems by SiC power semiconductors, IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 28722882, Jul. 2011. [13] D. Domes, W. Hofmann, and J. Lutz, A rst loss evaluation using a vertical SiC-JFET and a conventional Si-IGBT in the bidirectional matrix converter switch topology, in Proc. Eur. Conf. Power Electron. Appl., 2005, pp. 110. [14] M. Bakowski, Status and prospects of SiC power devices, IEEJ Trans. Ind. Appl., vol. 126, no. 4, pp. 391399, 2006. [15] P. Friedrichs, Silicon carbide power semiconductorsNew opportunities for high efciency, in Proc. 3rd IEEE Conf. Ind. Electron. Appl., 2008, pp. 17701774. [16] P. Friedrichs, Unipolar SiC devices: Latest achievements on the way to a new generation of high voltage power semiconductors, in Proc. Power Electron. Motion Control Conf. IPEMC 2006, Aug. 1416, 2006. [17] G. Tolstoy, D. Peftitsis, J. Rabkowski, and H.-P. Nee, Performance tests of 4,14,1 mm2 SiC JFET for DC/DC boost converter application, in Proc. Eur. Conf. Silicon Carbide Related Mater. (ECSCRM), Oslo, Norway, Aug. 29Sep. 2, 2010. [18] H. Zhang, L. M. Tolbert, J. H. Han, M. S. Chinthavali, and F. Barlow, 18 kW three phase inverter system using hermetically sealed SiC phaseleg power modules, in Proc. 25th Annu. IEEE Appl. Power Electron. Conf. Expo. (APEC), 2010, pp. 11081112. [19] F. Xu, D. Jiang, J. Wang, F. Wang, L. M. Tolbert, T. J. Han, J. Nagashima, and S. J. Kim, High temperature packaging of 50 kW three-phase SiC power module, in Proc. IEEE 8th Int. Conf. Power Electron. ECCE Asia (ICPE & ECCE), 2011, pp. 24272433. [20] P. Ning, T. G. Lei, F. (Fred) Wang, G.-Q. Lu, K. D. T. Ngo, and K. Rajashekara, A novel high-temperature planar package for SiC multichip phase-leg power module, IEEE Trans. Power Electron., vol. 25, no. 8, pp. 20592067, Aug. 2010. [21] D. Urciuoli, R. Green, A. Lelis, and D. Ibitayo, Performance of a dual, 1200 V, 400 A, silicon-carbide power MOSFET module, in Proc. IEEE Energy Convers. Congr. Expo., Sep. 1216, 2010, pp. 33033310. [22] E. Platania, Z. Chen, F. Chimento, A. E. Grekov, R. Fu, L. Lu, A. Raciti, J. L. Hudgins, H. A. Mantooth, D. C. Sheridan, J. Casady, and E. Santi, A physics-based model for a SiC JFET accounting for electric-elddependent mobility, IEEE Trans. Ind. Appl., vol. 47, no. 1, pp. 199211, Jan./Feb. 2011. [23] V. Veliadis, T. McNutt, M. Snook, H. Hearne, P. Potyraj, and C. Scozzie, A 1680-V (at 1 mA/cm2 ) 54-A (at 780 W/cm2 ) normally ON 4 H-SiC JFET with 0.143-cm2 active area, IEEE Electron Device Lett., vol. 29, no. 10, pp. 11321134, Oct. 2008. [24] G. Kelner, M. S. Shur, S. Binari, K. J. Sleger, and H-S Kong, Hightransconductance p-Sic buried-gate JFETs, IEEE Trans. Electron Devices, vol. 36, no. 6, pp. 10451049, Jun. 1989. [25] I. Josifovic, J. Popovic-Gerber, and J. A. Ferreira, SiC JFET switching behavior in a drive inverter under inuence of circuit parasitics, in Proc. IEEE 8th Int. Conf. Power Electron. ECCE Asia (ICPE & ECCE), May 30Jun. 3, 2011, pp. 10871094. [26] F. Xu, D. Jiang, J. Wang, F. Wang, L. M. Tolbert, T. J. Han, and S. J. Kim, Characterization of a high temperature multichip SiC JFET-based module, in Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Sep. 1722, 2011, pp. 24052412. [27] R. Wang, Z. Chen, D. Boroyevich, J. Li, Y. Yiying, and R. Kaushik, A novel hybrid packaging structure for high-temperature SiC power modules, in Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Sep. 1722, 2011, pp. 333338. [28] I. Josifovic, J. Popovic-Gerber, and J. A. Ferreira, Power sandwich industrial drive with SiC JFETs, in Proc. 14th Eur. Conf. Power Electron. Appl. (EPE 2011), Aug. 30Sep. 1, 2011, pp. 110.

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[29] M. Chinthavali, P. Ning, Y. Cui, and L. Tolbert, Investigation on the parallel operation of discrete SiC BJTs and JFETs, in Proc. Appl. Power Electron. Conf. (APEC), Mar. 610, 2011. [30] S. Round, M. Heldwein, J. Kolar, I. Hofsajer, and P. Friedrichs, A SiC JFET driver for a 5 kW, 150 kHz three-phase PWM converter, in Proc. 14th Ind. Appl. Soc. Annu. Meet. Ind. Appl. Conf., 2005, vol. 1, pp. 410 416. [31] J. Rabkowski, D. Peftitsis, and H.-P. Nee, Design steps towards a 40-kVA SiC inverter with an efciency exceeding 99.5%, in Proc. 27th Annu. IEEE Appl. Power Electron. Conf. Expo., Feb. 59, 2012, pp. 15361543.

Dimosthenis Peftitsis (S03) was born in Kavala, Greece, in 1985. He received the Diploma in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2008. Since 2008, he has been working toward the Ph.D. degree in the Electrical Energy Conversion Laboratory, KTH Royal Institute of Technology, Stockholm, Sweden. In 2008, he was involved in research on his diploma thesis at ABB Corporate Research, V aster as, Sweden, for six months. His research interests include gate- and base-driver design for SiC JFETs and bipolar junction transistors, as well as protection circuits for normally ON SiC JFETs.

Josef Lutz was born in 1954. He received the Dipl.-Phys. degree from the University of Stuttgart, Stuttgart, Germany, in 1983, and the Dr.-Ing. degree in electrical engineering from the Technical University of Ilmenau, Ilmenau, Germany, in 1999. In 1983, he was with the SEMIKRON ElektronikGmbH, Nuremberg, Germany, where he was involved in the development of gate turn-off thyristors and fast-recovery diodes. He introduced the controlled axial lifetime diode and is the holder of several patents in the eld of fast-recovery diodes. Since August 2001, he has been a Professor of power electronics and electromagnetic compatibility with the Chemnitz University of Technology, Chemnitz, Germany. Dr. Lutz is a Member of the Board of Directors of the ZfM, a consultatory member of the Board of Directors of the Power Conversion Intelligent Motion, and a Member of the International Steering Committee of the European Power Electronics and Drives Association, the technical program committee of the International Conference on Integrated Power Electronics Systems, and the program committee of the International Seminar on Power Semiconductors. He was awarded the degree of Honorable Professor by the North Caucasus State Technical University, Stavropol, Russia, in 2005.

Roman Baburske was born in Werdau, Germany, in 1980. He received the Dipl.-Ing. degree in electrical engineering and the Ph.D. degree in electrical engineering and information technology from Chemnitz University of Technology, Chemnitz, Germany, in 2006 and 2011, respectively. From 2006 to 2011, he was with the Chair of Power Electronics and Electromagnetic Compatibility, Chemnitz University of Technology, where he worked on ruggedness analyses of high-power semiconductor devices. The main focus of his research was on the reverse-recovery process of bipolar power diodes. Since 2011, he is with Inneon Technologies AG, Neubiberg, Germany, where he is currently working on new technologies for high-voltage diodes and IGBTs.

Georg Tolstoy (S09) was born 1981 in G avle, Sweden. He received the M.Sc. degree in engineering physics from Uppsala University, Uppsala, Sweden, in 2008. Since 2008, he has been working toward the Ph.D. degree in power electronics at the KTH Royal Institute of Technology, Stockholm, Sweden. He was previously a Project Worker at ABB Corporate Research Center, V aster as, Sweden, and a Software Engineer at SAAB Avitronics, Kista, Sweden.

Jacek Rabkowski (M10) received the M.Sc. and Ph.D. degrees in electrical engineering from the Warsaw University of Technology, Warsaw, Poland, in 2000 and 2005, respectively. In 2005, he joined the Institute of Control and Industrial Electronics, Warsaw University of Technology, as an Assistant Professor. Since 2010, he has been with Electrical Machines and Power Electronics Laboratory, KTH Royal Institute of Technology, Stockholm, Sweden, as a Guest Researcher. His research interests include novel topologies of power converters, pulsewidth modulation techniques, drive units, and converters with SiC devices.

Hans-Peter Nee (S91M96SM04) was born in V aster as, Sweden, in 1963. He received the M.Sc., Licentiate, and Ph.D. degrees in electrical engineering from the KTH Royal Institute of Technology (KTH), Stockholm, Sweden, in 1987, 1992, and 1996, respectively. In 1999, he joined as a Professor of power electronics at KTH, where he currently serves as the Head of the Electrical Energy Conversion Laboratory. His current research interests include power electronic converters, semiconductor components, and control aspects of utility applications, such as exible ac transmission systems and HVDC transmission, and variable-speed drives. Dr. Nee has received several awards for his research. He is currently an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS, and was on the board of the IEEE Sweden Section for several years, serving as its Chairman during 20022003. He is a Member of European Power Electronics and Drives Association, involved with the Executive Council and the International Scientic Committee.