Monolithic D/A Converters

Basic

DAC Specs Basic MOS DAC Implementations Performance Limits in DACs Improved DAC Implementations

PRG, DACs, Slide 1

PRG, DACs slide2

Integral vs Differential Non-Linearity

INL = 1lsb DNL = small INL = 1lsb DNL = 2lsb

Analog output

Analog output

. .
1lsb

1lsb

Digital input
PRG, DACs, Slide 3

Digital input

High Speed ADC/DAC Techniques

Traditional Approach
Bipolar Technology Current-switched DAC LWT Thin-lm resistors for >10 bits

Problems:
Not LSI Compatible No self-cal capability

Key Issues for CMOS LSI High-Integration ICs:

How do we integrate high-resolution DACs in CMOS? How do we calibrate or trim linearity for >10 bits?

Approaches:
Current-Switched DACs Resistor-String DACS Charge-Redistribution DACs Algorithmic DACs

PRG, DACs, Slide 4

Current-Switched DACs in CMOS using Ratioed Devices

Advantages: Can be very fast Small for <9-10 bits Disadvantages: Depends on VT, device mismatch

Id1

Id2
I I D
= W L W L + V

2V GS

T V T

PRG, DACs, Slide 5

Current-Switched DACs

Advantages
Inherent High Speed Easy to Generate Nonlinear Xfer Easy to Segment Amenable to Self-Cal

Disadvantages
INL Depends on Transistor Matching Critically dependent on Rout of device

PRG, DACs, Slide 6

Resistor-String DACs

PRG, DACs, Slide 7

X-Y Decoding in R-String DACs

Poly lines

Metal pickup lines Vref

Diffused Resistors

Switch tree

Analog Vout

Problems: Turning corners Process gradients

Ref: Hoff, Huggins et al, JSC Feb 79, Pellgrom, ISSCC90

PRG, DACs, Slide 8

Resistor-string DACs
Advantages
Inherently Monotonic Small area for <8 bits

Disadvantages
Large area for >8bits Susceptible to Process Gradients Susceptible to Contact Resistance Susceptible to Voltage Coefcient

Examples
Intel 8021, 80960

PRG, DACs, Slide 9

Resistors vs. Capacitors for Precision DACs

Representative Component Nonidealities, Typical Technologies Component type N+PolyN+Poly cap, 20u P-Diffused R, 3uX50u N+Poly Resistor, 3x50u Thin lm resistor, 3X50 Matching range, 1 sigma 0.1%-0.3% TC, typical 40ppm/deg C VC, typical 50ppm/V

0.2%-0.5% 0.2-0.5% 0.1-0.3%

1500ppm/ C 300ppm/ C 100ppm/ C

100ppm/V <50ppm/V 0

PRG, DACs, Slide 10

Polysilicon Capacitor and Switch Structure

PRG, DACs, Slide 10.1

Charge-redistribution ADC
1. Sampling Mode

PRG, DACs, Slide 11

Charge-Redistribution ADC
2. Hold Mode

PRG, DACs, Slide 12

Charge-Redistribution ADC
3. Bit trials

PRG, DACs, Slide 13

Charge-redistribution ADC
4. Final State

Key Points:
Charge is Redistributed Operation is parasitic insensitive Linearity = f(cap ratios) Can be calibrated for absolute linearity
ref: McCreary JSC 12/75 PRG, DACs, Slide 14

Conventional Charge-Redistribution DACs

Advantages:
Inherent Sample/Hold MOS Compatible Can be made inherently monotonic Potential for very low power

Disadvantages
Trim or self-cal required for >10bit linearity Requires cap in process

DAC Summary
Current-switched widely used for high-speed video, low-res Cap arrays often used in precision data acquisition or telecom apps R-string used mostly in capacitorless technologies

PRG, DACs, Slide 15

Performance Limits in Monolithic DACs

Fundamental limits: Noise
Capacitive DACs- kT/C Current switched DACs- Thermal R-string DACS- thermal

Settling Time
gm/C- varies with type, speed of technology

Linearity
Component linearity (R,C)

Practical Limits Noise

Digital Noise Coupling

Settling Time
Various, including Glitch behavior

Linearity
Component matching
PRG, DACs, Slide 16

Performance Limits in Monolithic DACs

Linearity Settling Time

Modications for Improved Performance

Segmented DACs Self-Calibrated DACs Dynamic Element Matching Current Replica DACs

PRG, DACs, Slide 17

The Mismatch Phenomena Probability

R R
=

2 1

R R

For typical technolgies and geometries, 1-sigma lies in the range 0.1% to 2-5% Key Question: What determines sigma?

refs: McCreary JSC 12/81(caps), Shyu, JSC12/84(caps, devices),Lakshmikumar , JSC, 12/86(devices) PRG, DACs, Slide 18

Mismatch Effects in Binary Weighted DACs

PRG, DACs, Slide 19

Design Approaches for Improving Linearity

Laser

Trimming Discrete trim/Poly fuse Segmentation Self-Calibration Dynamic Element matching

PRG, DACs, Slide 20

How do we Solve this in a DAC?

Improvement of DAC DNL by Segmentation Standard Approach: Segmentation

Iout

I1

I2

I3

I/2

I/4

I/8

Equal Segments

Iout
I1+I2+I3 I1+I2 I1

I2 too big

KEY POINT: MATCHING RQMT FOR GIVEN DNL IS REDUCED DRAMATICALLY

PRG, DACs, Slide 21

Improved DNL Through Segmentation plus Interpolation Improved Approach:

Segmentation Plus Interpolation Iout

N/8 Divider

I1

I2

I3

I4

Equal Segments I1+I2+I3+I4 I1+I2+I3 I1+I2 I1 I3 TOO BIG

Key Point: DAC inherently provide very good DNL INL Not Affected

ref: Shoeff, ISSCC79

PRG, DACs slide22

Symp VLSI paper

PRG, DACs, Slide 23

Segmented DACs
Key Concept:
Improve DNL by building DAC Xfer characteristic out of additive equal segments rather than binary weighted elements

Advantages:
Dramatically improves DNL With proper decoding can improve glitch energy

Disadvantages:
More complex switching Does nothing for INL

Key Design Issues:

Number of segments Layout, segment turnon sequence
refs: Kumazawa, VLSICkts, 1990; Nakamura, VLSIckts, 1990 PRG, DACs, Slide 24

Resistor/Capacitor Interpolation

PRG, DACs, Slide 25

refs: Fotouhi, JSC12/79;Tan, ISSCC83

Capacitor-Resistor Interpolation

Ref: Agazzi, JSC, 4/89 PRG, DACs, Slide 26

Self-Calibration of Q-R DACs

PRG, DACs, Slide 27

Self-Cal of Q-R DACS, contd

refs: Lee, Hodges, JSC, 12/84, Miller, ISSCC90, Croteau, ED, Sept86 PRG, DACs, Slide 28

Self-Calibrated DACs
Key Concept:
Improve DNL and INL by using on-chip intelligence to measure and correct DAC non-linearity

Advantages:
Dramatically improves DNL, DNL Can compensate for environmental changes .Allows high-performance DAC/ADC with standard technology

Disadvantages:
Much more complex analog and digital circuitry Self-cal can be a burden to the user .

PRG, DACs slide29

Example Self-Cal Application

Single-Chip CMOS Programmable Data Acquisition System
Uses Digital CMOS to allow higher level of integration of DAS function in a reasonable size Uses self-cal to allow 13bit ADC in std CMOS Address application diversity throught programmability Uses lateral bipolar transistors and poly fuse trimming for precision band gap.

PRG, DACs, Slide 30

Current-Replica Self-Calibration

To Calibrate Segment: Force Iseg=Iref

Problem:
Charge Injection error

Solutions:
Big Cs Small switch Slow turnoff Small correction current
ref: Groenveld, ISSCC89 PRG, DACs, Slide 31

Algorithmic ADC Technique

Potential Advantages
Hardware simplicity Single parameter calibration Inherently programmable gain function Inherent Differential Implementation

Potential Disadvanatages
Sensitivity to Loop Offsets Speed limitations in Op Amp Settling

Critical Design Issues

Loop Offset Cancellation Loop Gain Calibration Op Amp Settling Time Optimization
refs: Ohara JSC 12/87, Webb ISSCC80, Li JSC12/84, Jusuf, CICC92 PRG, DACs, Slide 32