International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN 6480(Print),

, ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

ENGINEERING AND TECHNOLOGY (IJARET)

ISSN 0976 - 6480 (Print) ISSN 0976 - 6499 (Online) Volume 4, Issue 5, July August 2013, pp. 17-23 IAEME: www.iaeme.com/ijaret.asp Journal Impact Factor (2013): 5.8376 (Calculated by GISI) www.jifactor.com

IJARET
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INTEGRATED BRIDGELESS PWM BASED POWER CONVERTERS

L.Raguraman 1 and P.Sabarish2
2

Assistant Professor, CHANDY College of Engineering, Thoothukudi. Assistant Professor, PSN College of Engineering and Technology, Tirunelveli.

ABSTRACT In this study a new integrated bridgeless PWM based power converter for power factor correction. The proposed converter integrates the bridgeless boost rectifier with the asymmetrical pulse-width modulation half-bridge dcdc converter. The proposed converter provides an isolated dc output voltage without using any full-bridge diode rectifier. Conduction losses are lowered by eliminating the full-bridge diode rectifier. Zero-voltage switching of the power switches reduces the switching power losses. The proposed converter gives a high efficiency, high power factor, and low cost. The effectiveness of the proposed converter is verified on a 250 W (40V/1 A) experimental prototype. The proposed converter achieves a high efficiency of 93.0% and an almost unity power factor for 250 W output power at 90 Vrm s line voltage. Index Terms - Power converter, asymmetrical single stage, zero- voltage switching (ZVS). I. INTRODUCTION pulse width modulation, bridgeless, half bridge,

The advances in power factor correction (PFC) technology have enabled the development of single-phase acdc converters [1][10] in the recent pieces of literature. The previous single-stage PFC acdc converters [8][11] need the full-bridge diode rectifier. The full-bridge diode rectifier increases the conduction losses and decreases the power efficiency. Especially, at low line voltage, the full-bridge diode rectifier causes high conduction losses, resulting in additional thermal management. These problems can be overcome by eliminating the full-bridge diode rectifier. Up to now, however, any bridgeless single-stage PFC acdc converter has not been re- ported for singlestage PFC acdc converters. The discontinuous conduction mode (DCM) single-stage PFC acdc converters are widely used for their simple and efficient structures [4][8]. Generally, two power stages of the PFC circuit and dcdc converter are simplified by sharing a common switch [4][7] or a pair of switches [8] [11]. Most single-stage PFC acdc converters use single-switch dcdc converter topologies like fly 17

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

back [4], [5] or forward Converters [6], [7]. However, the single-stage single- switch acdc converters have low power efficiency because of the hard-switching operation. Single-stage soft-switching ac dc converters [8][11] have been studied to improve the power efficiency. Single-stage soft-switching acdc converters based on the half-bridge converter provide low voltage stresses and zero-voltage switching (ZVS) operation of the power switches [8][10]. The active-clamping techniques [11] have been applied to the single-stage PFC acdc converters. However, the majority of these development efforts have been focused on only reducing switching power losses. II. CIRCUIT DESCRIPTION Fig. 1 shows the circuit diagram of the proposed converter. The bridgeless boost rectifier consists of the boost inductor Lb, dc-link capacitor Cd , and switching devices D1 , D2 , S1,and S2 . D1 and D2 are slow-recovery diodes. S1and S2 are metal oxidesemiconductor field-effect transistors (MOSFETs). DS1 and DS2 are body diodes of S1 and S2 , respectively. CS1 and CS2 (CS=CS= Cs2 ) are the output capacitors of S1 and S2 , respectively. The APWM half-bridge dcdc converter consists of Cd, ,S1, S2 , blocking capacitor Cb , transformer T , output diodes D01 and Do2 , output filter inductor Lo , and output filter capacitor Co .Ro is the output resistor. By sharing Cd ,S1and S2 ,the proposed converter integrates the bridgeless boost rectifier with the APWM halfbridge dcdc converter. .

Fig. 1 Circuit diagram of the proposed converter III. CIRCUIT OPERATION Fig. 2 shows the operation modes of the proposed converter during one switching period Ts .Fig. 2(a) shows the operation modes during Ts for a positive half line period. S1 is controlled with the duty ratio D. The conduction times of S1and S2 are DTs and (1 D)Ts , respectively. When S1is turned ON, the input current ii flows through Lb , D1 , and S1 . When S1 is turned OFF, the input current ii flows through Lb , D1 , Cd , S2 , and DS2 . Fig. 2(b) shows the operation modes during Ts for a negative half line period. S2 is controlled with the duty ratio D. When S2 is turned ON, the input current ii flows through S2 ,D2 , and Lb. When S2 is turned OFF, the input current ii flows through S1 , DS1 , Cd , D2 , and Lb .

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

Fig 2 operation of mode1 Mode 1 [t0, t1]: At t = t0, S1 is turned ON. ZVS of S1 is achieved when S1 is turned ON. The input current ii flows through Lb, D1, and S1. The boost inductor Lb stores energy from the line voltage vi. The boost inductor current iLb increases as ilb(t) = vi/Lb(t-to) . (1)

At t =t1, S1 is turned OFF. The primary current ip charges CS1 and discharges CS2. The voltage VS2 across S2 decreases from Vd to zero, while the voltage VS1 across S1 increases from zero to Vd. The magnetizing current iLm and boost inductor current iLb are considered constant because the time interval during this mode is negligible compared to Ts. Mode 2 [t2, t3]: At t = t2, S2 is turned ON. ZVS of S2 is achieved when S2 is turned ON. The input current ii flows through Lb, D1, Cd, S2, and DS2. The energy stored in the boost inductor Lb is released to the dc-link capacitor Cd. The boost inductor current iLb decreases as ilb(t) = ilb(t2)-vi/Lb(t-t2) . (2)

Fig 3 operation of mode 2 Mode 3[t4, t5]: At t =t4, S2 is turned OFF. As the primary current ip charges CS2 and discharges CS1. The voltage VS1 across S1 decreases from Vd to zero, while the voltage VS2 across S2 increases from zero to Vd. As long as the switch S1 is turned ON before the Magnetizing current iLm changes is direction; ZVS of S1 can be assured. At the secondary side, the output filter inductor current iLo freewheels through both output diodes Do1 and Do2.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

Fig 4 Operation of mode 3

IV. CIRCUIT ANALYSIS A. Power Factor The boost inductor Lb operates at DCM. Then, the peak boost inductor current iLb, peak follows the line voltage vi with a fixed duty ratio to supply the output power for a constant output voltage. Suppose that the converter is lossless and the duty ratio is fixed, the boost inductor Lb should be determined as Lb < Vin2DTs/2Pomax. (3)

It is defined as the ratio of the real to apparent power.Apparent power is defined as the and reactive power.

square

root

of

the

sum

of

the

real

B. Efficiency It is defined as ratio of the output real power to the reactive power. A. DC Characteristics From the volt-second balance relation on the magnetizing inductor Lm during Ts, the voltage Vb across the capacitor Cb is expressed as Vb = DVd. (4) From the volt-second balance relation on the output filter inductor Lo during Ts, the following relation between the output voltage Vo and the dc-link capacitor voltage Vd is expressed: Vo/ Vd =2ND(1 - D). (5)

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

V. EXPERIMENTAL RESULTS The proposed converter in Fig. 1 has been built to verify its performance with the following parameters: 1) line voltage vi :90150 Vrms ; 2) output voltage Vo:40 V; 3) output power Po : 250 W; 4) switching frequency fs: 50 kHz; 5) line filter inductor Lf : 1 mH; 6) line filter capacitor Cf : 2.2 F; 7) boost inductor Lb: 50 H; 8) magnetizing inductor Lm: 150 H; 9) blocking capacitor Cb: 1 F; 10) dc-link capacitor Cd : 220 F; 11) output filter inductor Lo: 50 H; 12) output filter capacitor Co : 2200 F; 13) transformer turns ratio N: 0.4; 14) switch output capacitor CS : 500 pF.

Fig. 5 Experimental results: boost inductor current iLb : 15 A/division; volt- age VD 1 across the diode D 1 : 100 V/division; output filter inductor current iLo : 5 A/division, 4 s/division In this integrated bridgeless a new soft switched boost converter has been stimulated on the voltage and current.

Fig 6 Source voltage and current 21

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

Fig 7 Output voltage and current

VI. CONCLUSION As a new single-stage PFC scheme, this paper has proposed an integrated bridgeless PWM based power converter. The proposed converter gives a high efficiency by reducing the conduction losses and switching losses. The proposed converter has the following features for the bridgeless single-stage PFC acdc converters: 1) Low switching losses by the ZVS operation of power switches. 2) Simple control method for PFC and output voltage regulation. 3) Low conduction losses by essentially eliminating the full bridge diode rectifier. 4) Reduced component counts by integrating two power conversion stages. The performance of the proposed converter has been evaluated by the experimental results based on a 250W (40V/1 A) converter prototype. The proposed converter achieves a high efficiency of 93.0% and an almost unity power factor at 90 Vrms line voltage. REFERENCES D. L. OSullivan, M. G. Egan, and M. J.Willers, A family of single-stage resonant AC/DC converters with PFC, IEEE Trans. Power Electron.,vol. 24, no. 2, pp. 398408, Feb. 2009. [2] M. S. Agamy and P. K. Jain, Performance comparison of single-stage three-level resonant AC/DC converter topologies, IEEE Trans. Power Electron., vol. 24, no. 4, pp. 10231031, Apr. 2009. [3] Z. Jun, D. D. C. Lu, and S. Ting, Fly back-based single-stage power factor-correction scheme with time-multiplexing control, IEEE Trans.Power Electron., vol. 57, no. 3, pp. 10411049, Sep. 2010. [4] L. Shiguo, Q. Weihong, W. Wenkai, and I. Batarseh, Flyboost powerfactor correction cell and a new family of single-stage AC/DC converters,IEEE Trans. Power Electron., vol. 20, no. 1, pp. 2534, Jan. 2005. [5] D. D. C. Lu, H. H. C. Iu, and V. Pjevalica, Single-stage AC/DC boostforwardconverter with high power and regulated bus and output voltages,IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 21282132, Jun. 2009. 22 [1]

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 5, July August (2013), IAEME

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