P2-3 Digitally controlled phase locked loop with tracking analog-to-digital converter

Sooho Cha, Chunseok Jeong, Changsik Yoo

Dept. of Electronics and Computer Engineering, Hanyang University, Seoul, Korea deitie@gmail.com, chunseok.jeong@hynix.com, csyoo@hanyang.ac.kr Abstract - A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-todigital converter the key building blocks of digital PLL (DPLL), there is no need for the trade-off between jitter, power consumption and silicon area. The DCPLL was implemented in a 0.18m CMOS process and the active area is 0.35 mm2. The DCPLL consumes 59mW during the normal operation and 984W during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps rms jitter.

Joongsik Kih
Hynix Semiconductor Inc., Ichon, Korea joongsik.kih@hynix.com

analog control signal is generated by a digital-to-analog converter (DAC) embedded in a tracking ADC loop. The locking information is stored as the digital input of the DAC and thus the DCPLL can be powered down during the standby state. The tracking ADC has 10-bit resolution to provide the sufficient locking accuracy and jitter performance to the DCPLL. The detailed description of the DCPLL and the experimental results are given in the following sections.

I. Introduction
The phase locked loop (PLL) is widely used in digital, analog, and mixed-mode systems for various purposes such as frequency multiplication, clock synchronization, zero-delay buffering, and so on. Conventionally, the PLL is an analog circuitry where the locking information is stored as an analog signal. With the analog locking information, it is very difficult to turn off the PLL during the power-down state because the information can be lost. Therefore, the power consumption during the powerdown state can be substantial. On the other hand, if the PLL is constructed with only digital circuits such as digitally controlled oscillator (DCO), time-to-digital converter (TDC) and digital control logics as shown in Fig. 1 (digital PLL : DPLL), the DPLL can be turned off during the power-down state [1]. Additional benefit of the DPLL is its easy portability to different process technologies. The jitter and locking accuracy of the DPLL depend on the time step provided by the TDC and DCO. The smaller time steps of TDC and DCO, usually the larger power consumption and silicon area. The main requirement on the PLL of this work is powerdown capability during the standby state of the system. For that purpose, it is sufficient to store the locking information of the PLL as digital code even if the PLL contains analog circuit blocks. Therefore, the PLL of this work is not a DPLL but a digitally controlled PLL (DCPLL). Neither DCO nor TDC is employed in the DCPLL. Instead, as in conventional analog PLL (APLL), voltage controlled oscillator (VCO) is used and its
0-7803-9162-4/05/$20.00 2005 IEEE
Fig. 1. Conventional DPLL with DCO and TDC.

II. Digitally controlled phase locked loop with tracking analog-to-digital converter
As the conventional APLL [2-3], the proposed DCPLL shown in Fig. 2 employs a VCO, frequency divider, phase frequency detector (PFD), charge pump (CP), and loop filter. The difference from the conventional APLL is the tracking ADC which generates the control signal for the VCO. With this tracking ADC, the analog control signal at the loop filter output is converted to a digital code which enable the digital control of the loop.

Fig. 2. Proposed DCPLL with tracking ADC.

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The DCPLL has two feedback loops. One is the global feedback loop for the locking of the DCPLL and the other is the tracking ADC loop converting the low-pass filtered PFD/CP output to the digital code. In order for the local feedback loop, the tracking ADC loop, to have a negligible effect on the stability of the DCPLL, the bandwidth of the tracking ADC loop is designed to be much wider than that of the global feedback loop.

selected as shown in Fig. 4-(a) [5]. If the column (row) control path is faster, one less (more) row of the current cells are temporarily selected, creating large glitch. To avoid this problem, the improved decoding scheme shown in Fig. 4-(b) which has been proposed in [5] is adopted. This scheme uses different control logics for even and odd rows and limits the glitch to be less than 2LSB even with delay mismatch between column and row control signals.

A. Tracking ADC
The tracking ADC shown in Fig. 3 has 10-bit resolution for sufficient locking accuracy and jitter performance. The low-pass filtered PFD/CP output is compared with the output of the DAC and the 10-bit counter is toggled until the difference between the low-pass filter PFD/CP output and the DAC output becomes smaller than the magnitude of 1-LSB.

Decoder output

Row ... 0 1 1

Row ... 0 1 1

(a)
Decoder output

Fig. 3. Tracking analog-to-digital converter.

During the power-down mode of the DCPLL, the PFD and CP are turned off and thus the loop filter output is floated. The loop filter output can therefore deviate from its original value obtained during the normal operation. When the DCPLL wakes up from the power-down mode, the tracking ADC changes the DAC input digital code because the loop filter output and the DAC output are different. That is, the DCPLL must be re-locked before the system can begin its normal operation. In order to prevent the loop filter output from floating during the power-down mode, a switch is added between the loop filter output and the DAC output as shown in Fig. 3. This switch is turned-on during the power-down mode and the loop filter output is ensured to be the same as the DAC output.

Row ... 0 1 1

Row ... 0 1 1

Row ... 1 1 1

(b) Fig. 4. (a) Conventional decoding scheme and (b) the decoding scheme with negligible glitch [5]

C. Comparator
Even with the input offset voltage of the comparator, the DCPLL can be locked. At the completion of the locking, of course, there would be some difference between the outputs of the loop filter and DAC. However, the offset of the comparator must still be compensated. During the power-down state, the loop filter output is forced to be the same as the DAC output to prevent the loop filter output from floating and enable fast wake-up. If the locked value of the loop filter output is different from the DAC output due to the input offset of the comparator, the DCPLL should be re-locked when the system exits from the power-down state.

B. Digital-to-analog converter in tracking ADC

The glitch of the DAC in the tracking ADC loop plays a key role in determining the jitter of the DCPLL. To minimize the glitch, the 10-bit DAC is thermometer coded and built with the segmented structure: 9-bit with unit current cells and 1-bit with a binary scaled current cell [4]. The array of the current cells is configured as a four by five matrix. If some mismatch between the control signal paths for the row and column switch exists, thermometer coded DAC still exhibits large glitch when another row is
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Row ... 1 1 1

Row ... 1 1 1

Row ... 1 1 1

D. Voltage controlled oscillator

The VCO shown in Fig. 6-(a) is a fully differential ring oscillator for small sensitivity to common-mode noise. The oscillation frequency can be controlled from 350MHz to 1.3GHz as shown in Fig. 6-(b). The active VCO control voltage range is from 0.6V to 1.1V. The replica bias ensures the constant swing of the output of the VCO [7].

(a)

(b)
1

(a)
2
2000 NN SS FF

Latch Offset compensation Signal amplification Pre-charge Latch

Frequency (MHz) 1600

1200

800

(c) Fig. 5. (a) Comparator with offset-compensation circuit, (b) pre-amplifier with rail-to-rail input common-mode range and (c) its offset-compensation timing diagram.

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0 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 VCO control voltage (V)

(b)

As shown in Fig. 5-(a), the comparator is composed of the pre-amplifier and sense-amplifier type latch where the input offset is compensated [6]. Because the control voltage can vary in a wide range, the pre-amplifier of the comparator employs a rail-to-rail input stage to allow a wide input range as shown in Fig. 5-(b). The timing of the comparator is shown in Fig. 5-(c) where 1 and 2 are non-overlapped clocks. When 1 is high, the input and output nodes of the pre-amplifier are connected to the reference voltage and the offset voltages are stored on the capacitor. When 2 is high, the offset voltages are cancelled and only the input differential voltage is amplified. When Latch is LOW, the output nodes of latch are pre-charged to VDD. When Latch goes to HIGH, the latch senses the outputs of the pre-amplifier.

Fig. 6. (a) Fully differential ring oscillator type VCO and (b) its voltage-to-frequency characteristic.

III. Experimental results

The DCPLL with a tracking ADC has been implemented in a 0.18m CMOS process. A microphotograph of fabricated PLL is shown in Fig. 7. The active area of the DCPLL is 1.0mm0.35mm. Fig. 8 shows the locking behavior of the DCPLL simulated by HSPICE. The measured reference and output clocks are shown in Fig. 9. The rms jitter of the DCPLL is measured to be 16.8ps as shown in Fig. 10. With 1.8V supply voltage, the DCPLL consumes 59mW during the normal operation and 984W during the power-down state. The measured performance of the DCPLL is summarized in Table 1.
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DAC APLL Counter

Fig. 7. Microphotograph of the DCPLL

IV. Conclusions
A digitally controlled phase-locked loop (DCPLL) with tracking ADC has been fabricated in a 0.18m CMOS process. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analogto-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. The locking information is stored as the digital code and thus the DCPLL can be powered down during the standby state. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter the key building blocks of digital PLL (DPLL), there is no need for the trade-off between jitter, power consumption and silicon area. The DCPLL was implemented in a 0.18m CMOS process and occupies 0.35 mm2 of onchip area. While consuming 59mW during the normal operation at a 1.8V supply, the DCPLL shows 16.8ps rms jitter.
Fig. 8. Simulated locking behavior of the DCPLL

Fig. 9. Measured 120MHz reference and 1.2GHz output clocks

Acknowledgment
The CAD tools used in this work were supported by IDEC.

References
[1] T. Olsson et al., "A digitally controlled PLL for digital SOCs," IEEE J. Solid-State Circuits, Vol. 39, No. 5, pp. 751-760, May. 2004. [2] F. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Trans. Communications, Vol. COM-28, pp. 1849 - 1858, Nov. 1980. [3] J. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE J. Solid-State Circuits, Vol. 31, No. 11, pp. 1723-1732, Nov. 1996. [4] C. Lin et al., "A 10 bit, 500Msample/s CMOS DAC in 0.6mm2," IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 1948-1958, Dec. 1998. [5] J. Lin et al., "A PVT Tolerant 0.18MHz to 600MHz SelfCalibrated Digital PLL in 90nm CMOS Process," Dig. Tech. Papers, Int. Solid-State Circuits Conf., pp. 488-489, Feb. 2004. [6] B. Razavi et al., "Design techniques for high-speed, highresolution comparators," IEEE J. Solid-State Circuits, Vol. 27, No. 12, pp. 1916-1926, Dec. 1992. [7] S. Kim et al., A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL, IEEE J. Solid-State Circuits, Vol. 32, No. 5, pp. 691-700, May. 1997.

Fig. 10. Jitter measurement results Table 1. Performance summary of DCPLL Technology Die area Supply voltage Power Dissipation Jitter Locking range 0.18m 4-metal CMOS 1.0mm 0.35mm 1.8V 59mW : normal operation 984W : power-down state RMS : 16.8ps 250MHz ~ 1.2GHz

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