Journal of the Korean Physical Society, Vol. 59, No. 2, August 2011, pp.

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Design of a 100 V High-side n-channel LDMOS Transistor for Breakdown Voltage Enhancement
Kunsik Sung and Taeyoung Won
Department of Electrical Engineering, School of Engineering, Inha University, Incheon 402-751, Korea (Received 19 April 2011) In this paper, we discuss on the optimal design of a high-side n-channel lateral double-diused metal-oxide-semiconductor eld-eect transistor (LDMOSFET) whose breakdown voltage is over 100 V with a 0.35-m bipolar-complementary metal semiconductor- double diused metal oxide semiconductor process. The proposed nLDMOSFET was fabricated and tested in order to conrm the features of a deep N+ sinker and the gap between the drift region (DEEP N-WELL) and the center of the source. The surface was a implanted by the N-layer for a high breakdown voltage and simultaneously a low specic on-resistance. The computer simulation of the proposed high-side LDMOS exhibited a Breakdown voltage of 115 V and a specic on-resistance of as low as 2.20 mcm2 , which is consistent with the experimental results.
PACS numbers: 77.22.Jp, 81.07.Bc, 85.30.Tv, 85.30.-z Keywords: LDMOS, High-side, BCDMOS, RESURF DOI: 10.3938/jkps.59.412

I. INTRODUCTION Bipolar-Complementary metal semiconductor-Double diused metal oxide semiconductor (BCD) process is widely used in a variety of areas such as large displays (TVs and monitors), small displays (hand-held and mobile), POE (power-on-ethernet), and storage controller chips. Recently, many companies have made an eort to combine power management, logic, audio and communication functions in a single chip. Therefore, much larger logic content has been integrated into BCD technology [17]. The process involves a high-voltage DE (drainextended) CMOS, a LDMOS (lateral double-diused MOS), a BJT (bipolar junction transistor), a low-TC (temperature coecient) resistor, a 1 2 fF/m2 MIM (metal-insulator-metal) capacitor, and so on. When the n-channel LDMOS is operated in the highside mode, the source voltage can be raised above the substrate voltage because the source is connected to the load of the next stage. In order to resolve this electrical isolation problem, a NBL (n+ buried layer) is purposely inserted beneath the source region, which prevents the punch-through phenomen between the source and the substrate. The NBL, however, tends to limit the breakdown voltage (BVdss) because the high doping concentration of the NBL drives out the extension of the depletion region. In order to resolve this limitation, scientists have proposed to utilize the SOI (silicon-on-insulator) substrate for implementing the LDMOS devices for volt E-mail:

age up to 80 V. However, the SOI process has shortcomings, such as high production cost and high process temperature, which results in high power consumption. In this paper, we propose a novel high-side n-channel LDMOS eld-eect transistor with a breakdown voltage over 100 V while keeping the thermal budget for the conventional 0.35-m BCD process. The proposed nchannel LDMOSFET has a deep N+ sinker and a structure with a gap of 5.5 m between the DEEP N-WELL and the center of the source, the surface of which is implanted with an n-layer for a high breakdown voltage and simultaneously for a low specic on-resistance. In addition, the proposed process requires no additional process steps other than one mask step and ion-implantation, which allows integration with logic CMOS and all the other existing components.

II. EXPERIMENTS AND DISCUSSION In order to devise an optimized LDMOS structure, we performed a 1D/2D process and device simulations with Synopsys TSUPREM-4 and MEDICI. In this work, we made a deep N+ sinker and varied the size of the gap between the drift region (DEEP N-WELL) and the center of the source for a xed P-EPI layer with a thickness of 8.1 m and a doping concentration of 1 1015 atom/cm3 , respectively. Figure 1 presents a diagram illustrating cross-sectional views of the conventional LDMOS structure and the proposed structure with/without a deep N+ sinker under
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twon@inha.ac.kr; Fax: + 82-32-862-1350

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Fig. 1. (Color online) Cross-sectional view of the high-side LDMOS: (a) conventional structure, (b) proposed structure without a deep N+ sinker, and (c) proposed structure with a Deep N+ Sinker.

Fig. 2. (Color online) Doping proles for the (a) conventional structure, (b) proposed structure without a deep N+ sinker, and (c) proposed structure with a deep N+ sinker.

Fig. 4. (Color online) Breakdown characteristics for the proposed and the conventional high-side LDMOS structures with the same drift region lengths.

Fig. 3. (Color online) Potential distribution at VDS = 70 V for the (a) conventional structure, (b) proposed structure without a deep N+ sinker, and (c) proposed structure with a deep N+ sinker.

study. Referring to Fig. 2, we can see that a carefullyoptimized gap (P-EPI) is inserted between the P-body and the DEEP N-WELL. Figure 3 presents a diagram illustrating the electric potential lines of the proposed structure, with the conventional one for comparison. The potential distribution reveals that the equi-potential lines of the conventional high-side LDMOS between the

P-body and the NBL are denser than there of the proposed one at VDS = 70 V, which implies that a higher electric eld, which limits the breakdown voltage, exists in the depletion region for the conventional high-side LDMOS. We should note that, in contrast to the DEEP N-WELL, the proposed LDMOS experiences has a gap which mitigates the electric eld crowding due to lower doping concentration of P-EPI (1 1015 atom/cm3 ). Figure 4 presents diagrams illustrating the breakdown characteristics for the proposed and the conventional high-side LDMOS structures. The simulation results shows that the breakdown point of the proposed device shifts from 70 V to 115 V when we change the device structure from the conventional device to the proposed one.

III. EXPERIMENTAL RESULT We fabricated 100-V high-side LDMOS transistors in our 0.35-m BCD process. One additional mask layer

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Journal of the Korean Physical Society, Vol. 59, No. 2, August 2011

Fig. 5. (Color online) Experimental breakdown voltage and specic on-resistance for the proposed 100-V high-side LDMOS as functions of the gap between the DEEP N-WELL and the source center.

Fig. 7. (Color online) Experimental IDS -VDS and breakdown voltage characteristics for 100-V high-side LDMOS transistors.

Fig. 6. (Color online) Experimental breakdown voltage and specic on-resistance for the proposed 100-V high-side LDMOS as functions of the gap between the N-layer and the source center.

Fig. 8. (Color online) Simulated impact ionization for the proposed high-side 100-V LDMOS and the conventional LDMOS at VDS = 70 V.

was used for the surface n-layer. Figure 5 shows the characteristics of the breakdown voltage and the specic on-resistance (RON,sp ) as functions of the DNWELL gap from the source center. The breakdown voltage and the specic on-resistance are proportional to the DNWELL gap. The proposed high-side LDMOS provides a breakdown voltage of 110 V and a specic on-resistance of 2.20 mcm2 for a gap of 5.0 m. New paragraph gure 6 presents a schematic diagram illustrating the breakdown voltage and the specic on-resistance (RON,sp ) as a function of the N-layer gap from the source center for a DNWELL gap of 4.5 m. Referring to Figure 6, we can see that the specic on-resistance is proportional to the DNWELL gap. However, the breakdown voltage remain almost unchanged. Therefore, we can see that the N-layer reduces the specic on-resistance while minimizing the change in the breakdown voltage. New paragraph Figure 7 shows the forward IDS -VDS and the breakdown characteristics for the 100-V high-side LDMOS transis-

tors. The devices show good performance up to VG = 8 V and VDS = 100 V. Generally, the on-state breakdown voltage of the LDMOS is lower than the o-state breakdown voltage due to the Kirk Eect [8]. The surface n-layer not only reduces the on-resistance but also eciently reduces the Kirk Eect to ensure a high on-state breakdown voltage. New paragraph gures 8 presents a schematic diagram illustrating the impact ionization rate at 1.3 m from the surface of the N-channel LDMOS transistor. Referring to Fig. 8, we see that the proposed device has a maximum impact ionization as low as 2.44 1016 cm3 s1 at VDS = 70 V whereas the conventional one has a value of 6.69 1019 cm3 s1 at the same condition, which implies that the proposed LDMOS reduces the carrier generation near the drain at high VGS and VDS to ensure a high on-state breakdown voltage [913]. New paragraph Fig. 9 shows the simulated device structure and the impact ionization rates at VDS = 30, 50, and 70 V. The high impact ionization

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REFERENCES
[1] D. Riccardi, A. Causio, I. Filippi, A. Paleari, L. V. A. Pregnolato, P. Galbiati and C. Contiero, in Proceeding The 19th International Symposium on Power Semiconductor Devices and ICs (Jeju, Korea, May 27-31, 2007), p. 73. [2] T. Uhlig, A. Bemmann, C. Ellmers, F. Furnhammer, M. Gross, Y. H. Hu, J. Liu, R-R. Ludwig, M. Reinhold, M. Stoisiek, E. Votintseva and M. Wittmaack, in Proceeding The 19th International Symposium on Power Semiconductor Devices and ICs (Jeju, Korea, May 27-31, 2007), p. 237. [3] J. A. van der Pol et al., in Proceeding The 12th International Symposium on Power Semiconductor Devices and ICs (Toulouse, France, May 22-25, 2000), p. 327. [4] S. Merchant, T. Eand, S. Haynie, W. Headen, K. Kajiyama, S. Paiva, R. Shaw, I. Tachikake, T. Tani and C.-Y. Tsai, in Proceeding The 14th International Symposium on Power Semiconductor Devices and ICs (Santa Fe, New Mexico, USA, June 4-7, 2002), p. 185. [5] M. Inaba, J. Sakano, H. Miyazaki, M. Iwamura, Y. Maeda, K. Mashino, Y. Nagai and M. Mori, in Proceeding The 15th International Symposium on Power Semiconductor Devices and ICs (Cambrige, UK, April 14-17, 2003), p. 97. [6] F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakahama, H. Aoki and K. Hamada, in Proceeding The 16th International Symposium on Power Semiconductor Devices and ICs (Kitakyushu, Japan, May 24-27, 2004), p. 165. [7] C.-J. Ko, S.-Y. Lee, I.-Y. Park, C.-E. Park, B.-K. Jun, Y.-J. Lee, C.-H. Kang, J.-O Lee, N.-J. Kim and K.-D. Yoo, in Proceeding The 21th International Symposium on Power Semiconductor Devices and ICs (Catalonia, Spain, June 14-18, 2009), p. 103. [8] P. Hower, in Proceeding The 14th International Symposium on Power Semiconductor Devices and ICs (Santa Fe, New Mexico, USA, June 4-7, 2002), p. 1. [9] Y.-Gy. Kim, B.-G. Cho, S.-Y. Park and T. Won, J. Nanosci. Nanotechnol. 8, 4565 (2008). [10] H.-G. Kim, S.-Y. Cho, Y.-G. Kim and T. Won, J. Korean Phys. Soc. 53, 1506 (2008). [11] J.-S. Kim and T. Won, Microelectron. Eng. 84, 1556 (2006). [12] H.-G. Kim and T. Won, Jpn. J. Appl. Phys. 47, 4975 (2008). [13] S.-Y. Park, B.-G. Cho, S.-S. Yang and T. Won, J. Nanosci. Nanotechnol. 10, 3600 (2010).

Fig. 9. (Color online) Simulated device structure and impact ionization rates for the proposed and the conventional high-side LDMOS structures.

spot moves from the gate to the drain due to the high current density. As illustrated in Fig. 9, the proposed LDMOS reduces the carrier generation near the drain at high VGS and VDS to ensure a high on-state breakdown voltage. IV. CONCLUSION In this research, a 100-V high-side LDMOS was implemented in a conventional 0.35-m BCD process. The proposed LDMOS employs a deep N+ sinker, a DNWELL gap of 5.0 m, and surface n-layer implants to ensure a high breakdown voltage and a low on-resistance. The proposed high-side LDMOS provides BV = 110 V and RON,sp = 2.20 mcm2 . The proposed process doesnt need any additional thermal budgets thus, all other existing components are available in the new process.

ACKNOWLEDGMENTS This work was supported by the Inha University Research Fund. The authors would like to express special thanks to Dong-Bu Semiconductor for fabricating the LDMOS devices.