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RISC architecture
Atmel A lused d3methods h d toincrease i the h processing i powerof fAVR
Increasetheclockfrequency UsetheHarvardArchitecture UsetheRISCarchitecture Morenumberofcomplexinstructions Someofthemneverusedbyprogrammers Hugecostofimplementingalargenumberofinstructions Mostoftheportionsofthetransistorsonchipareusedbytheinstruction decoders Designersthinkofsimplifyingandreducingthenumberofinstructions Asthisconceptdeveloped,theresultingprocessorscametobeknownasRISC (Reducedinstructionsetcomputers)
CSICarchitecture(Complexinstructionsetcomputer):
RISCarchitecture:
RISC Features
RISCprocessorsh haveafi fixed dinstruction i t ti size. i I InCSICmicrocontroller i t ll instructions i t ti can be1,2,or3bytes.InaRISCarchitecture,thesizeofallinstructionsisfixed.TheCPU candecodetheinstructionsquickly. Largenumberofregisters, registers advantageisthatitavoidstheneedforalargestackto storeparameters.AllRISCarchitectureshaveatleast32registers. RISCprocessorshaveasmallinstructionset.BasicinstructionssuchasADD,SUB, MUL,LOAD,STORE,AND,OR,EXOR,CALLJUMPandsoon.Makesprogrammersjob moretedious,therefore,RSICismorecommonlyusedinhighlevellanguage environmentsuchasC programmingratherthanassemblylanguageenvironment. 95%ofallinstructionsareexecutedwithonlyonclockcycle,incontrasttoCISC instructions. RISCprocessorshaveseparatebusesfordataandcode.Useofseparatebusesfor codeanddataoperandsisreferredtoasHarvardarchitecture. Duetosmall llsetof finstructions,areimplemented l dusingthe h hardwire h d method. h d HardwiringofRISCinstructionstakesonly10%ofthetransistors. RSICusesloadstorearchitecture.
PORTD
Serial
Interrupts Timers
PORTC
AVR microcontroller i t ll
Basic architecture of AVR designed by 2 students of Norwegian Institute of Technology, Alf-Egil Bogen and Vegard Wollan Bought and developed by Atmel in 1996 Different meanings of AVR: Atmel it is a product name It may be Advance Virtual RISC or Alf and Vegard RISC (name of the AVR designers)
AVR Features
8bitRISCsinglechipmicrocontroller H Harvard d A Architecture hi Onchipprogram(code)ROM DataRAM DataEEPROM, TimersandI/Oports ADC PWM ADC, DifferentkindsofserialinterfacessuchasUSART,SPI,I2C (TWI),CAN,USBandsoon
AVR Features
AVRmicrocontrollerprogramROM
8MofprogramROMspace,notallfamilymemberscomewiththatmuch ROMinstalled ProgramROMsizevaryfrom1Kto256K UseonchipFlashmemoryforprogramstorage Flash as memory e o yis sideal dea for o fast astdevelopment de e op e t ca canbee erased asedinseco seconds ds
AVRmicrocontrollerdataRAMandEEPROM
RAMspace datastorage Maximumof64Kbytes y ofdataRAMspace p NotallfamilymemberscomewiththatmuchRAM DataRAMspace 3components:generalpurposeregisters(GPRs),I/O memoryandinternalSRAM 32GPRsinallAVRs SRAMsizeandI/Omemoryssizevariesfromchiptochip EEPROMtostorecriticaldata
AVR Features
AVRmicrocontrollerI/Opins
3to86pinsforI/O NumberofI/Opinsdependsonthenumberofpinsinthepackage itself NumberofpinsforAVRpackage 8to100 8pinAT90S2323 3I/O 100 00p pinAtmega t ega1280 80 86I/O /O
AVRmicrocontrollerperipherals
MostoftheAVRcomeswithADC,timersandUSARTsasstandard p p peripherals ADC 10bit,numberofADCchannelsvariesandcanbeupto16 Upto6timersalongwithwatchdogtimer USART connecttheAVRbasedsystemtoserialportssuchasthe COMportofx86PC AlsocomewithI2CandSPI,someofthemhaveUSBandCANbuses
Availabilityofdevelopmenttools:softwareandhardware
Availabilityofanassemblers,adebugger,acodeefficientC languagecompiler, anemulator,technicalsupportandthirdpartyvendorsupportforthechip
Wideavailabilityandreliablesourcesofmicrocontroller
readyavailabilityinneededquantitiesbothnowandinthefuture
Classifiedinto4g groups: Purpose p Classic, ,Mega, g ,Tiny yandSpecial p p ClassicAVR(AT90Sxxxx) OriginalAVRchip MegaAVR(ATmegaxxxx)
Powerfulmicrocontrollerwithmorethan120instructionsandlots ofdifferentperipheralcapabilities Programmemory 4Kto256Kbytes Package:28to100pins Extensiveperipheralset Extensiveinstructionset
ADDinstruction
ADDRd,Rr ;addRrtoRdandstoretheresultinRd
I/Omemory(SFRs)
Dedicatedtospecificfunctionssuchasstatusregister,timers,serial communication I/Oports communication, ports,ADCandsoon ThefunctionofeachI/OmemorylocationisfixedbyCPUdesigneratthe timeofdesign. Thenumber Th b of fl locations ti i inth thed data t memoryfor f I/Omemorydepends d d onthe th pinnumbersandperipheralfunctionssupportedbythatchip TheAVRhaveatleast64bytesofI/Omemorylocations ItisalsocalledstandardI/Omemory
InternaldataSRAM
UsedforstoringdataandparametersbyAVRprogrammersandCcompilers. compilers Itisgenerallycalledscratchpad
STSinstruction
STSk,Rr LDI R20,0x99 STS0x200 0x200,R20 STS0x201,R20 STS0x202,R20
(storedirecttodataspace)
;storeregisterintothelocationk ;loadR20with0x99 ;storeR20inloc0x200 ;storeR20inloc0x201 ;storeR20inloc0x202
;kisaddressfrom0x0000to0xffff
OUTinstruction
OUTA,Rr LDIR20,0xE2
(OUTtoI/Olocation)
;storeregistertoI/Olocation ;loadR20with0xE2
OUTPORTA,R20;outR20toPORTA
MOVinstruction
MOVRd Rd,Rr R ;Rd Rd=Rr R MOVR10,R20 ;R10=R20
ALU instructions
Status register