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Exposure to the complete design process of FPGA system with wide range of IP core and NIOSII embedded Micro controller .You will learn how to make best use of the latest features of the Quartus II software, including all the productivity and efficiency benefits of using TimeQuest Timing Analysis, Incremental Design and PowerPlay power analysis and optimization. Altera NIOS II & SoPC covers both hardware and software aspects of the design flow and are accessible to engineers. This co-training approach enables successful team working on SoPC designs. This ensures successful convergence in the design flow and the development of efficient architectures. The scope of the course includes an appreciation of the hardware platform, hardware-software partitioning, hardware acceleration as well as software development and debugging. Approximately 50% of class time is spent on practical exercises to reinforce the lectures. The exercises make use of a development board to emphasize the real-world application of the techniques learned. FPGA System Design using VHDL/Verilog (Altera) is developed and maintained by Enixs based on source material from Altera.
Pre-requisites
All participants must be computer literate and must have a basic understanding of digital design and Digital Design Techniques or have a good working knowledge of digital hardware design. Prior experience in C or C++ is preferable.
CONTENTES OF TRAINING PROGRAM General Intro about FPGA architecture and FPGA as a system component
Programmable logic evolution, FPGA vs. CPLD, FPGA essential building blocks, logic mapping to the FPGA, Different classes of pins of an FPGA and system connectivity considerations, Understanding packages and thermal data, FPGA - Memory, Processor, DSP/Multiplier, serial I/Os, Clock management components, FPGA suppliers and differentiation
VHDL - Module 1
VHDL Intro, Entities and Architectures, Instantiation and Port Maps, Structural modeling, Behavioral modeling
VHDL - Module 2
Dataflow modeling, Synthesis of combinational logic and Synthesis of Sequential Logic.
Quartus Design Viewer & planner Chip Planner, RTL Viewer, Technology Map Viewer, Design Flow Automation using TCL commands, Why and when to use DSP Builder Exercises, creating own design partitions, allocating FPGA logic elements, timing and power analysis for revision projects, signal taping for own codes. Designing a System on a Programmable Chip (SoPC)
Why and when to use SoPC, available IPs, SoPC design flow, identifying standard and specific components, User interface, principles, step-by-step system generation, using the wizard and configuring the blocks, defining and customizing the NIOS II processor and tightly coupled memories.
Case studies
Sdram Controller, USB Controller, I2C Controller and Music Player