Design and Construction of a PC-based Partial Discharge Analyzer using FPGA

Rattapoom Vudhichamnong, Thanaporn Thongphuak, Warut Thaweesub, Ekachai Tuntikanokporn, Narong Tongchim and Samruay Sangkasaad
Center of Excellence in Electrical Power Technology Chulalongkom University, Bangkok, Thailand e-mail : rattauoom63,iowit.com
Abstract: This paper presents the implementation of the PC-based PD (Partial Discharge) analyzer. This PD analyzer is capable of measuring both PD level and IEC integrated quantities and analyzing PD data stored in a 3-dimensional distribution. FPGA (Field Programmable Gate Arrays) is the main IC in digital part for circuits implementation to perform real-time data processing, controlling and interfacing to PC. In the analysis process, the H ($,q) distribution is derived from the recorded PD data stream. Fractal features are calculated fi-om the surface of the distribution. Finally, automatic classification of defects will be performed. Real-time measurement and display on Windows98 platform are achieved by using the VxD device driver and the visual-style software developed in C++ language. The test result shows that the characteristic of the PD analyzer complies with IEC Publ. 60270.

lyzer is an indispensable tool for insulation PD ssessment due to the significance of PD over condition the lifetime and reliability of insulation has long been \ recognized. \ However, the use of diagnosis device depends on the ratio between benefit and cost. Therefore high performance of PD analyzer has to be achieved while affordable cost is still maintained. Recent technology in electronics and computer realizes the implementation of high-performance yet low-cost measuring instruments. The PD analyzer can now utilize the combination of FPGA (Field Programmable Gate Arrays), PC and Windows operating system for implementing complicated digital part without compromising ease of use. Moreover, using FPGA means reduction of time-to-market period and using both PC and Windows means real-time displaying and complex analyzing can be performed.

Keywords: PD Analyzer, Insulation diagnosis, FPGA , PC-based instrument, Automatic classification, Fractal features, Centour score
1. INTRODUCTION

2. BRIEF OVERVIEW OF FPGA

n the era of industry and teFology, bulk power transfer is necessary for increasing energy demand. Also with the electric power transmitted on an overhead as line increases approximately with the square of the system operating voltage. While the principle of generating higher voltage is simple, that of insulation for higher voltage is not. Therefore most of the problems in high voltage techniques are concemed with the insulation. With the higher operating voltage for high voltage equipment and with economics reasons, the increasing stress of the insulation is inevitable. Even for welldesigned equipment, the presence of defects during manufacturing, transportation-or installation.@ases adds more possibility for local electric field to be higher than the local dielectric strength. Whenever the condition is met, PD (Partial Discharge) will occur. Although the magnitude of such discharges is usually small, they cause progressive deterioration and may lead to ultimate failure. It is therefore essential to detect and evaluate their presence in a non-destructive quality control test.

FPGA devices feature a gate-array-like architecture, with a matrix of logic cells surrounded by a periphery of I/O cells, as shown in Figure 1[1]. Segments of metal interconnect can be linked in an arbitrary manner by programmable switches to form the desired signal nets between the cells. FPGA combines an abundance of logic gates, registers, and I/Os with fast system speed. FPGA can be programmed and verified quickly compare to normal gate arrays. The offered advantages also include higher integration than existing standard solutions and no non-recurring engineering charges or associated risk possible for mask-programmed gate arrays. Moreover, the designed circuits can be upgraded after production to add more functionality.

VO BLOCKS

LOOlC BLOCKS

Figure 1. FPGA Architecture

0-7803-6355-8/00/ $10.00 Q 2000 IEEE

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3. DESIGN CONCEPT

4.1

ANALOG CIRCUIT

The designed PD analyzer works in a real-time PCbased instrumentation trend. PC is used for data processing, displaying, recording and analysing. Both analog and digital circuits of MI (Measuring Instrument) unit are populated in one PC expansion card. The card was designed to communicate with PC through an ISA (Industrial Standard Architechture) bus because the throughput of the bus is enough for the preprocessed PD data from FPGA and the implementation of interface circuit and device driver to handle ISA bus signals is not complicated. The characteristic of PD detection part was aimed to comply with IEC Publ. 60270. To diagnose the condition of insulation system in high voltage equipment, PD signal is measured and recorded. H, (4, q) distribution matrix is then calculated from the surface of the distribution using the boxcounting method. Finally, automatic classification of defects using Centour score to determine the isoprobability lines from different defect groups is performed.
4. SYSTEM INPLEMENTATION

Analog circuit is used for detecting and processing PD signal and test voltage signal that occur in PD test circuit. The designed CD (Coupling Device) performs two distinct functions. In high-frequency range, CD acts as a passive high-pass filter to separates PD signal from test voltage signal but it acts as the low-voltage arm of the voltage divider, formed by CD and a coupling capacitor Ck, in low-frequency range so that test voltage signal is attenuated up to 92 dB. These two output signals from CD then pass to MI card by two RG-59/U cables. When the filtered PD signal flows into MI, the low-noise digital-controlled amplifier and the active band-pass filter will further condition the signals. For the attenuated test voltage signal, only a generalpurpose digital-controlled amplifier is used. Two 12-bit ADCs (Analog to Digital Converters) are utilized to convert PD and test voltage signals to 12-bit digital format with the sampling rate of 20 MHz and 50 kHz respectively[2]. All the hardware part is diagrammed in Figure 3.
4.2 DIGITAL CIRCUIT

The task of designing and developing the PD analyzer comprises 4 main parts shown in Figure 2. can be described as follows:

Digital
ClKCUlt

+
+

Device Driver

-+

Application
Softvare

& - I

Digital circuit is developed to handle the data and the functionality such as signal processing, system controlling and bus interfacing for an MI. Digital circuits are designed by using VHDL (VHSIC Hardware Description Language) and implemented in a single FPGA, a Xilinx XC4036XL. Digital sub-circuits include a time-base generator, a PD peak detector, a memory unit readwrite controller and I/O transfer controller as shown in Figure 4. PD detection circuit start from processing and recording signals coming from ADC1 and ADC2.

Figure 3. Diagram of the designed PD analyzer

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The two memory units alternately store data with synchronization signal from the zero-crossing of 50 Hz power frequency signal. All digital circuits is also shown in Figure 5.

4.3

DEVICE DRIVER

Device driver is a software that fbnctions as a device controller of a hardware and has capability to interface with an application. Win32 application in Windows98 normally uses device driver or ring0 DLL to communicate with hardware. VxD (Virtual Device Driver) is a 32-bit device driver software that works with VMM (Virtual Machine Manager) to manage system resource so that all programs can share the resource efficiently[3]. VxD works in kernel mode of operating system and then has privilege over application software such as using privileged instruction of CPU to access any part of the system. Since interrupt signal in this PD analyzer can occur upto every 20 ms, VxD was developed to handle such a high repetition signal. The VxD driver used in this work performs interrupt and 110 virtualization, memory buffer management and communication with application software. The application program uses Device I10 Control interface by calling the Win32 API named DeviceIoControl directly to communicate with VxD. In contrast, VxD uses Ring0 Event Handle received from undocumented API named OpenVxDHandle to signal the event to application program. The developed VxD model is shown in Figure 6.

Figure 4. Diagram of digital circuits implemented in FPGA . (Ml, M2 : Memory units)

Application
User

. f N

.fN

Hacdva re

Ope r a t i n g

System

Figure 6. The developed VxD model

4.4 APPLICATION SOFTWARE

Application software handles user interface, data visualization and PD analysis routines. The software was developed on Windows98 using Borland C++ Builder compiler. The software consists of 3 parts that can be described as follows :
1.) PD Detector part displays the measured PD signal. The display area composes of one main signal display frame and two supplementary history frames. This part composes of 4 functions: Calibration, Linear time base display, Elliptical time base display and qVcurve display. Time window and bipolar sensitivity threshold can also be adjusted. This form controls all detection fbnctions and all successive form calls. Example of Calibration display is shown in Figure 7. 2.) Signal Capture part captures unprocessed PD waveform to diagnose problems in analog part such as high level of interference, reflected pulses caused by impedance mismatching, P-response etc. as shown in Figure 8. The signal can be zoomed in for more detail.

4
a

Mcz

Figure 5.All digital circuits

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Figure 7. Calibration display

Figure IO. Distribution form

16117 4 a

Figure 8 Signal Capture frame

3.) PD Analyzer part consists of 5 forms for PD signal analysing. The form calling order is shown in Figure 9.

- Parameter
-

form is shown when pressing "Analyzer" button. All parameters for PD signal recording, such as recording time and number of record count, can be configured in this form. Ellipse form displays the recorded signal on an elliptical time base. Distribution form shown in Figure 10 visualizes PD data in 2 and 3 dimensional distributions. The distributions can be saved to a file or opened from previously stored files or from databases. Fractal form calculates and displays fractal features derived from the distribution file. Decision form shown in Figure 11 features PD database displaying in a tree structure, percentile calculation and automatic recognition for PD diagnostics of high-voltage equipment using Centour score method.

Figure 1 1. Decision form

5 . TEST RESULTS
The test was exercised to ensure that characteristic of the PD detection part complies with IEC Publ. 60270 [4] and the analysis algorithm is correct and reliable. The test result for the PD detection part is shown as follows:

Figure 9. Form calling order in the PD Analyzer part

1.) Frequency response is shown in Figure 12. The test system has f, and f2 equal to 44 kHz and 427 kHz respectively. 2.) Linearity is better than 0.5 percent. 3.) Pulse resolution time is better than 8.5 ps. 4.) Apparent charge readings reside in acceptable ranges of the standard. 5.) Sensitivity for test object having capacitance of 0.1 nF to 100 nF is shown in Figure 13. Sensitivity is better than 1 pC for C, (capacitance of test object) and Ck(capacitance of coupling capacitor) equal to 1 nF.

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1 kHz

10 km

100 kHz

1 MHz

.I
Io MH2

Figure 12. Frequency response of the detection part

sensitivity(pC)
Figure 15. Detected signal of Corona dischaEge

Figure 13. Sensitivity of the PD analyzer for Cr = 1 nF

Field test for ensuring the validity of the analysis algorithm was performed by simulating various defect type. In the demonstration shown in Figure 14, corona discharge was simulated on a high-voltage capacitor. After gradually raising the test voltage, PD was founded to be about 60 pC at 10.5 kV as shown in Figure 15. PD signal was stored and the distribution was visualized in the PD Analyzer mode as shown in Figure 16. Fractal features was then extracted. Finally, automatic fingerprint recognition was performed. The probability of being Corona Discharge was above 70 percent while the probability for other defect groups was essentially zero.

Figure 16. Distribution of Corona discharge pulses

6.

CONCLUSION

The PD analyzer proposed here is capable of detecting and analysing PD in high-voltage equipment. The characteristic of the detection part complies with IEC Publ. 60270. The analysis algorithm can classify the defect effectively on the basis of the validity of the collected database. PC-based instrumentation approach utilized here results in a high-performance yet low-cost measuring system. Due to rapid development in FF'GA technology, the high speed and complex digital circuits can be designed and implemented. It is expected that real-time noise reduction in PD detection can also be achieved by using FPGA.

Figure 14. Demonstration of the PD analyzer

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ACKNOWLEDGEMENT

The authors would like to express their gratitude to The Thailand Research Fund for providing the financial support of this research.

REFERENCES
1. Xilinx Inc. The Programmable Logic Data Book. 1998. p. 1-4. 2. Analog Devices Inc. Short Form Desimers Guide. 1999. pp. 94 - 118. 3. Oney, W. Programming the Microsoft Windows Driver Model. Microsoft Press, 1999. p. 3. 4. IEC 60270. Partial Discharge Measurements.: 1998.

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