EVMOMAPL137 TechRef Revg

OMAP-L137 Evaluation Module
Technical Reference
2008
DSP Development Systems
OMAP-L137 Evaluation Module Technical Reference
511345-0001 Rev. A November 2008
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
Copyright 2008 Spectrum Digital, Inc.
Contents
Introduction to the OMAP-L137 Evaluation Module ............................ 1-1 Provides you with a description of the OMAP-L137 Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview of the OMAP-L137 EVM ............................. 1-4 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply ......................................................... 1-6 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the OMAP-L137 Evaluation Module. 2.1 EMIF-A Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 EMIF-B SDRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Memory Card Interface .............................................. 2-2 2.1.3 UART Interface ................................................... 2-2 2.1.4 USB Interface ..................................................... 2-3 2.2 AIC3106 Interface ...................................................... 2-3 2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 Daughter Card Interface ................................................ 2-6
Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical layout of the OMAP-L137 Evaluation Module and its connectors. 3.1 Board Layout ........................................................ 3.2 Connectors ........................................................ 3.2.1 J1, USB Capacitance Select ........................................... 3.2.2 J2, USB 2.0 Connector and Jumpers ..................................... 3.2.3 J3, USB Connector ................................................... 3.2.4 J4, 14 Pin External JTAG Connector ...................................... 3.2.5 J5, ARM JTAG Emulation Header ........................................ 3.2.6 J6, +5 Volt Input ..................................................... 3.2.7 P1, RS-232 UART ................................................... 3.2.8 P2, MMC/SD Connector ............................................... 3.2.9 P3, Line In .......................................................... 3.2.10 P4, Microphone In .................................................. 3.2.11 P5, Headphone Out ................................................ 3.2.12 P6, Line Out ....................................................... 3.2.13 P8, RJ9 Connector ................................................. 3.2.14 P9, Ethernet Interface .............................................. 3.2.15 P10, Ethernet Interface .............................................. 3.2.16 Expansion Connector Overview ...................................... 3.2.16.1 P11, Audio / Expansion Connector .................................. 3.2.16.2 P12, Expansion 2 Connector ....................................... 3.2.16.3 P13, Expansion 3 Connector ........................................ 3.2.17 P14, Phono Jack In ................................................. 3.2.18 P15, Phono Jack In ................................................. 3.2.19 J201, Embedded JTAG Emulation Interface ............................. 3.3 LEDs ................................................................ 3.4 Switches ............................................................. 3.4.1 SW1, EMU0/1 Select Switch ........................................... 3.4.2 SW2, Boot Mode Select Switch ........................................ 3.4.3 SW3, User Readable 4 Position DIP Switch .............................. 3.4.4 SW4, Reset Switch .................................................. 3.4.5 SW5, Pull-Up Switch ................................................. 3.4.6 SW6, On/Off Switch ................................................. 3.5 Test Points ........................................................ A Schematics .............................................................. Contains the schematics for the OMAP-L137 Evaluation Module B Mechanical Information .................................................. Contains the mechanical information about the OMAP-L137 Evaluation Module
3-1 3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-8 3-9 3-10 3-10 3-11 3-11 3-12 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-18 3-18 3-18 3-19 3-19 3-20 3-22 3-22 3-23 3-23 3-24 A-1 B-1
About This Manual This document describes the board level operations of the OMAP-L137 Evaluation Module (EVM). The EVM is based on the Texas Instruments OMAP-L137 Processor. The OMAP-L137 Evaluation Module is a table top card that allows engineers and software developers to evaluate certain characteristics of the OMAP-L137 processor to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The OMAP-L137 Evaluation Module will sometimes be referred to as the OMAP-L137 EVM or EVM. Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully.
Related Documents, Application Notes and User Guides Information regarding the OMAP-L137 can be found at the following Texas Instruments website: http://www.ti.com
Table 1: Manual History Revision A Beta History
Table 2: Board History PWB Revision D Beta Release History
Chapter 1 Introduction to the OMAP-L137 EVM
Chapter One provides a description of the OMAP-L137 EVM along with the key features and a block diagram of the circuit board.
Topic
1.1 1.2 1.3 1.4 1.5 1.6 Key Features Functional Overview of the OMAP-L137 EVM Basic Operation Memory Map Boot Switch Settings Power Supply
Page
1-2 1-4 1-4 1-5 1-6 1-6
1-1
Spectrum Digital, Inc

1.1 Key Features The OMAP-L137 EVM is a standalone development platform that enables users to evaluate and develop applications for the OMAP-L137 processor. Schematics and application notes are available to ease hardware development and reduce time to market.
On-board JTAG
SD/MMC
DIP LEDs
EMIFA Expansion
Serial Exp. I2C ROM BOOT CFG RTC PWR
EMIFA EMIFB
SD/MMC
Embedded JTAG Emulator SDRAM SDRAM
32 TI JTAG ARM JTAG
OMAP -L137
Audio Expansion
JTAG McASP0/1
TPS65023 VREG
I2C Bus
MII
PWR
AIC3106 CODEC
USB1 / USB0
PWR SW
UART
Micrel ENET PHY + Switch

LINE OUT HP OUT LINE IN MIC IN S/PDIF Handset SPKR Handset MIC
RS-232
ENET RJ45
ENET RJ45
USB1
USB0
Figure 1-1, Block Diagram OMAP-L137 EVM The EVM comes with a full complement of on board devices that suit a wide variety of application environments. Key features include: A Texas Instruments OMAP-L137 device with a C674x VLIW DSP floating point processor and an ARM926EJ-S processor operating up to 300 Mhz. 64 Megabytes SDRAM SPI Boot EEPROM 2 Port Ethernet Phy/switch SD/MMC/MMC Plus media card interfaces TLV320AIC3106 Stereo Codec USB 1.1 High speed interface USB2 2.0 Full speed interface RS-232 Interface
1-2
OMAP-L137 EVM Technical Reference

On chip real time clock Configurable boot load options 4 user LEDs/4 position user DIP switch Single voltage power supply (+5V) Expansion connectors for daughter card use Embedded JTAG Emulation 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces
Figure 1-2, OMAP-L137 EVM
1-3

1.2 Functional Overview of the OMAP-L137 EVM The OMAP-L137 on the EVM interfaces to on-board peripherals through the 16-bit wide multiplexed EMIF interface pins. The SDRAM memory is connected to its own dedicated 32 bit wide bus. An on-board AIC3106 codec allows the DSP to transmit and receive analog audio signals. The I2C bus is used for the codec control interface, while the McASP controls the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond to microphone input, headphone output, line input, and line output. The EVM includes 4 user LEDs, a 4 position user DIP switch, and on chip real time clock. On board multi-plexing allows ease of interfacing to the daughter cards. An included +5V external power supply is used to power the board. On-board switching voltage regulators provide the CPU core voltage, +3.3V, +1.8V for peripheral interfacing. The board is held in reset by the on board power controller until these supplies are within operating specifications. Code Composer Studio communicates with the EVM through an embedded emulator or via the TI 14 pin or ARM 20 pin external JTAG connectors. 1.3 Basic Operation The EVM is designed to work with TIs Code Composer Studio IDETM, or MontaVista tool environments. Code Composer communicates with the board through an on board JTAG emulator. This EVM is shipped with an EVM specific Code Composer Studio environment. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers.
1-4

1.4 Memory Map The OMAP-L137 processor has a byte addressable address space. However, there are some limitations to byte addressing determined by peripheral interconnection to the OMAP-L137 device. Program code and data can be placed anywhere in the unified address space. Addresses are multiple sizes depending on hardware implementation. Refer to the appropriate device data sheets for more details. The memory map shows the address space of a generic OMAP-L137 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of memory can be remapped in software as L2 cache rather than fixed RAM. The part incorporates a dual EMIF interface. One dedicated EMIF, EMIF-B, directly interfaces to the SDRAM memory. EMIF-A has 3 separate addressable regions called chip enable spaces (CE0, CS2, CS3), however the EVM uses this interface as a peripheral interface to daughter card connectors. The memory map of the OMAP-L137 EVM is shown in the table below. Table 1: OMAP-L137 EVM Memory Map
Start Address 0x0080 0000 0x00E0 0000 0x00F0 0000 0x0184 0000 0x1180 0000 0x11E0 0000 0x1FF0 0000 0x8000 0000 0xB000 0000 0xC000 0000 0xFFFE E000 0xFFFF 0000 End Address 0x0083 FFFF 0x00f0 7FFFF 0x00F0 8000 0x0184 FFFF 0x1183 FFFF 0x11E0 7FFF 0x11F0 7FFF 0x8001 FFFF 0xB000 7FFF 0xDFFF FFFF 0xFFFE FFFF 0xFFFF 1FFF ARM Interrupt Controller ARM Local RAM ARM Mem Map DSP Mem Map DSP L2 RAM DSP L1P RAM DSP L1D RAM DSP Memory System DSP L2 RAM DSP L1P RAM DSP L1D RAM Shared RAM EMIFB control regs EMIFB SDRAM Data
1-5

1.5 Boot Switch Settings The EVM has a 5 position switch that allow users to configure the operational state of the processor when it is released from reset and determine the source for processor booting. Switch SW2 configures the boot mode that will be used when the DSP starts executing. By default the switches are configured to serial EEPROM boot. The table below shows the boot mode sources and their respective switch positions. Table 2: SW2, Boot Mode Select
Pos 1 Boot[7] OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON Pos 2 Boot[2] OFF OFF ON ON ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON Pos 3 Boot[1] OFF ON OFF ON ON OFF OFF ON ON OFF OFF OFF OFF ON ON ON ON Pos 4 Boot[0] ON OFF ON OFF ON OFF OFF ON ON OFF OFF ON ON ON ON OFF ON Pos 5 Boot[3] NA NA NA NA NA OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF Boot Pin BTMODE[7,2,1,0,3] 0 0 0 1 x 0 0 1 0 x 0 1 0 1 x 0 1 1 0 x 0 1 1 1 x 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 0 Boot Mode NOR HPI SPI0 Flash SPI1 Flash NAND 8-bit I2C0 Master I2C0 Slave I2C1 Master I2C1 Slave SPI0 EEPROM * SPI1 EEPROM SPI0 Slave SPI1 Slave UART0 UART1 UART2 * Emulation Debug *
* Supported on Standalone EVM 1.6 Power Supply The EVM operates from a single +5V external power supply connected to the main power input (J6), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into core voltage, +1.8V and +3.3V using Texas Instruments TPS65023 Power Management Unit. The +3.3V and +1.8V supply are used for the DSP's I/O buffers and other chips on the board.
1-6
Chapter 2 Board Components
This chapter describes the operation of the major board components on the OMAP-L137 EVM.
Topic
2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.3 2.4 2.5 EMIF-A Interfaces EMIF-B SDRAM Memory Interface Memory Card Interface UART Interface USB Interface AIC3106 Interface Ethernet Interface I2C Interface Daughter Card Interface
Page
2-2 2-2 2-2 2-2 2-2 2-3 2-4 2-5 2-6
2-1

2.1 EMIF-A Interfaces A separate 16 bit EMIF with three chip enables divide up the address space and allow for asynchronous accesses on the EVM. The EVM uses this interface for peripheral interfaces to the daughter card.
2.1.1 EMIF-B SDRAM Memory Interface The OMAP-L137 device incorporates a dedicated 32 bit wide SDRAM memory bus. The EVM uses two 256 Megabit, 16 bit wide memories on this bus, for a total of 64 megabytes of memory for program, data, and video storage. The internal SDRAM controller uses a PLL to control the SDRAM memory timing. Memory refresh for SDRAM is handled automatically by the OMAP-L137 internal SDRAM controller.
2.1.2 Memory Card Interface The EVM supports SD/MMC/MMC PLUS media card interfaces. This interface is multiplexed with other function the EMIFA bus.
2.1.3 UART Interface The internal UART2 on the OMAP-L137 device is driven to connector P1. The UARTs interface is routed to the RS-232 line drivers prior to being brought out to a DB-9 connector, P1.
2.1.4 USB Interface The OMAP-L137 incorporates two on chip USB controllers. The USB 2.0 interface is brought out to a micro A/B connector. A jumper is provided to make a flexible host, peripheral, and USB on the go interface. The second USB 1.1 interface is brought out to an A type host interface connector.
2-2

2.2 AIC3106 Interface The EVM incorporates a Texas Instruments TLV320AIC3106 stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line output so the user can hear the output. The codec communicates using two serial channels, one to control the codecs internal configuration registers and one to send and receive digital audio samples. The I2C bus is used as the AIC3106s control channel. The control channel is generally only used when configuring the codec, it is typically idle when audio data is being transmitted, McASP1 is used as the bi-directional data channel. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The EVM examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The codec is clocked via a 24.576 Mhz oscillator. The internal sample rate generator subdivides the default system clock to generate common audio frequencies. The sample rate is set by a codec register. The figure below shows the codec interface on the OMAP-L137 EVM.
AIC3106 Codec IC
SCL SDA Control I2C Format Digital SCL SDA Control Registers Analog LINE OUT
2
MIC IN
LINE IN
McASP
AXR[0] AXR[5] ACLKR ACLKX AFSR AFSX DOUT DIN BCLK WCLK ADC MIC IN LINE IN DAC LINE OUT HP OUT HP OUT
Figure 2-1, OMAP-L137 EVM CODEC INTERFACE
2-3

2.3 Ethernet Interface The OMAP-L137 incorporates an ethernet MAC which interfaces to a Micrel KSZ8893MQL ethernet switch. The multi-port 10/100 Mbit interface is isolated and brought out to two RJ-45 standard ethernet connectors, P9, P10. The ethernet addresses is stored in the on board I2C EEPROM. The 2 ethernet addresses stored in the EEPROM are the first address and the address + 1. The first address should always be an even number. The I2C bus is also used to control configuration registers in the switch that are not accessible via the MDIO module. Two ports provide the ability to input and pass data for Voice Over IP (VOIP) or other daisy chained applications. Connector P9 is the primary port for normal operation. The RJ-45 jacks have 2 LEDs integrated into their connector. The LEDs are green and yellow and provide link and transmit status from the ethernet controller. The MAC address for each EVM is also written on a label on the bottom of the board. The figure below shows an examples of this.
Figure 2-2, OMAP-L137 MAC Address
2-4

2.4 I2C0 Interface The I2C0 bus on the OMAP-L137 is ideal for interfacing to the control registers of many devices. On the OMAP-L137 EVM the I2C0 bus is used to configure the ethernet phy and Codec. An I2C ROM is also interfaced via the serial bus. The format of the bus is shown in the figure below. Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop Write Sequence Start Slave Address R Data STOP Read Sequence Figure 2-3, I2C Bus Format The addresses of the on board peripherals are shown in the table below. Table 1: I2C0 Memory Map Device KSZ8893MQL TLV320AIC3106 I2C EEPROM Address 0x5D 0x1B 0x25 R/W R/W R/W R/W Function Ethernet Switch CODEC I2C EEPROM
2-5

2.5 Daughter Card Interfaces The EVM provides expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their EVM platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are interfaces which include McASP, and serial I/O expansion. The EMIF-A signals are brought out as LCD, peripheral, or EMIF signals. The daughter card connectors used on the EVM are shown in the table below. Table 2: Daughter Card Connectors Reference Designator P11 P12 P13 Part Numbers Used On EVM QSE-040-01-L-D-A-K QSE-020-01-L-D-A-K QSE-040-01-L-D-A-K Manufacturer Samtec Samtec Samtec
One of the compatible mating daughter card connectors used to interface to the EVM are shown in the table below (other heights are available). Table 3: Mating Daughter Card Connectors Reference Designator XP11 XP12 XP13 Part Numbers Used On EVM QTE-040-02-L-D-A-K QTE-020-02-L-D-A-K QTE-040-02-L-D-A-K Manufacturer Samtec Samtec Samtec
2-6
Chapter 3 Physical Description
This chapter describes the physical layout of the OMAP-L137 EVM and its interfaces.
Topic
3.1 Board Layout 3.2 Connectors 3.2.1 J1, USB Capacitance Select 3.2.2 J2, USB 2.0 Connector and Jumpers 3.2.3 J3, USB 1.1 Connector 3.2.4 J4, 14 Pin External JTAG Connector 3.2.5 J5, ARM JTAG Emulation Header 3.2.6 J6, +5V Input 3.2.7 P1, RS-232 UART 3.2.8 P2, MMC/SD Connector 3.2.9 P3, Line In 3.2.10 P4, Microphone In 3.2.11 P5, Headphone Out 3.2.12 P6, Line Out 3.2.13 P8, RJ9 Connector 3.2.14 P9, Ethernet Interface 3.2.15 P10, Ethernet Interface 3.2.16 Expansion Connector Overview 3.2.16.1 P11, Audio / Expansion Connector 3.2.16.2 P12, Expansion 2 Connector 3.2.16.3 P13, Expansion 3 Connector 3.2.17 P14, Phono Jack In 3.2.18 P15, Phono Jack In 3.2.19 J201, Embedded JTAG Emulation Interface
Page
3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-8 3-9 3-10 3-10 3-11 3-11 3-12 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-18 3-18
3-1
Topic
3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.5 3.5 LEDs Switches SW1, EMU0/1 Select Switch SW2, Boot Mode Select Switch SW3, User Readable 4 Position DIP Switch SW4, RESET Switch SW5, Mux Control Switch SW6, On/Off Switch Test Points
Page
3-18 3-19 3-19 3-20 3-22 3-22 3-23 3-23 3-24
3-2

3.1 Board Layout The OMAP-L137 EVM is a 5.0 x 8.55 inch (127 x 217 mm.) ten (10) layer printed circuit board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the top side of the OMAP-L137 EVM.
SW6
J6
DS7
SW4
J201
P1
J205 P9 DS501 SW1 P2 P10 J5 P8 P14 P3 P4 P5 P15 P6 J3 J1 J2 P11 P12 SW5 DS1-4 SW3 J4 DS5,8,9 DS5 P13 SW2
Figure 3-1, OMAP-L137 EVM, Interfaces Top Side 3-3

3.2 Connectors The EVM has numerous connectors and option jumpers to control and provide connections to various peripherals. These connectors and jumpers are described in the following sections. Table 1: Connectors
Connector J1 J2 J3 J4 J5 J6 P1 P2 P3 P4 P5 P6 P8 P9 P10 P11 P12 P13 P14 P15 J201 J205 2x5 Size 1x2 2 6 2x7 2x8 2 9 28 4 4 4 4 4 12 12 2 x 45 2 x 22 2 x 45 3 3 Function USB Capacitance Select USB Interface USB Interface TI 14 Pin JTAG ARM JTAG Emulation Header +5V In RS-232 UART SD/MMC Connector Line In Microphone In Headphone Out Line Out RJ9 Connector Ethernet Ethernet Audio Expansion Connector Expansion 2 Expansion 3 Phono Jack Phono Jack Embedded JTAG Interface Not populated, factory use only
3-4

3.2.1 J1, USB Capacitance Select Connector J1 is a jumper is used to provide more capacitance when the USB connector is used in the host mode. When the jumper is shorted the extra capacitance is provided. These open and shorted position are shown below.
Open USB VBUS J1 J1 Shorted USB VBUS
Figure 3-2, J1, USB Capacitance Select
Table 2: J1, USB Capacitance Select

Position Open Shorted Function 6.8 uF Capacitance 106.8 uF Capacitance
3-5

3.2.2 J2, USB 2.0 Connector and Jumpers Connector J2 is a micro A/B USB connector. The pinout for the J2 connector is shown in the table below. Table 3: J2, USB Connector
Pins 1 2 3 4 5-9 Signal USB_VBUS USB_DM USB_DP USB_ID USB_SHIELD
* Use internal register to swap DM/DP pair. This feature was used to improve printed circuit board routing.
The EVM supplies up to 500 ma of current to the USB_VBUS via a TPS2065. This is enabled via the OMAP-L137s DRV_VBUS pin. J1 supplies extra capacitance for host mode operations. Remove J1 for USB On The Go operations.
3.2.3 J3, USB 1.1 Connector Connector J3 is a USB-A connector. This connector is connected directly to the OMAP L137 processor. A TPS2065 switches on host power via the L137 GPIO[15]. The pinout for the J3 connector is shown in the table below. Table 4: J3, USB Connector
Pins 1 2 3 4 5 6 Signal VBUS D-, USB1_DM D+, USB1_DP GND, Ground USB_Shield USB_Shield
3-6

3.2.4 J4, 14 Pin External JTAG Connector Connector J4 is a 2 x 7 double row male header. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown in the figure below. TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TRSTGND no pin (key) GND GND GND EMU1
Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal
Figure 3-3, 14 Pin External JTAG Connector
3.2.5 J5, ARM JTAG Emulation Header The J5 emulation header is located on the top side of the board and is used to provide an interface to ARM compatible JTAG emulators. The pinout for this connector is shown in the table below. Table 5: J5, ARM JTAG Emulation Header
Pin # 1 3 5 7 9 11 13 15 17 19 Signal VCC_3V3 ARM_TRSTn ARM_TDI ARM_TMS ARM_TCK ARM_TCKRET ARM_TDO ARM_RSTn NC NC Pin # 2 4 6 8 10 12 14 16 18 20 Signal VCC_3V3 Ground Ground Ground Ground Ground Ground Ground Ground Ground
3-7

3.2.6 J6, +5V Input Connector J6 is the input power connector. This connector brings in +5 volts to the EVM. This is a 2.5mm. jack. The inside of the jack is tied to through a fuse to VCC_5V. The other side is tied to ground and LED DS7. The figure below shows this connector as viewed from the card edge. +5V J6 Ground PC Board Front View Figure 3-4, J6, +5 Volt Input Connector
3.2.7 P1, RS-232 UART The P1 connector is a 9 pin male D-connector which provides a UART interface to the EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U28) and is located on the top side of the board. A view of the connector from the card edge is shown in the figure below. The signals present on this connector are defined in the following table.
5 9 4 8 3 7 2 6 1
Figure 3-5, P1, DB9 Male Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a standard dual row to DB-9 connector interface used on personal computers. Table 6: P1, RS-232 Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name NC R_IN, Rx Data T_OUT, Tx Data NC GND NC Pin 8 Pin 7 NC
3-8

3.2.8 P2, MMC/SD Connector The P2 MMC/SD connector is located on the top side of the board and is used to provide an interface to the following interfaces: MMC+, SD, and MMC. The pinout for the P2 connector is shown in the table below. Table 7: P2, MMC/SD Connector
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Signal MMC_SD_DATA3 - #1_MMC+/MMC/SD MMC_SD_CMD - #2_MMC+/MMC/SD GND - #3_MMC+/MMC/SD DSK_3V3 - #4_MMC+/MMC/SD MMC_SD_CLK - #5_MMC+/MMC/SD GND - #6_MMC+/MMC/SD MMC_SD_DATA0 - #7_MMC+/MMC/SD MMC_SD_DATA1 - #8_MMC+/SD MMC_SD_DATA2 - #9_MMC+/SD MMC_SD_DATA4 - #10_MMC+ MMC_SD_DATA5 - #11_MMC+ MMC_SD_DATA6 - #12_MMC+ MMC_SD_DATA7 - #13_MMC+/ MMC_SD_WP - SD_WP MMC_SD_INS - CD Reserved Reserved GND DSK_3V3 Reserved GND Reserved Reserved Reserved NC NC GND GND
3-9

3.2.9 P3, Line In Connector P3 is an stereo audio line input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground (sleeve) Left Line In (ring) Right Line In (tip) Figure 3-6, P3, Audio Line In Stereo Jack
Table 8: P3, Line In Interface

Pin # 1 (sleeve) 2 (ring) 3 (tip) 4 (sleeve) AIC3106 Signal GND_AC LINE1L+ LINE1R+ GND_AC
3.2.10 P4, Microphone In Connector P4 is an stereo microphone line input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground (sleeve) Left Line In (ring) Right Line In (tip) Figure 3-7, P4, Microphone In Stereo Jack
Table 9: P4, Microphone In Interface

Pin # 1 (sleeve) 2 (ring) 3 (tip) 4 (sleeve) AIC3106 Signal GND_AC MIC3L/MIC3R MIC3L/MIC3R GND_AC
3-10

3.2.11 P5, Headphone Out The P5 connector is a 3.5 mm. stereo headphone output from the TVL320AIC3106 on the EVM. The signals on the mating plug are shown in the figure below The signals present on this connector are defined in the following table.
Ground (sleeve) Right Line Out (ring) Left Line Out (tip) Figure 3-8, P5, Headphone Out Stereo Jack
Table 10: P5, Headphone Out Interface

Pin # 1(sleeve) 2(ring 3(tip) 4 AIC3106 Signal GND_AC HPLOUT HPROUT NC
3.2.12 P6, Line Out The audio line out connector P6, is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground (sleeve) Right Line Out (ring) Left Line Out (tip) Figure 3-9, P6, Audio Line Out Stereo Jack
Table 11: P6, Audio Line Out Stereo Jack

Pin # 1 (sleeve) 2 (ring) 3 (tip) 4 (sleeve) AIC33 Signal GND_AC LEFT_LO+ RIGHT_LO+ NC
3-11

3.2.13 P8, RJ9 Connector The headset interface, P8, is a standard RJ9-4 connector which is not populated as shipped.
3.2.14 P9, Ethernet Interface The P9 connector is located on the top side of the board and is used to provide an Ethernet interface. P9 integrates the magnetics and standard RJ-45 connector. The two tables below show the signals present on the magnetics interface and the connector side. Table 12: P9, Magnetics/LEDs Interface Signals
Pin # 1 3 5 7 9 11 Signal TXP1 (TXD+) RXP1 (RXD+) ENET_VDDATR (RXD-CT) NC1 VCC_3V3(LED1+) DSK_3V3(LED2+) Pin # 2 4 6 8 10 12 Signal TXM1 (TXD-) ENET_VDDATR (TXD-CT) RXM1 (RXD-) GND P1LED2(LED1-) P1LED3(LED2-)
The ethernet connector incorporates 2 LEDs which give link and transmit status from the ethernet controller. Table 13: P9, RJ-45 Connector
Pin # 1 3 5 7 Signal TX_DATA+ RX_DATA+ NC NC Pin # 2 4 6 8 Signal TX_DATANC RX_DATANC
3-12

3.2.15 P10, Ethernet Interface The P10 connector is located on the top side of the board and is used to provide an Ethernet interface. P10 integrates the magnetics and standard RJ-45 connector. The two tables below show the signals present on the magnetics interface and the connector side. Table 14: P10, Magnetics/LEDs Interface Signals
Pin # 1 3 5 7 9 11 Signal TXP2 (TXD+) RXP2 (RXD+) ENET_VDDATR (RXD-CT) NC1 VCC_3V3(LED1+) DSK_3V3(LED2+) Pin # 2 4 6 8 10 12 Signal TXM2 (TXD-) ENET_VDDATR (TXD-CT) RXM2 (RXD-) GND P2LED2(LED1-) P2LED3(LED2-)
The ethernet connector incorporates 2 LEDs which give link and transmit status from the ethernet controller. Table 15: P10, RJ-45 Connector
Pin # 1 3 5 7 Signal TX_DATA+ RX_DATA+ NC NC Pin # 2 4 6 8 Signal TX_DATANC RX_DATANC
3-13

3.2.16 Expansion Connector Overview The EVM has three expansion connectors which allow the user to interface to other logic which is unique to his application Some of the signals on the EVM are multiplexed with an on board resource or they have multiple options on the L137 device. To enable these signals there are several control lines on the expansion connector. Pulling the control lines high enables the functions marked in the Mux_Ctl column tables. The number in the Mux_Ctl column indicates which pins it controls. An N in front of the column indicates the pin is available when the control line is not pulled high. Each control line is pulled down on the EVM, therefore a pull-up resistor of approximately 500 ohms is required to enable the control line to a logic 1. A * in the Mux_Ctl column indicates this is a control line on the expansion connectors. The next 3 tables indicate the interface signal and the appropriate control line on the pins of the expansion connectors.
3-14

3.2.16.1 P11, Audio / Expansion Connector Table 16: P11, Audio / Expansion Connector
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
Signal
VCC_5V VCC_5V NC SEL_ENETn_MCASP0 T_AMUTE0 Ground EXP1_AFSX0 Ground T_ACLKX0 Ground EXP_AXR0[0] EXP_AXR0[1] EXP_AXR0[2] EXP_AXR0[3] EXP_AXR0[4] EXP_AXR0[5] EXP_AXR0[6] EXP_AXR0[7] Ground AHCLKR2 EXP1_SPI1_SCSn EXP1_SPI1_CLK EXP_RESETn Ground T_AMUTE1 Ground EXP_AFSX1 Ground EXP_ACLKX1 Ground EXP_AXR1[0] EXP_AXR1[1] EXP_AXR1[2] EXP_AXR1[3] EXP_AXR1[4] EXP_AXR1[5] EXP1_SEL_MCASP1 NC VCC_5V VCC_5V Ground Ground Ground Ground NC
Mux_Ctl
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
Signal
VCC_5V VCC_5V I2C0_SDA I2C0_SCL EXP_ACHLKR0 Ground T_AFSR0 Ground T_ACLKR0 Ground EXP_AXR[8] EXP_AXR0_9 EXP_AXR0_10 EXP1_AXR0_12 EXP1_AXR0_13 EXP1_AXR0_14 EXP1_AXR0_15 T_AXR0_11/AXR2_0/GPIO3_11 Ground EXP1_AMUTE2_8 EXP1_SPI1_ENAn EXP1_SPI1_SIMO EXP1_SPI1_SOMI Ground EXP_AHCLKX1 Ground T_AFSR1 Ground T_ACLKR1 Ground T_AXR1[6] T_AXR1[7] T_AXR1[8] T_AXR1[9] T_AXR1[10] T_AXR1[11] SEL_SPI1_EXP1 NC VCC_5V VCC_5V Ground Ground Ground Ground NC
Mux_Ctl
*1
1 1 1 1 1 1 1 1
1 N7 N7 N11 N11 N11 N11
N12 3
2 2 2
N5 N5 2 *2
*3
* 1 Control line for Mux_Ctl 1 signals, * 3 Control line for Mux_Ctl 3 signals, * N7 is not control signal 7 (default), * N12 is not control signal 12 (default)
* 2 Control line for Mux_Ctl 2 signals * N5 is not control signal 5 (default) * N11 is not control signal 11 (default)
3-15

3.2.16.2 P12, Expansion 2 Connector Table 17: P12, Expansion 2 Connector
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
Signal
VCC_5V VCC_5V Ground EXP_SPI1_SOMI EXP2_SPI1_SIMO EXP_SPI1_CLK EXP2_SPI1_SCSn EXP2_SPI1_ENAn Ground SEL_SPI1_EXP2 EXP_EQEP1A EXP_EQE1B SEL_EXP2_QEP1 EXP2_UART1_RXD EXP2_UART1_TXD Ground SEL_EXP2_UART1 EXP_RESETn VCC_5V VCC_5V Ground Ground
Mux_Ctl
Pin
1 3 5
Signal
VCC_5V VCC_5V Ground EXP2_SPI0_SOMI EXP2_SPI0_SOMO EXP2_SPI0_CLK EQEP0A EQEP0B Ground IC20_SCL IC20_SDA NC SEL_EXP2_QEP0 EXP2_TMP640_OUT12 EXP2_TMP640_IN12 Ground SEL_SPI1_EXP2_B SEL_EXP2_TIMER VCC_5V VCC_5V Ground Ground
Mux_Ctl
9 9 9 4 4 *4 5 5 *5 7 7 *7
7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
6 6 6 6 6
*6 9 9 *8 *9
* 4 Control line for Mux_Ctl 4 signals * 5 Control line for Mux_Ctl 5 signals * 6 Control line for Mux_Ctl 6 signals * 7 Control line for Mux_Ctl 7 signals * 8 Control line for Mux_Ctl 8 signals * 9 Control line for Mux_Ctl 9 signals
3-16

3.2.16.3 P13, Expansion 3 Connector Table 18: P13, Expansion 3 Connector
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
Signal
VCC_5V VCC_5V EXP3_SEL_MEMD0_7 EXP3_SEL_MEM Ground EXP_EMIFA_D0 EXP_EMIFA_D2 EXP_EMIFA_D4 EXP_EMIFA_D6 Ground EXP_EMIFA_D8 EXP_EMIFA_D10 EXP_EMIFA_D12 EXP_EMIFA_D14 Ground EXP3_SEL_MEMD8_D11 EXP3_SEL_MEMD12_D16 Ground EXP3_EMIFA_CLK Ground Ground EXP3_EMIFA_OEn EXP3_EMIFA_WEn Ground EMIFA_WAIT0 EMIFA_CS0n NC EMIFA_BA0 EMIFA_A0 EXP_EMIFA_A2 EMIFA_A3 EMIFA_A5 EMIFA_A7 EMIFA_A9 EMIFA_A11 Ground EXP_RESETn NC VCC_5V VCC_5V Ground Ground Ground Ground NC
Mux_Ctl
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
Signal
VCC_5V VCC_5V NC EXP3_SEL_MEM_CTL Ground EXP_EMIFA_D1 EXP_EMIFA_D3 EXP_EMIFA_D5 EXP_EMIFA_D7 Ground EXP_EMIFA_D9 EXP_EMIFA_D11 EXP_EMIFA_D13 EXP_EMIFA_D15 Ground EXP_EMIFA_WEn_DQM0 EXP_EMIFA_WEn_DQM1 Ground EMIFA_SDCKE Ground Ground EMIFA_CS4n EMIFA_CS5n NC EMIFA_CS2n EXP3_EMIFA_CS3n NC EMIFA_BA1 EXP_EMIFA_A1 EMIFA_A4 EMIFA_A6 EMIFA_A8 EMIFA_A10 EMIFA_A12 NC Ground NC NC VCC_5V VCC_5V Ground Ground Ground Ground NC
Mux_Ctl
* 10 * 11 10 10 10 10 13 13 14 14 * 13 * 14
* 12 10 10 10 10 13 13 14 14 11 11
11 11
10 10
12
10
10
* 10 Control line for Mux_Ctl 10 signals * 11 Control line for Mux_Ctl 11 signals * 12 Control line for Mux_Ctl 12 signals * 13 Control line for Mux_Ctl 13 signals * 14 Control line for Mux_Ctl 14 signals 3-17

3.2.17 P14, Phono Jack In Connector P14 is a phono jack input. This connector is not populated as shipped.
3.2.18 P15, Phono Jack In Connector P15 is a phono jack input. This connector is not populated as shipped.
3.2.21 J201, Embedded JTAG Emulation Interface Connector J201 is a USB interface providing JTAG access to the processor. This allows the user to develop and debug using Code Composer Studio on a PC.
3.3 LEDs The EVM has ten (10) LEDs which are located on the top side of the board. Information regarding the LEDs are shown in the table below. Table 19: LEDs
LED # DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS501 Use User control, EMIFA D12 User control, EMIFA D13 User control, EMIFA D14 User control, EMIFA D15 USB-EMU ON/OFF VCC_1V2 VCC_5V VCC_1V8 VCC_3V3 On board EMU status Color Green Green Green Green Green Green Green Green Green Green
3-18

3.4 Switches The EVM has six (6) switches. The function of these switches are shown in the table below. Table 20: Switches
Switch SW1 SW2 SW3 SW4 SW5 SW6 Function EMU0/EMU1 Control Boot Mode Select User Readable RESET Switch Pull Up Select On/Off Power Switch Type 4 Position DIP 6 Position DIP 4 Position DIP Push Button/Momentary 6 Position DIP Toggle
3.4.1 SW1, EMU0/1 Select Switch SW1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0 and EMU1 pins on the OMAP-L137 processor. This switch is not needed for the OMAP-L137 processor. The default is to select pull ups on the EMU0 and EMU1.
3-19

3.4.2 SW2, Boot Mode Select Switch Switch SW2 is a 6 position DIP switch. Only 5 of the positions are used. Note that only 5 combinations provide valid options. The boot mode options are described in the table below. Table 21: SW2, Boot Mode Select DIP Switch Position 1 2 3 4 5 6 Pins 1-12 2-11 3-10 4-9 5-8 6-7 Signal BOOTMODE[7] BOOTMODE[2] BOOTMODE[1] BOOTMODE[0] BOOTMODE[3] NC
The figure below shows the SW2 switch.

Raised Actuator SW2 1 1 2 2 3 3 4 4 5 5 6 6 12 11 10 9 8 7
Figure 3-10, SW2, Boot Mode Select Switch
3-20

The table below shows the position settings which select the various boot modes. Table 22: SW2, Boot Mode Select
Pos 1 Boot[7] OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON Pos 2 Boot[2] OFF OFF ON ON ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON Pos 3 Boot[1] OFF ON OFF ON ON OFF OFF ON ON OFF OFF OFF OFF ON ON ON ON Pos 4 Boot[0] ON OFF ON OFF ON OFF OFF ON ON OFF OFF ON ON ON ON OFF ON Pos 5 Boot[3] NA NA NA NA NA OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF Boot Pin BTMODE[7,2,1,0,3] 0 0 0 1 x 0 0 1 0 x 0 1 0 1 x 0 1 1 0 x 0 1 1 1 x 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 0 Boot Mode NOR HPI SPI0 Flash SPI1 Flash NAND 8-bit I2C0 Master I2C0 Slave I2C1 Master I2C1 Slave SPI0 EEPROM * SPI1 EEPROM SPI0 Slave SPI1 Slave UART0 UART1 UART2 * Emulation Debug *
* Supported in standalone EVM
3-21

3.4.3 SW3, User Readable 4 Position DIP Switch Switch SW6 is a 4 position DIP switch mapped to EMIFA data bus lines D8-D11 via a multiplexer. The table below shows what signal each position appears on.
ON Raised Actuator
3 2 SW3
Figure 3-11, SW3, User Readable 4 Position DIP Switch
Table 23: SW3, User Readable 4 Position DIP Switch Position 1 2 3 4 Signal SW_DIP0, EMIFA - D8 SW_DIP1, EMIFA - D9 SW_DIP2, EMIFA - D10 SW_DIP3, EMIFA - D11
3.4.4 SW4, RESET Switch Switch SW4 is a push button reset switch that will RESET the board.
3-22

3.4.5 SW5, Mux Control Switch Switch SW5 is a 6 position DIP switch that allows mux control signals to be pulled up to +3.3 volts. This switch allows enabling on mux control signals. The six signals that can be pulled up are shown in the table below. Alternatively the multiplexer control lines can be enabled via daughter card connectors. Additional control lines are mapped to the daughter card connectors. Refer to the expansion connector sections 3.2.16.1 to 3.2.16.2 for more information. Table 24: SW5, Pull-Up Switch Position SW5-1 SW5-2 SW5-3 SW5-4 SW5-5 SW5-6 Signal SEL_ENETn_MCASP0 SEL_EXP2_TIMER SEL_EXP2_UART1 ON_BD_OFF_BD EXP3_SEL_MEMD8-D11 EXP3_SEL_MEMD12-D15 Mux_Ctl *1 *9 *7 U19 control for USB * 13 * 14
The figure below shows the SW5 switch.

CFG_EN 1 1 2 2 Raised Actuator 3 3 4 4 5 5 6 6 12 11 10 9 8 7 SW5
Figure 3-12, SW5, Pull-Up Switch
3.4.6 SW6, On/Off Switch Switch SW6 is an on/off toggle switch that allows +5 volts from the J6 connector to be applied to the board.
3-23

3.5 Test Points The EVM has 49 test points. All test points appear on the top of the board. The following figure identifies the position of each test point. The next table lists each test point and the signal appearing on that test point.
TP31
TP27
TP32
TP34
TP20
TP515
TP14
TP13
TP33 TP16 TP15 TP520 TP35-38 TP517 TP26 TP24
TP21 TP17 TP22 TP18 TP23 TP9-12 TP25 TP6 TP514 PTP4 PTP5 TP7 TP8 TP40 TP39 TP4 TP5 PTP9 PTP7 PTP1 PTP3 TP2 TP1 PTP6 PTP8 PTP2 PTP10
Figure 3-13, OMAP-L137 EVM, Test Points
3-24

Table 25: OMAP-L137 EVM Test Points
Test Point #
TP1 TP2 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15
Signal
U13, Pin 6,7,8, VBUS From J2 DSK_3V3, U13, Pin 5, OCn U14, Pin 6,7,8, VBUS from J3 DSK_3V3, U14, Pin 5, OCn U1, F7, RSV1 U38, Pin 35, GPIO1 U38, Pin 35, GPIO2 U38, Pin 45, MFP0 U38, Pin 46, MFP1 U38, Pin 47, MFP2 U38, Pin 48, MFP3 U41, Pin 2, P1LED1 U41, Pin 3, P1LED0 U41, Pin 5, P2LED1
Test Point #
TP16 TP27 TP28 TP29 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP515 TP517 TP520
Signal
U41, Pin 6, P2LED0 U44, Pin 28, INTn U44, Pin 20, VLDO1 U44, Pin 18, VLDO2 VCC_5V U54, Pin 5, ALT_CPU_1V2 USB1, TAIN0 USB1, TAIN1 USB1, TAIN2 USB1, TAIN3 U38, Pin 27, MONO_LO+ U38, Pin 28, MONO_LOFactory Use Factory Use Factory Use
There are 10 power test point pairs for major power domains on the EVM. These test points provide a convenient mechanism to check the EVMs multiple power supplies. The table below shows the voltages for each test point and what the supply is used for. Table 26: Power Test Points
Access Test Points
TP17, TP18 TP19, TP20 TP21, TP22 TP23, TP24 TP25, TP26
Voltage
DSK_3V3 CPU_1V2 CPU_3V3 DSK_1V8 CPU_1V8
Shunt
0.025 ohms 0.025 ohms 0.025 ohms 0.025 ohms 0.025 ohms
Comments
All EVM 3.3V supplies except CPU All CPU 1.2V supplies All CPU 3.3V supplies All EVM 1.8V supplies except CPU All CPU 1.8V supplies
3-25

Furthermore the EVM has ten 2 pin power test points for specific power domains on the L137 device. These voltages are measured across a resistor which is why there are two points to each test position. The square pad is the ground. The round pad is the measured voltage. The figure below shows what a typical power test point looks like.
Measured voltage Pin 2 Ground Pin 1
Figure 3-14, Power Test Point The table below shows the power test points and the voltage measured. Table 27: Power Test Points
Power Test Point
PTP1 PTP2 PTP3 PTP4 PTP5 PTP6 PTP7 PTP8 PTP9 PTP10
Voltage Measured
CPU_3V3 CPU_1V2 CPU_1V2 CPU_1V2 CPU_1V2 CPU_1V2 CPU_3V3 CPU_1V8 CPU_3V3 CPU_1V8
3-26
Appendix A Schematics
This appendix contains the schematics for the OMAP-L137 EVM.
A-1
A-2
4 3 2 1
SCHEMATIC CONTENTS
D
SHEET01 SHEET02 SHEET03 SHEET04 SHEET05 SHEET06 SHEET07 SHEET08 SHEET09 SHEET10 SHEET11 SHEET12 SHEET13 SHEET14 SHEET15 SHEET16 SHEET17 SHEET18 SHEET19 SHEET20 SHEET21 SHEET22 SHEET23 SHEET24 SHEET25 SHEET26 SHEET27 SHEET28 SHEET29 SHEET30 SHEET31 SHEET32
TITLE PAGE L137 McASP/ETHERNET ETHERNET/McASP MUX L137 SERIAL I/O SPI MUXING L137 USB 2.0 PORT L137 USB 1.0 PORT L137 EMIF A L137 EMIF B L137 JTAG/CLOCKS L137 POWER PINS L137 GROUND PINS L137 DECOUPLING CAPACITORS BOOT MODE SWITCHES EMIFB SDRAM SPI ROM USER SWITCHES/LEDS RS232 INTERFACE SD/MMC MUXING SD/MMC/MMC Plus CARD INTERFACE JTAG CONNECTOR INTERFACE AIC3106 AUDIO CODEC AIC PHONE/AUDIO JACK ETHERNET PHY/SWITCH ETHERNET POWER ETHER NET PORTS EXPANSION CONNECTOR 1 EXPANSION CONNECTOR 2 EXPANSION CONNECTOR 3 POWER POWER II POWER IN
REVISION STATUS OF SHEETS DWN R.R.P. T.W.K. R.R.P. R.R.P. C.M.D. R.R.P. R.R.P.
4
REV
SH CHK A ENGR ENGR-MGR QA MFG NEXT ASSY RLSE APPLICATION USED ON 27 A 17 D A 9 10 A 7 8 B 18 19 20 A B A 28 29 30 A B B
31
32
REV
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size:B Date:

3 2
SH
21
22
23
24
25
26
OMAP-L137 EVM TITLE PAGE DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
REV
SH
11
12
13
14
15
16
REV
Revision: D Sheet 1 of 32
SH
DATE 06/01/2008 DATE 06/01/2008 DATE 12/01/2006 DATE 06/01/2008 DATE 06/01/2008 DATE 06/01/2008 DATE 06/01/2008
27 DSK_3V3
T_AMUTE0
T_AMUTE0
R1
22
R2 NO-POP
27 R3 2K U1-6 RN1
T_AFSX0
T_AFSX0
D
L4 AMUTE0__RESETOUT AXR1_0/GPIO4_0 AXR1_1/GPIO4_1 AXR1_2/GPIO4_2 AXR1_3/EQEP1A/GPIO4_3

RN3
6,27 T_ACLKX0 27 T_AFSR0 27 T_ACLKR0
T_ACLKX0 T_AFSR0 T_ACLKR0
RN2 5 6 7 8
AMUTE0 RPACK4-22 AFSX0 4 ACLKX0 3 AFSR0 2 ACLKR0 1
D5 C5 C4 B4 AFSX0/GPIO2_13/BOOT_10 ACLKX0/ECAP0/APWM0/GPIO2_12 AFSR0/GPIO3_12 ACLKR0/ECAP1/APWM1/GPIO2_15 AXR1_4/EQEP1B/GPIO4_4 AXR1_5/EPWM2B/GPIO4_5 AXR1_6/EPWM2A/GPIO4_6 AXR1_7/EPWM1B/GPIO4_7 AXR0_6/RMII_RXER/ACLKR2/GPIO3_6 AXR0_3/RMII_CRS_DV/AXR2_2/GPIO3_3 AXR0_4/RMII_RXD_0/AXR2_1/GPIO3_4 AXR0_5/RMII_RXD1/AFSX2/GPIO3_5 AXR0_2/RMII_TXEN/AXR2_3/GPIO3_2 AXR0_0/RMII_TXD0/AFSR2/GPIO3_0 AXR0_1/RMII_TXD1/ACLKX2/GPIO3_1 AHCLKR0/RMII_MHZ_50CLK/GPIO2_14/BOOT_11 AXR0_8/MDIO_D/GPIO3_8 AXR0_7/MDIO_CLK/GPIO3_7 L1 L2 L3 N2 N1 M4 M3
AXR1[4] AXR1[5] AXR1[6] AXR1[7] RN4 AXR1[8] AXR1[9] AXR1[10] AXR1[11] RN5 AHCLKR1 ACLKR1 AFSR1
T3 R2 P2 P1 4 3 2 1 4 3 2 1
AXR1[0] AXR1[1] AXR1[2] AXR1[3]
RPACK4-22 T_AXR1[0] 5 T_AXR1[1] 6 T_AXR1[2] 7 T_AXR1[3] 8 RPACK4-22 T_AXR1[4] 5 T_AXR1[5] 6 T_AXR1[6] 7 T_AXR1[7] 8
T_AXR1[1] T_AXR1[2]
27 27
3 T_AXR0[6]/RMII_RXER R5 R6 R7 22 22 RMII_RXD[0] RMII_RXD[1] 22 RMII_CRS_DV A7
T_AXR0[6]/RMII_RXER
R4
22
RMII_RXER
D7
T_AXR1[6] T_AXR1[7]
27 27
3 T_AXR0[3]/RMII_CRS_DV
T_AXR0[3]/RMII_CRS_DV
3 T_AXR0[4]/RMII_RXD[0] 3 T_AXR0[5]/RMII_RXD[1] R8 22 RMII_TXEN
T_AXR0[4]/RMII_RXD[0] T_AXR0[5]/RMII_RXD[1]
B7 C7 D8 B8 C8 A4 K2 K3 K4 D4 B5 A5
R15
AXR1_8/EPWM1A/GPIO4_8 AXR1_9/GPIO4_9 AXR1_10__GPIO5_10 AXR1_11/GPIO5_11
M2 M1 N3 T4
4 3 2 1
T_AXR1[8] T_AXR1[9] T_AXR1[10] T_AXR1[11]
27 27 27 27 T_AHCLKR1 27 T_ACLKR1 27 T_AFSR1 27
3 T_AXR0[2]/RMII_TXEN R9 R10 R11 R12 R14 22 22 RMII_MDIO_D B6 RMII_MDIO_CLK A6 22 RMII_MHZ_50 22 22 RMII_TXD[0] RMII_TXD[1]
T_AXR0[2]/RMII_TXEN
3 T_AXR0[0]/RMII_TXD[0] 3 T_AXR0[1]/RMII_TXD[1]
T_AXR0[0]/RMII_TXD[0] T_AXR0[1]/RMII_TXD[1]
AHCLKR1/GPIO4_11 ACLKR1/ECAP2/APWM2/GPIO4_12 AFSR1/GPIO4_13
4 3 2 1
AHCLKX1 ACLKX1 AFSX1 AMUTE1 0 22 R16
RPACK4-22 T_AXR1[8] 5 T_AXR1[9] 6 T_AXR1[10] 7 T_AXR1[11] 8 RPACK4-22 5 T_AHCLKR1 T_ACLKR1 6 T_AFSR1 7 8
DSK_3V3
R13 NO-POP
AHCLKX1/EPWM0B/GPIO3_14 ACLKX1/EPWM0A/GPIO3_15 AFSX1/EPWMSYNCI/EPWMSYNC0/GPIO4_10 AMUTE1/EHRPWMTZ/GPIO4_14 AHCLKX0/AHCLKX2/USB_REFCLKIN/GPIO2_11 AXR0_11/AXR2_0/GPIO3_11
4 3 2 1
RN6
5 6 7 8
T_AHCLKX1 T_ACLKX1 T_AFSX1 T_AMUTE1 RPACK4-22 T_AXR0_11/AXR2_0/GPIO3_11
T_AMUTE1
27
3 T_AHCLKR0/RMII_MHZ_50
T_AHCLKR0/RMII_MHZ_50
R17 2K
T_AXR0_11/AXR2_0/GPIO3_11 27
3 T_AXR0[8]/RMII_MDIO_D
T_AXR0[8]/RMII_MDIO_D DSK_3V3
OMAPL137ZKB C1 0.1uF
VCC_3V3
3 T_AXR0[7]/RMII_MDIO_CLK
T_AXR0[7]/RMII_MDIO_CLK
U2
16
U3 C2 0.1uF T_AXR1[3]
VCC 4 1A
DSK_3V3
Vcc
C3 .1uF
24
T_AIC_MCLK
T_AXR1[4]
7 9 12
T_AIC_BCLK
2A 3A 4A 8 GND
U4 SN74LVC1G32DCKRG4
T_AHCLKX1 T_AFSX1 T_AXR1[0] T_AXR1[5] T_ACLKX1
3 4 7 8 11 1
,4,5,8,16,19,27,31 BOOT_DISABLEn
1 4 2
DSK_3V3
1A1 1A2 1A3 1A4 1A5 1OE
1B1 1B2 1B3 1B4 1B5
2 5 6 9 10
T_AIC_MCLK 22 T_AIC_WCLK 22 T_AIC_DOUT 22 T_AIC_DIN 22 T_AIC_BCLK 22
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE
2 3 5 6 11 10 14 13 1 15
SN74CBTLV3257PW EXP_ACLKX1
EXP_AXR1[3] EXP_EQEP1A EXP_AXR1[4] EXP_EQEP1B
27 28 27 28
27 EXP1_SEL_MCASP1
R18 2K 3,4,5,8,16,19,27,31 BOOT_DISABLEn EXP_AHCLKX1 28 SEL_EXP2_QEP1
R19 2K
C4 .1uF
14 17 18 21 22 13
1 4 2 3
U5 SN74LVC1G00DCKRG4
2A1 2A2 2A3 2A4 2A5 2OE
2B1 2B2 2B3 2B4 2B5 GND
15 16 19 20 23 12
SN74CBTLV3384PW
EXP_ACLKX1 27 EXP_AXR1[5] 27 EXP_AXR1[0] 27 EXP_AFSX1 27 EXP_AHCLKX1 27
3,14,16,19,31 BOOT_DISABLE
MCLK: AHCLKX1 (drive this clock into McASP) SPECTRUM DIGITAL INCORPORATED BCLK: ACLKX1 (McASP will drive this into the AIC) WCLK: AFSX1 (McASP will drive this into the AIC) DIN: AXR1[5] (McASP) OMAP-L137 EVM Title: DOUT: AXR1[0] (McASP) Page Contents: McASP/Ethernet MAC Drive the MCLK into McASP1 Tx. McASP generates the Tx bit and frame clocks. Configure McASP such that the Rx section Size: B DWG NO 511342-0001 operates off of the Tx section clocks.
Date:
4 3 2
Revision: A Monday, Novem ber 24, 2008

1
Sheet
of
32
A-3
R20 2K DSK_3V3
1 4 2 3
SN74LVC1G02DCKR U8 C7 0.1uF C8 .01uF DSK_3V3
2,4,5,8,16,19,27,31 BOOT_DISABLEn
A-4
4 3 2 1
DSK_3V3
C5 0.1uF U6
D
1 4 2
SN74LVC1G08DCKRG4
Disconnect A1 port = B1 port A1 port = B2 port A2 port = B1 port A2 port = B2 port Disconnect A1 port = B1 port/A2 port = B2 port A1 port = B2 port/ A2 port = B1 port FUNCTION
14,27 SEL_ENETn_MCASP0
FUNCTION TABLE INPUTS INPUTS/OUTPUTS S2 S1 S0 A1 A2 L L L Z Z L L H B1 Z L H L B2 Z L H H Z B1 H L L Z B2 H L H Z Z H H L B1 B2 H H H B2 B1
C6 0.1uF U7
1 56 55 S0 S1 S2
B_RMII_MHZ_50 B_RMII_TXD[0] B_RMII_TXD[1] B_RMII_TXEN B_RMII_CRS_DV B_RMII_RXD[0] B_RMII_RXD[1] B_RMII_RXER
VCC.1
17
2 T_AHCLKR0/RMII_MHZ_50 2 T_AXR0[0]/RMII_TXD[0] 2 T_AXR0[1]/RMII_TXD[1] 2 T_AXR0[2]/RMII_TXEN 2 T_AXR0[3]/RMII_CRS_DV 2 T_AXR0[4]/RMII_RXD[0] 2 T_AXR0[5]/RMII_RXD[1] 2 T_AXR0[6]/RMII_RXER 2 T_AXR0[8]/RMII_MDIO_D 2 T_AXR0[7]/RMII_MDIO_CLK R21 360 EXP_AHCLKR0 T_AXR0[8]/RMII_MDIO_D T_AXR0[7]/RMII_MDIO_CLK T_AXR0[0]/RMII_TXD[0] T_AXR0[1]/RMII_TXD[1] T_AXR0[2]/RMII_TXEN T_AXR0[3]/RMII_CRS_DV T_AXR0[4]/RMII_RXD[0] T_AXR0[5]/RMII_RXD[1] T_AXR0[6]/RMII_RXER
T_AHCLKR0/RMII_MHZ_50
B_RMII_MHZ_50 24 B_RMII_TXD[0] 24 B_RMII_TXD[1] 24 B_RMII_TXEN 24 B_RMII_CRS_DV 24 B_RMII_RXD[0] 24 B_RMII_RXD[1] 24 B_RMII_MDIO_D 24 B_RMII_MDIO_CLK 24 EXP_AHCLKR0 27
2 4 6 9 11 13 15 18 21 23 25 27 1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
54 52 50 47 45 43 41 39 36 34 32 30
R22 1K EXP_AXR0[0] EXP_AXR0[1] EXP_AXR0[2] EXP_AXR0[3] EXP_AXR0[4] EXP_AXR0[5] EXP_AXR0[6] 27 27 27 27 27 27 27 EXP_AXR0[8] 27 EXP_AXR0[7] 27
B
EXP_AXR0[0] EXP_AXR0[1] EXP_AXR0[2] EXP_AXR0[3] EXP_AXR0[4] EXP_AXR0[5] EXP_AXR0[6] EXP_AXR0[8] EXP_AXR0[7]
3 5 7 10 12 14 16 20 22 24 26 28 1A2 2A2 3A2 4A2 5A2 6A2 7A2 8A2 9A2 10A2 11A2 12A2 GND.1 GND.2 GND.3 GND.4
SN74CBTLV16212DGGR
1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 8 19 38 49
53 51 48 46 44 42 40 37 35 33 31 29
R23 360
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date:

4 3 2
OMAP-L137 EVM Ethernet Muxes DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
Revision: B Sheet 3 of 32
14,16 BOOTMODE[2] 14,16 SPI0_CLK
14,16 BOOTMODE[3] 14,16 SPI0_ENAn RN7 5 6 7 8 RPACK4-22 4 3 2 1
14,16 BOOTMODE[0] 14,16 SPI0_SOMI
DSK_3V3
D
14,16 BOOTMODE[1] 14,16 SPI0_SIMO
DSK_3V3
R24 20K U1-9 R27 R28 NO-POP 22
R25 20K
R26 20K
16 SPI0_SCSn
UART1_TXD/AXR0_10/GPIO3_10 UART1_RXD/AXR0_9/GPIO3_9 UART0_TXD/I2C0_SCL/TM64P0_OUT12/GPIO5_9/BOOT_9 UART0_RXD/I2C0_SDA/TM64P0_IN12/GPIO5_8/BOOT_8 P3 R3 C6
D6
R29 R30 R31 R32
22 22 22 22
AXR0_10 AXR0_9 UART0_TXD_I2C0_SCL UART0_RXD_I2C0_SDA
T5 R5 R6 P6 N4 SPI0_CLK/EQEP1I/GPIO5_2/BOOT_2 SPI0_ENAn/UART0_CTSn/EQEP0A/GPIO5_3/BOOT_3 SPI0_SOMI/EQEP0I/GPIO5_0/BOOT_0 SPI0_SIMO/EQEP0S/GPIO5_1/BOOT_1 SPI0_SCSn/UART0_RTSn/EQEP0B/GPIO5_4/BOOT_4
5,14 BOOTMODE[7] 5,14 SPI1_CLK RN8 5 6 7 8 RPACK4-22 4 3 2 1
5 T_SPI1_ENAn
T_SPI1_ENAn
DSK_3V3
T6 R4 P5 N5 P4 SPI1_CLK/EQEP1S/GPIO5_7/BOOT_7 SPI1_ENAn/UART2_RXD/GPIO5_12 SPI1_SOMI/I2C1_SCL/GPIO5_5/BOOT_5 SPI1_SIMO/I2C1_SDA/GPIO5_6/BOOT_6 SPI1_SCSn/UART2_TXD/GPIO5_13
R33 NO-POP
R34 NO-POP
C
R35 20K
SPI1_SOMI
DSK_3V3 R36 NO-POP OMAPL137ZKB R37 20K
5 SPI1_SIMO
R38 NO-POP
DSK_3V3 R39 VCC_3V3 VCC_3V3 C10 U9 R40 2.2K 0.1uF U10 R41 2.2K 22
DSK_3V3
DSK_3V3
DSK_3V3
5 T_SPI1_SCSn
T_SPI1_SCSn
C9
R42 2.2K
R43 2.2K
0.1uF
16 VCC 1A 2A 3A 4A 1 15
AXR0_9
16
UART0_TXD_I2C0_SCL UART0_RXD_I2C0_SDA
4 7 9 12 8
VCC 4 7 9 12
R45 360
AXR0_10
EXP_AXR0_9 27 EXP2_UART1_RXD 28 EXP_AXR0_10 27 EXP2_UART1_TXD 28
1A 2A 3A 4A 8 GND
R44 360
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
2 3 5 6 11 10 14 13
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE
2 3 5 6 11 10 14 13 1 15
SN74CBTLV3257PW
I2C0_SCL 16,22,24,27,28,30 EXP2_TMP64P0_OUT12 28 I2C0_SDA 16,22,24,27,28,30 EXP2_TMP64P0_IN12 28
S GND OE SN74CBTLV3257PW
2,3,5,8,16,19,27,31 BOOT_DISABLEn 2,3,5,8,16,19,27,31 BOOT_DISABLEn 14,28 SEL_EXP2_TIMER R47 2K Title: Page Contents: Size: B Date:
4 3 2
SPECTRUM DIGITAL INCORPORATED OMAP-L137 EVM Serial I/O DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
14,28 SEL_EXP2_UART1
R46 2K
Revision: A Sheet 4 of 32
A-5
A-6
4 3 2 1
VCC_3V3 C11 0.1uF U11
16 VCC 1A 2A 3A 4A GND
R49 2K 4,14 SPI1_CLK 4 SPI1_SIMO 4 SPI1_SOMI
4 7 9 12
R48 360
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE 1 15
2 3 5 6 11 10 14 13
EXP1_SPI1_CLK 27 EXP2_SPI1_CLK 28 EXP1_SPI1_SIMO 27 EXP2_SPI1_SIMO 28 EXP_SPI1_SOMI 27 EXP2_SPI1_SOMI 28
8
SN74CBTLV3257PW
2,3,4,8,16,19,27,31 BOOT_DISABLEn 28 SEL_SPI1_EXP2_B
U12 4 T_SPI1_SCSn T_SPI1_SCSn
7 1A 1B1 1B2 1B3 1B4

UART2_RXD 18 EXP1_SPI1_ENAn 27 EXP2_SPI1_ENAn 28 UART2_TXD 18 EXP1_SPI1_SCSn 27 EXP2_SPI1_SCSn 28
6 5 4 3
4 T_SPI1_ENAn
T_SPI1_ENAn
9 2A
VCC_3V3 C12 0.1uF
2B1 2B2 2B3 2B4 S0 S1 10E 2OE

R50 2K R51 2K
10 11 12 13
16 VIN GND 1 15 8
14 2
74CBTLV3253 2,3,4,8,16,19,27,31 BOOT_DISABLEn 27 SEL_SPI1_EXP1 28 SEL_SPI1_EXP2

4 3 2
OMAP-L137 EVM SPI MUXING DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
TP1 VBUS DSK_3V3 U13 VCC_5V
C266 .1uF
2 3 IN1 IN2
J1
+
EN
OCn
2,27 T_ACLKX0 10uF
4 GND
DSK_3V3
2 1 2
HEADER 2
+
+C13
1
C14 6.8uF R52 100K TPS2065D
OUT1 OUT2 OUT3

C15 0.1uF
8 7 6
L1
BLM21PG221SN1
3 1
U59 74CBTLV1G125CRG4 R53 10K
THESE FOOTPRINTS ARE OVERLAYED ONLY 1 OF 3 IS POPULATED AT 1 TIME
DSK_3V3 ON_BD_OFF_BD 8,14 R54 NO-POP TP2 VBUS_OCn2
C16 100uF
PTP7
CPU_3V3
J2B
HEADER 2
1B
C17 0.001uF R56 10K C18 0.1uF C19 0.01uF C20 1uF
SHIELD1 ATTACH 2B 3B 4B DD+ GND SHIELD2

USB-micro/A/B connector
FULL SIZE B CONNECTOR
USB_SHIELD
0.02
R55
E1 NFM21PC474R1C3D 1
L593 BLM18AG121SN1D U1-7
USB_ SHIELD
CPU_1V8
PTP8
2 H5 USB0_VDDA33 USB0_DRVVBUS/GPIO4_15 USB0_VSSA33 USB0_DM E3 USB0_VDDA18 USB0_ID USB0_VSSA USB0_VDDA12 D2 USB0_DP F3 C3 F4 G4

USB0_DM USB0_DP
2 USB0_VBUS E4 D3
J2A
Differential Pair
HEADER 2
0.02
R57
E2 NFM21PC474R1C3D 1
H4
1AB 2AB 3AB 4AB 5AB
VBUS DD+ ID GND SHIELD5 SHIELD6 SHIELD7 SHIELD8 MH1 MH2 5 6 7 8 9 10

MICRO A-B CONNECTOR
C21 0.001uF L594 BLM18AG121SN1D
C22 0.1uF
C23 0.01uF
C24 1uF
OMAPL137ZKB C26 NO-POP C27 .22uF
C264 0.1uF U55 USB_SHIELD
3
R59 NO-POP R58 NO-POP
VCC
DSK_3V3
IO1 2 NC.2 GND
IO2
5
J2C
3 1A 2A 3A 4
TPD2E001DRL
SHIELD3 VBUS-A DD+ 4A GND SHIELD4
USB_SHIELD
4
FULL SIZE A CONNECTOR
USB_SHIELD
R391 C270
1M .1uF

4 3 2
OMAP-L137 EVM PRIMUS USB 2.0 INTERFACE DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
Revision: B Sheet 6 of 32
A-7
EN
OCn
C35 0.001uF
C36 0.1uF
C37 0.01uF
C38 1uF
3 2
VCC
GND
A-8
4 3 2 1
TP4 VBUS VCC_5V U14 TPS2065D
2 3 IN1 IN2 GND

C29 100uF DSK_3V3
+ +C28
1
R60 100K
OUT1 OUT2 OUT3

C30 0.1uF
8 7 6
10uF
R62 10K TP5
R61 10K
8 ON_BD_USB_DRV VBUS_OCn1
8 ON_BD_USB_OVC
C
Differential Route 90 ohms
PTP9
2
R120 15K U1-8 C31 0.001uF C32 0.1uF C33 0.01uF C34 1uF
CPU_3V3 R63 E3 NFM21PC474R1C3D 3 1
HEADER 2
0.02
J3 USB1_SH
6
USB_DM USB_DP
C1 USB1_VDDA33 USB1_VDDA18 USB1_DM USB1_DP B3 A3

R223 R375
S1
C2 1
OMAPL137ZKB R393 15K
24.9 1% 24.9 1%
PTP10
1 2 3 4 5
VBUS DD+ GND S2

USB-A connector USB1_SH C263 0.1uF C271 R392 .1uF 1M
B
CPU_1V8
HEADER 2 R64
0.02
E4 NFM21PC474R1C3D 3 1
IO1 NC.2
IO2
5
U56 TPD2E001DRL

4 3 2
OMAP-L137 EVM USB 1.0 HOST INTERFACE DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
DSK_3V3
R65 10K U1-3
29 EMIFA_WAIT0
R66
22
N6 EMA_WAIT0/UHPIHRDYn/GPIO2_10
EMA_BA0/LCD_D4/GPIO1_14 EMA_BA1/LCD_D5/UHPI_HHWIL/GPIO1_13
RN9
R8 P8
DC_3V3 R68 NO-POP RN10 RPACK8-22
R67 20K
EMA_A0/LCD_D7/GPIO1_0 EMA_A1/MMCSD_CLK/UHPI_HCNTL0/GPIO1_1 EMA_A2/MMCSD_CMD/UHPI_HCNTL1/GPIO1_2 EMA_A3/LCD_D6/GPIO1_3 EMA_A4/LCD_D3/GPIO1_4 EMA_A5/LCD_D2/GPIO1_5 T13 R15 R13 P15 P13 N15 N13 M15 EMA_D0/MMCSD_DAT0/UHPI_HD0/GPIO00/BOOT_12 EMA_D1/MMCSD_DAT1/UHPI_HD1/GPIO0_1 EMA_D2/MMCSD_DAT2/UHPI_HD2/GPIO0_2 EMA_D3/MMCSD_DAT3/UHPI_HD3/GPIO0_3 EMA_D4/MMCSD_DAT4/UHPI_HD4/GPIO0_4 EMA_D5/MMCSD_DAT5/UHPI_HD5/GPIO0_5 EMA_D6/MMCSD_DAT6/UHPI_HD6/GPIO0_6 EMA_D7/MMCSD_DAT7/UHPI_HD7/GPIO0_7/BOOT_13 EMA_A6/LCD_D1/GPIO1_6 EMA_A7/LCD_D0/GPIO1_7 EMA_A8/LCD_PCLK/GPIO1_8 EMA_A9/LCD_HSYNC/GPIO1_9 EMA_A10/LCD_VSYNC/GPIO1_10 EMA_A11/LCD_ACn/ENB_CSn/GPIO1_11 EMA_A12/LCD_MCLK/GPIO1_12 P10 N10 T11 R11 N8 P11 N11
RN11 8 7 6 5 4 3 2 1 R69 R72 22 DC_3V3
T9 R9 P9 N9 T10 R10
8 7 6 5 4 3 2 1
RPACK8-22 9 10 11 12 13 14 15 16
EMIFA_BA0 29 EMIFA_BA1 29 EMIFA_A0 29 EMIFA_A1 19 EMIFA_A2 19 EMIFA_A3 29 EMIFA_A4 29 EMIFA_A5 29 RPACK8-22 9 10 11 12 13 14 15 16 22 EMIFA_CS0n DSK_3V3 C39 .1uF R73 20K EMIFA_A6 EMIFA_A7 EMIFA_A8 EMIFA_A9 EMIFA_A10 EMIFA_A11 EMIFA_A12 29 29 29 29 29 29 29
19 19 19 19 19 19 19 19
EMIFA_D0 EMIFA_D1 EMIFA_D2 EMIFA_D3 EMIFA_D4 EMIFA_D5 EMIFA_D6 EMIFA_D7
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
DC_3V3
R70 20K
R71 NO-POP
EMA_CS0n/UHPIHASn/GPIO2_4 EMA_CS2n/UHPI_HCSn/GPIO2_5/BOOT_15 EMA_CS3n/AMUTE2/GPIO2_6 EMA_CASn/EMA_CS4n/GPIO2_1 EMA_RASn/EMA_CS5n/GPIO2_2 EMA_CLK/OBSCLK/AHCLKR2/GPIO1_15 EMA_SDCKE/GPIO2_0 EMA_OEn/UHPI_HDS1n/AXR0_13/GPIO2_7 EMA_WE/UHPI_HRWn/AXR0_12/GPIO2_3/BOOT_14 EMA_WE_DQM0n/UHPI_HINTn/AXR0_15/GPIO2_9 EMA_WE_DQM1n/UHPI_HDS2n/AXR0_14/GPIO2_8 R12 T12 R7 M13 M14 P12
T8 P7 T7 L16 N7
2
R74 NO-POP
EMIFA_CS2n 29
1 2 3 4 5 6 7 8 N12 T14 R14 P16 P14 N16 N14 M16 EMA_D8/UHPI_HD8/LCD_D8/GPIO0_8 EMA_D9/UHPI_HD9/LCD_D9/GPIO0_9 EMA_D10/UHPI_HD_10/LCD_D10/GPIO0_10 EMA_D11/UHPI_HD11/LCD_D11/GPIO0_11 EMA_D12/UHPI_HD12/LCD_D12/GPIO0_12 EMA_D13/UHPI_HD13/LCD_D13/GPIO0_13 EMA_D14/UHPI_HD14/LCD_D14/GPIO0_14 EMA_D15/UHPI_HD15/LCD_D15/GPIO0_15
RN12 RPACK8-22
16 15 14 13 12 11 10 9
2,3,4,5,16,19,27,31 BOOT_DISABLEn R75 R76 R77 22 22 22 R78 22 R79 22 R80 22 EMIFA_OEn DC_3V3
B
EMIFA_CS3n EMIFA_CS4n 19 EMIFA_CS5n 19 EMIFA_CLK EMIFA_SDCKE 29
OMAPL137ZKB VCC_3V3 C41 U16 0.1uF U17
VCC_3V3
C40
0.1uF
16 VCC 1A 2A 3A 4A GND S OE 1 15
29 29 29 29 EMIFA_OEn EMIFA_WEn EMIFA_WEn_DQM1 EMIFA_WEn_DQM0
VCC 4 7 9 12 8
R83 2K 29 EXP3_SEL_MEM U19 EMIFA_CLK SN74CBTLV3257PW
16
EMIFA_D8
1A
EMIFA_D9
2A
1 3
R82 22 EMIFA_WEn R86 R87 22 22 EMIFA_WEn_DQM0 EMIFA_WEn_DQM1 U58
U15 SN74CBTLV1G125
EMIFA_D10
3A
R81 20K VCC_3V3 C265 0.1uF R84 2K R85 NO-POP
EMIFA_D11
12 1 15
4A S OE
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
2 3 5 6 11 10 14 13
USER_SW1 17 EXP_EMIFA_D8 USER_SW2 17 EXP_EMIFA_D9 USER_SW3 17 EXP_EMIFA_D10 USER_SW4 17 EXP_EMIFA_D11
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
2 3 5 6 11 10 14 13
EXP1_AXR0_15 27 EXP3_EMIFA_WEn_DQM0 29 EXP1_AXR0_14 27 EXP3_EMIFA_WEn_DQM1 29 EXP1_AXR0_12 27 EXP3_EMIFA_WEn 29 EXP1_AXR0_13 27 EXP3_EMIFA_OEn 29
GND
SN74CBTLV3257PW
16
EMIFA_CS3n
VCC 4 7 9
ON_BD_USB_DRV 7 AHCLKR2 27 R152 360 EXP3_EMIFA_CLK 29 ON_BD_USB_OVC 7
1A 2A 3A 12 8 4A GND
EXP_EMIFA_CS0n 29
EXP1_AMUTE2 27 EXP3_EMIFA_CS3n 29
VCC_3V3 14,29 EXP3_SEL_MEMD8_D11
C42
7 1A 1B1 1B2 1B3 1B4
U18
0.1uF 29 EMIFA_CS0n
16 9
VCC 2A
EMIFA_D12 29 29 29 C43 R88 0.1uF 2K VCC_3V3
6 5 4 3
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE

SN74CBTLV3257PW
2 3 5 6 11 10 14 13 1 15 10 11 12 13 2B1 2B2 2B3 2B4
1A
EMIFA_D13
2A
EMIFA_D14
3A
SPECTRUM DIGITAL INCORPORATED 29 EXP3_SEL_MEM_CTL ON_BD_OFF_BD 6,14
EMIFA_D15
12 1 15
4A S OE
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
2 3 5 6 11 10 14 13
USER_LED1 17 EXP_EMIFA_D12 USER_LED2 17 EXP_EMIFA_D13 USER_LED3 17 EXP_EMIFA_D14 USER_LED4 17 EXP_EMIFA_D15
10E 2OE 16 8 VIN GND

74CBTLV3253
1 15 S0 S1 14 2
R384 2K
EXP3_SEL_MEM_CTL2 29 R89 2K
Title: Page Contents: Size: B Date:
OMAP-L137 EVM CPU EMIF A DWG NO 511342-0001 Monday, Novem ber 24, 2008 Sheet 8 of Revision: B 32
GND
SN74CBTLV3257PW
14,29 EXP3_SEL_MEMD12_D15
4
A-9
A-10
4 3 2 1
U1-4 RN13 EMIFB_D0 EMIFB_D1 EMIFB_D2 EMIFB_D3 EMIFB_D4 EMIFB_D5 EMIFB_D6 EMIFB_D7
15 15 15 15 15 15 15 15
EMIFB_D0 EMIFB_D1 EMIFB_D2 EMIFB_D3 EMIFB_D4 EMIFB_D5 EMIFB_D6 EMIFB_D7
1 2 3 4 5 6 7 8 EMB_D0/GPIO6_0 EMB_D1/GPIO6_1 EMB_D2/GPIO6_2 EMB_D3/GPIO6_3 EMB_D4/GPIO6_4 EMB_D5/GPIO6_5 EMB_D6/GPIO6_6 EMB_D7/GPIO6_7 EMB_A0/GPIO7_2 EMB_A1/GPIO7_3 EMB_A2/GPIO7_4 EMB_A3/GPIO7_5 EMB_A4/GPIO7_6 EMB_A5/GPIO7_7 EMB_A6/GPIO7_8 EMB_A7/GPIO7_9
CPU_EMIFB_A10 CPU_EMIFB_A7 CPU_EMIFB_A6 CPU_EMIFB_A11 CPU_EMIFB_A12 CPU_EMIFB_A9 CPU_EMIFB_A8
RPACK8-10 16 15 14 13 12 11 10 9
F16 G13 G16 H13 H16 J13 J15 J16 EMB_BA0/GPIO7_1 EMB_BA1/GPIO7_0 D10 C10 B10 A10 D11 C11 B11 A11 16 15 14 13 12 11 10 9
RPACK8-22 RN16 DSK_3V3 CPU_EMIFB_A0 CPU_EMIFB_A1 CPU_EMIFB_A2 CPU_EMIFB_A3 CPU_EMIFB_A4 CPU_EMIFB_A5 CPU_EMIFB_A6 CPU_EMIFB_A7 CPU_EMIFB_A8 CPU_EMIFB_A9 CPU_EMIFB_A10 CPU_EMIFB_A11 CPU_EMIFB_A12
C9 B9
CPU_EMIFB_BA0 CPU_EMIFB_BA1
RPACK8-22 CPU_EMIFB_A5 9 CPU_EMIFB_A4 10 CPU_EMIFB_A0 11 CPU_EMIFB_A1 12 CPU_EMIFB_A2 13 CPU_EMIFB_A3 14 CPU_EMIFB_BA0 15 CPU_EMIFB_BA1 16 EMIFB_A5 15 EMIFB_A4 15 EMIFB_A0 15 EMIFB_A1 15 EMIFB_A2 15 EMIFB_A3 15 EMIFB_BA0 15 EMIFB_BA1 15 EMIFB_A10 15 EMIFB_A7 15 EMIFB_A6 15 EMIFB_A11 15 EMIFB_A12 15 EMIFB_A9 15 EMIFB_A8 15
RN14 EMIFB_A5 8 EMIFB_A4 7 EMIFB_A0 6 EMIFB_A1 5 EMIFB_A2 4 EMIFB_A3 3 EMIFB_BA0 2 EMIFB_BA1 1
15 EMIFB_D8 15 EMIFB_D9 15 EMIFB_D10 15 EMIFB_D11 15 EMIFB_D12 15 EMIFB_D13 15 EMIFB_D14 15 EMIFB_D15
RN15 EMIFB_D8 EMIFB_D9 EMIFB_D10 EMIFB_D11 EMIFB_D12 EMIFB_D13 EMIFB_D14 EMIFB_D15
1 2 3 4 5 6 7 8 EMB_D8/GPIO6_8 EMB_D9/GPIO6_9 EMB_D10/GPIO6_10 EMB_D11/GPIO6_11 EMB_D12/GPIO6_12 EMB_D13/GPIO6_13 EMB_D14/GPIO6_14 EMB_D15/GPIO6_15 EMB_A8/GPIO7_10 EMB_A9/GPIO7_11 EMB_A10/GPIO7_12 EMB_A11/GPIO7_13 EMB_A12/GPIO3_13 D12 C12 A9 B12 B15
RPACK8-10
RPACK8-10 16 15 14 13 12 11 10 9
C16 D13 D14 D15 D16 E13 E16 F13
1 2 3 4 5 6 7 8
EMIFB_A10 EMIFB_A7 EMIFB_A6 EMIFB_A11 EMIFB_A12 EMIFB_A9 EMIFB_A8
RN17
15 EMIFB_D16 15 EMIFB_D17 15 EMIFB_D18 15 EMIFB_D19 15 EMIFB_D20 15 EMIFB_D21 15 EMIFB_D22 15 EMIFB_D23 R621 10K R622 10K
R623 10K
R624 10K
R625 10K
1 2 3 4 5 6 7 8 G15 H14 H15 J14 K13 K16 L14 L15 EMB_D16 EMB_D17 EMB_D18 EMB_D19 EMB_D20 EMB_D21 EMB_D22 EMB_D23 EMB_SDCKE EMB_CLK EMB_CS0n EMB_CASn EMB_RASn A8
R94
16 15 14 13 12 11 10 9 C13 C14 D9 L13

R93 22 22 R92 22 R91 22 R90 22 RPACK8-10
EMIFB_SDCKE 15 EMIFB_CLK 15 EMIFB_CS0n 15 EMIFB_CASn 15 EMIFB_RASn 15 DSK_3V3
RN18 EMIFB_D24 EMIFB_D25 EMIFB_D26 EMIFB_D27 EMIFB_D28 EMIFB_D29 EMIFB_D30 EMIFB_D31
15 EMIFB_D24 15 EMIFB_D25 15 EMIFB_D26 15 EMIFB_D27 15 EMIFB_D28 15 EMIFB_D29 15 EMIFB_D30 15 EMIFB_D31
1 2 3 4 5 6 7 8 EMB_D24 EMB_D25 EMB_D26 EMB_D27 EMB_D28 EMB_D29 EMB_D30 EMB_D31
16 15 14 13 12 11 10 9
A13 B14 A14 E14 E15 F14 F15 G14
R626 10K R95 R96 R97 R98 R99 22 22 22 22 22
R627 10K
R628 10K
R629 10K
R630 10K
B
EMB_WE_DQM0n/GPIO5_15 EMB_WE_DQM1n/GPIO5_14 EMB_WE_DQM2n EMB_WE_DQM3n EMB_WEn K15 A12 B13 C15
K14
EMIFB_WEn_DQM0 15 EMIFB_WEn_DQM1 15 EMIFB_WEn_DQM2 15 EMIFB_WEn_DQM3 15 EMIFB_WEn 15
OMAPL137ZKB

4 3 2
OMAP-L137 EVM CPU EMIF-B DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
CPU_RTC_1V8 D21 MMBD4148
3
+
1 0.02
R100
C44 0.1uF SD Gold Panasonic supercap DSK_3V3
C45 0.01uF
C607 .33F
R101 10K U1-5
14,31 CPU_RESET
RTC_CVDD
18 pF C46 R102 NO-POP
G1 H1
R103 NO-POP 18 pF R104 0 C47 R105 NO-POP
RTC_XI G3 RESET RTC_XO H2 G2
Y1 32KHZ
21 DSP_TMS
DSP_TMS
J1 TMS TDI TDO TRST OSCIN TCK RTCK/GPIO7_14 EMU_0/GPIO7_15 OSCOUT OSCVSS E2 F1
R108 R106 NO-POP 18 pF
RTC_VSS
21 DSP_TDO
DSP_TDI
DSP_TDI
J2 J3 J4 F2 H3 K1 J5
21 DSP_TDO DSP_TRST#
C48
21 DSP_TRST#
21 DSP_TCK
Y2 24MHz
R107 100 C50 22pF OMAPL137ZKB
18 pF 0
C49 R109 NO-POP
21 DSP_EMU0 21 DSP_EMU1 DSK_3V3 DSK_3V3 C51 0.1uF
1
33
21 DSP_RTCK U20
R112
4 2 3
DSP_EMU1
R110 10K SW1
R111 10K
SN74LVC1G32
1 2 3
4 5 6
CASD20TB R113 2.2K
DSP_EMU0
SPECTRUM DIGITAL INCORPORATED R114 2.2K Title: Page Contents: Size: B Date: OMAP-L137 EVM CPU JTAG/CLOCKS DWG NO 511342-0001 Monday, Novem ber 24, 2008 Sheet 10 o f Revision: A 32
A-11
A-12
4 3 2 1
PTP6 DVDD CVDD
1 1
HEADER 2 CPU_1V2 0.025 R116
CPU_3V3 U1-2 0.025 R115
PTP1
2 2
HEADER 2 PTP5
1 1
2
CPU_1V2 NO-POP
HEADER 2 R117
CVDD.1 CVDD.2 CVDD.3 CVDD.4 CVDD.5 CVDD.6 CVDD.7 CVDD.8 CVDD.9 CVDD.10 CVDD.11 CVDD.12 CVDD.13 CVDD.14 CVDD.15 CVDD.16 CVDD.17 CVDD.18 RVDD.1 RVDD.2
C52 1uF C53 0.01uF C54 0.1uF C55 0.001uF
L6 K6 K7 K10 K11 J6 J7 J10 J11 J12 H7 H10 H11 G6 G7 G10 G11 F6 H6 H12
R118 0.02
R1 R16 M5 M8 M9 M12 L5 L11 L12 K5 K12 G5 G12 F5 F11 F12 E5 E8 E9 E12 B16 DVDD.1 DVDD.2 DVDD.3 DVDD.4 DVDD.5 DVDD.6 DVDD.7 DVDD.8 DVDD.9 DVDD.10 DVDD.11 DVDD.12 DVDD.13 DVDD.14 DVDD.15 DVDD.16 DVDD.17 DVDD.18 DVDD.19 DVDD.20 DVDD.21
PTP4
ALT_CPU_1V2
1 PLL0_VDDA D1
2
HEADER 2 ALT_CPU_1V2
PLL0_VSSA
E1
L24 0.02 BLMG1P500SPT R119 PTP3 C272 0.01uF
CPU_1V2
C56 0.1uF
1
L25 BLMG1P500SPT
2
HEADER 2
B1 RSV2 RSV1
C57 0.1uF OMAPL137ZKB C58 0.01uF
F7
TP6 TEST POINT

4 3 2
OMAP-L137 EVM CPU POWER PINS DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
Revision: C Sheet 11 o f 32
U1-1
H8 H9 G8 G9 F8 F9 F10 E6 E7 E10 E11 B2 A1 A2 A15 A16 VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSS.6 VSS.7 VSS.8 VSS.9 VSS.10 VSS.11 VSS.12 VSS.13 VSS.14 VSS.15 VSS.16 VSS.17 VSS.18 VSS.19 VSS.20 VSS.21 VSS.22 VSS.23 VSS.24 VSS.25 VSS.26 VSS.27 VSS.28 VSS.29 VSS.30 VSS.31 VSS.32
K8 K9 J8 J9 L7 L8 L9 L10 M6 M7 M10 M11 T1 T2 T15 T16
OMAPL137ZKB

4 3 2
OMAP-L137 EVM L137 GROUND PINS DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
Revision: A Sheet 12 o f 32
A-13
A-14
4 3 2 1
CVDD
C59 0.1uF
C60 0.1uF
C61 0.1uF
C62 0.1uF
C63 0.1uF
C64 0.1uF
C65 0.1uF
C66 0.1uF
C67 0.1uF
C68 0.1uF
CVDD CVDD
C73 0.1uF
C74 0.1uF
C75 0.1uF
C76 0.1uF
C77 0.1uF
C69 33uF
C70 33uF
C71 33uF
C72 33uF
DVDD
C78 0.1uF
C79 0.1uF
C80 0.1uF
C81 0.1uF
C82 0.1uF
C83 0.1uF
C84 0.1uF
C85 0.1uF
C86 0.1uF
C87 0.1uF
DVDD
B
C88 0.1uF
C89 0.1uF
C90 0.1uF
C91 0.1uF
C92 0.1uF
C93 0.1uF
C94 0.1uF
C95 0.1uF
C96 0.1uF
C97 0.1uF
DVDD
DVDD
C98 0.1uF
C99 0.1uF
C100 33uF
C101 33uF
C102 33uF
C103 33uF

4 3 2
OMAP-L137 EVM L137 DECOUPLING CAPACITORS DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
DSK_3V3 SW2
1 2 3 4 5 6
R121 R122 R123 R125 R126
2K 2K 2K 2K 2K
1 2 3 4 5 6
DSK_3V3 DIP_SWITCH_6
12 11 10 9 8 7
BOOTMODE[7] BOOTMODE[2] BOOTMODE[1] BOOTMODE[0] BOOTMODE[3]
4,5 4,16 4,16 4,16 4,16
C273 0.1uF R127 R128 R129 R124 R130
4
SN74LVC1G125 U60
20K
20K
20K
20K
DSK_3V3
C
C274 0.1uF
U61
1 4 2 3
1G08
10,31 CPU_RESET
20K
1 3
IMPLEMENTED IMPLEMENTED IMPLEMENTED IMPLEMENTED
DSK_3V3 SW5
1 2 3 4 5 6
BOOTMODE0 BOOTMODE1 BOOTMODE2 BOOTMODE3 BOOTMODE4 BOOTMODE5 BOOTMODE6 BOOTMODE7
INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL
PD PD PD PU PU PU PU PD
IMPLEMENTED
DONE DONE DONE
R376 R377 R378 R379 R385 R386
100 100 100 100 100 100
1 2 3 4 5 6
DIP_SWITCH_6
12 11 10 9 8 7
SEL_ENETn_MCASP0 3,27 SEL_EXP2_TIMER 4,28 SEL_EXP2_UART1 4,28 ON_BD_OFF_BD 6,8 EXP3_SEL_MEMD8_D11 8,29 EXP3_SEL_MEMD12_D15 8,29
BOOTMODE8 BOOTMODE9 BOOTMODE10 BOOTMODE11 BOOTMODE12 BOOTMODE13 BOOTMODE14 BOOTMODE15
INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL
PU PU PD PD PU PU PU PU
DONE DONE DONE DONE DONE DONE DONE DONE

4 3 2
OMAP-L137 EVM BOOT MODES DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
Revision: D Sheet 14 o f 32
A-15
A-16
4 3 2 1
U21 RN19 RN20 EMIFB_D15 EMIFB_D14 EMIFB_D13 EMIFB_D12 EMIFB_D11 EMIFB_D10 EMIFB_D9 EMIFB_D8 9 9 9 9 9 9 9 9
U22
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8

RN21 RPACK8-10
9 EMIFB_A0 9 EMIFB_A1 9 EMIFB_A2 9 EMIFB_A3 9 EMIFB_A4 9 EMIFB_A5 9 EMIFB_A6 9 EMIFB_A7 9 EMIFB_A8 9 EMIFB_A9 9 EMIFB_A10 9 EMIFB_A11 9 EMIFB_A12
EMIFB_A0 EMIFB_A1 EMIFB_A2 EMIFB_A3 EMIFB_A4 EMIFB_A5 EMIFB_A6 EMIFB_A7 EMIFB_A8 EMIFB_A9 EMIFB_A10 EMIFB_A11 EMIFB_A12
H7 H8 J8 J7 J3 J2 H3 H2 H1 G3 H9 G2 G1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 DQMH DQML

RN22 EMIFB_WEn_DQM3 EMIFB_WEn_DQM2
A2 B1 B2 C1 C2 D1 D2 E1 1 2 3 4 5 6 7 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 DQMH DQML

RPACK8-10
RPACK8-10 16 15 14 13 12 11 10 9 EMIFB_A0 EMIFB_A1 EMIFB_A2 EMIFB_A3 EMIFB_A4 EMIFB_A5 EMIFB_A6 EMIFB_A7 EMIFB_A8 EMIFB_A9 EMIFB_A10 EMIFB_A11 EMIFB_A12
H7 H8 J8 J7 J3 J2 H3 H2 H1 G3 H9 G2 G1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 1 2 3 4 5 6 7 8

EMIFB_D31 EMIFB_D30 EMIFB_D29 EMIFB_D28 EMIFB_D27 EMIFB_D26 EMIFB_D25 EMIFB_D24 9 9 9 9 9 9 9 9
A2 B1 B2 C1 C2 D1 D2 E1
RPACK8-10 16 15 14 13 12 11 10 9
9 EMIFB_BA0 9 EMIFB_BA1
EMIFB_BA0 EMIFB_BA1
G7 G8 F1 E8 E2 NC
EMIFB_SDCKE EMIFB_WEn EMIFB_CASn EMIFB_RASn
9 EMIFB_WEn_DQM1 9 EMIFB_WEn_DQM0
EMIFB_WEn_DQM1 EMIFB_WEn_DQM0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

EMIFB_BA0 EMIFB_BA1
E9 D8 D9 C8 C9 B8 B9 A8 G7 G8 F1 E8 E2
EMIFB_D7 9 EMIFB_D6 9 EMIFB_D5 9 EMIFB_D4 9 EMIFB_D3 9 EMIFB_D2 9 EMIFB_D1 9 EMIFB_D0 9 9 EMIFB_WEn_DQM3 9 EMIFB_WEn_DQM2
1 2 3 4 5 6 7 8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 E9 D8 D9 C8 C9 B8 B9 A8
16 15 14 13 12 11 10 9
M_EMIFB_D23 M_EMIFB_D22 M_EMIFB_D21 M_EMIFB_D20 M_EMIFB_D19 M_EMIFB_D18 M_EMIFB_D17 M_EMIFB_D16
NC
EMIFB_SDCKE EMIFB_WEn EMIFB_CASn EMIFB_RASn
9 EMIFB_SDCKE 9 EMIFB_WEn 9 EMIFB_CASn 9 EMIFB_RASn
F3 F9 F7 F8 CKE WE CAS RAS CS

EMIFB_CS0n
F3 F9 F7 F8 CKE WE CAS RAS CS G9
9 EMIFB_CS0n
EMIFB_CS0n
G9
M_EMIFB_D23 M_EMIFB_D21 M_EMIFB_D22 M_EMIFB_D19 M_EMIFB_D20 M_EMIFB_D17 M_EMIFB_D18 M_EMIFB_D16
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
9 9 9 9 9 9 9 9
9 EMIFB_CLK
EMIFB_CLK
F2 CLK
DSK_3V3
EMIFB_CLK
F2 CLK
DSK_3V3
A9 E7 J9 A7 B3 C7 D3 VDD.1 VDD.2 VDD.3 VDDQ.1 VDDQ.2 VDDQ.3 VDDQ.4

IS42S16160B-6BL C106 22 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C107 C108 C109
+ C104
VSS.1 VSS.2 VSS.3 VSSQ.1 VSSQ.2 VSSQ.3 VSSQ.4

IS42S16160B-6BL C110 C111 C112 C113
+ C105
A1 E3 J1 A3 B7 C3 D7 VDD.1 VDD.2 VDD.3 VDDQ.1 VDDQ.2 VDDQ.3 VDDQ.4 VSS.1 VSS.2 VSS.3 VSSQ.1 VSSQ.2 VSSQ.3 VSSQ.4
A9 E7 J9 A7 B3 C7 D3
A1 E3 J1 A3 B7 C3 D7
22 uF
C116 22 uF 0.1uF 0.1uF 0.1uF
C117
C118
+ C114
C119 0.1uF
C120 0.1uF
C121 0.1uF
+ C115
22 uF

4 3 2
OMAP-L137 EVM SDRAM - EMIF B DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
DSK_3V3
R131 10K DSK_3V3 U23 SPI_HOLD
1 HOLD VCC NC.3 NC.4 NC.5 NC.6 CS DO

W25X32VSFIG
SCLK DIO NC.14 NC.13 NC.12 NC.11 GND WP 9

SPI_WP 10K R132
16 15 14 13 12 11 10
DSK_3V3 ROM_SPI0_SIMO
ROM_SPI0_CLK
D
2
C122
3 4 5 6
ROM_SPI0_CS0
0.1uF
7 8
ROM_SPI0_SOMI
DSK_3V3
C
DSK_3V3
R133 10K
R134 10K
R135 10K
R136 10K
DSK_3V3 U24
C123 0.1uF
Vcc
C124 .1uF
24
ROM_SPI0_CLK ROM_SPI0_SOMI ROM_SPI0_SIMO ROM_SPI0_CS0
,5,8,19,27,31 BOOT_DISABLEn
1 4 2 3
DSK_3V3 U25 SN74LVC1G32DCKRG4 C125 .1uF
4,14 SPI0_CLK 4,14 SPI0_SOMI 4,14 SPI0_SIMO 4 SPI0_SCSn 4,14 SPI0_ENAn
3 4 7 8 11 1A1 1A2 1A3 1A4 1A5 1OE 1B1 1B2 1B3 1B4 1B5 1
2 5 6 9 10
28 SEL_EXP2_QEP0
R137 2K
14 17 18 21 22 2A1 2A2 2A3 2A4 2A5 2OE GND 2B1 2B2 2B3 2B4 2B5 13
15 16 19 20 23 12
EQEP0A 28 EQEP0B 28 EXP2.SPI0_SIMO 28 EXP2.SPI0_SOMI 28 EXP2.SPI0_CLK 28
1 4 2 3
U26 SN74LVC1G00DCKRG4 DSK_3V3
SN74CBTLV3384PW
DSK_3V3
R138 NO-POP
R139 NO-POP
R140 NO-POP U27
C126 .1uF
1 2 3 4
R141 0 R142 0 R143 NO-POP
A0 A1 NC VSS
VCC WP SCL SDA

24WC256
8 7 6 5
I2C0_SCL I2C0_SDA
I2C0_SCL 4,22,24,27,28,30 I2C0_SDA 4,22,24,27,28,30
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date: OMAP-L137 EVM SPI ROM DWG NO 511342-0001 Monday, Novem ber 24, 2008 Sheet 16 o f Revision: A 32
A-17
4 3 2 1
5 6 7 8
A-18
4 3 2 1
DSK_3V3
D
RN23 RPACK4-10K
SW3 RN24
8 8 8 8 LOW PROFILE DIP-4 RPACK4-1K

SILKSCREEN: USER SWITCHES
USER_SW1 USER_SW2 USER_SW3 USER_SW4
1 2 3 4
8 7 6 5
5 6 7 8
4 3 2 1
DSK_3V3
R144 330
R145 330
R146 330
R147 330
DS1 LED_GRN
DS2 LED_GRN
DS3 LED_GRN
DS4 LED_GRN
8 8 8 8
USER_LED1 USER_LED2 USER_LED3 USER_LED4
USER CONTROLLED LEDS
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size:B Date:

4 3 2
OMAP-L137 EVM USER SWITCHES LEDS DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
L2 BLM21PG221SN1D DSK_3V3 DSK_3V3 C127 1uF U28

+
DSK_3V3 GND_E_RS232
D
C128 10uF
R148 10K
R149 10K
15 VCC FORCEON
L3 UART2_TXD 1uH C130 10pF GND_E_RS232 L4 1uH P1 C132 10pF GND_E_RS232 BLM21PG221SN1D L5 R150 10K GND_E_RS232
FORCEOFF 12
16
DB9M
5 UART2_TXD
11 T_IN
C129 10pF
T_OUT
13
5 UART2_RXD
UART2_RXD
9 R_OUT R_IN
GND_E_RS232
5 9 4 8 3 7 2 6 1 11
1 EN INVALID
10
C131 10pF
10
2 C1+
C134 1uF
C2+
GND_E_RS232
SILKSCREEN: UART
C133 1uF
4 C1V+ 14 GND
MAX3221CPWRG4
C23 7
C135 1uF
V-
C136 1uF

4 3 2
OMAP-L137 EVM RS232 DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
A-19
R151 2K DSK_3V3
A-20
4 3 2 1
DSK_3V3
C137 0.1uF U29
1 4 2
1G08
Disconnect A1 port = B1 port A1 port = B2 port A2 port = B1 port A2 port = B2 port Disconnect A1 port = B1 port/A2 port = B2 port A1 port = B2 port/ A2 port = B1 port FUNCTION FUNCTION TABLE INPUTS INPUTS/OUTPUTS S2 S1 S0 A1 A2 L L L Z Z L L H B1 Z L H L B2 Z L H H Z B1 H L L Z B2 H L H Z Z H H L B1 B2 H H H B2 B1
29 EXP3_SEL_MEMD0_7
C138 0.1uF U30 DSK_3V3
1 4
2,3,4,5,8,16,27,31 BOOT_DISABLEn 1g02 U31 C139 0.1uF
2
C140 .01uF
1 56 55 VCC.1 S0 S1 S2 1A1 2A1 3A1 4A1 5A1 6A1 7A1 8A1 9A1 10A1 11A1 12A1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 54 52 50 47 45 43 41 39 36 34 32 30
EMIFA_D0 EMIFA_D1 EMIFA_D2 EMIFA_D3 EMIFA_D4 EMIFA_D5 EMIFA_D6 EMIFA_D7 EMIFA_A1 EMIFA_A2 8 EMIFA_CS4n 8 EMIFA_CS5n 8 8 8 8 8 8 8 8 8 8 EMIFA_D0 EMIFA_D1 EMIFA_D2 EMIFA_D3 EMIFA_D4 EMIFA_D5 EMIFA_D6 EMIFA_D7 EMIFA_A1 EMIFA_A2
17
C
2 4 6 9 11 13 15 18 21 23 25 27
MMC_SD_DATA0 20 MMC_SD_DATA1 20 MMC_SD_DATA2 20 MMC_SD_DATA3 20 MMC_SD_DATA4 20 MMC_SD_DATA5 20 MMC_SD_DATA6 20 MMC_SD_DATA7 20 MMC_SD_CLK 20 MMC_SD_CMD 20 MMC_SD_WP 20 MMC_SD_INS 20
3 5 7 10 12 14 16 20 22 24 26 28 1A2 2A2 3A2 4A2 5A2 6A2 7A2 8A2 9A2 10A2 11A2 12A2 GND.1 GND.2 GND.3 GND.4
SN74CBTLV16212DGGR
1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 8 19 38 49
53 51 48 46 44 42 40 37 35 33 31 29
EXP_EMIFA_D0 EXP_EMIFA_D1 EXP_EMIFA_D2 EXP_EMIFA_D3 EXP_EMIFA_D4 EXP_EMIFA_D5 EXP_EMIFA_D6 EXP_EMIFA_D7 EXP_EMIFA_A1 EXP_EMIFA_A2
EXP_EMIFA_D0 29 EXP_EMIFA_D1 29 EXP_EMIFA_D2 29 EXP_EMIFA_D3 29 EXP_EMIFA_D4 29 EXP_EMIFA_D5 29 EXP_EMIFA_D6 29 EXP_EMIFA_D7 29 EXP_EMIFA_A1 29 EXP_EMIFA_A2 29 EXP_EMIFA_CS4n 29 EXP_EMIFA_CS5n 29
R153 360

4 3 2
OMAP-L137 EVM SD/MMC CARD MUXING DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
Revision: B Sheet 19 o f 32
DSK_3V3
D
DSK_3V3
+
C141 10UF
C142 0.1uF
R154 51K
R155 51K
R156 51K
R157 51K
R158 51K
R159 51K
R160 51K
R161 51K
R162 51K
R163 51K P2 MMC_SD_DATA3 MMC_SD_CMD MMC_SD_CLK MHC-W21-601
19 MMC_SD_DATA3 19 MMC_SD_CMD
19 MMC_SD_CLK
19 19 19 19 19 19 19 DSK_3V3 DSK_3V3
MMC_SD_DATA0 MMC_SD_DATA1 MMC_SD_DATA2 MMC_SD_DATA4 MMC_SD_DATA5 MMC_SD_DATA6 MMC_SD_DATA7
MMC_SD_DATA0 MMC_SD_DATA1 MMC_SD_DATA2 MMC_SD_DATA4 MMC_SD_DATA5 MMC_SD_DATA6 MMC_SD_DATA7
1 2 3 4 5 6 7 8 9 10 11 12 13
#1_MMC+/MMCM/RSMMC/MMC/SD #2_MMC+/MMCM/RSMMC/MMC/SD #3_MMC+/MMCM/RSMMC/MMC/SD #4_MMC+/MMCM/RSMMC/MMC/SD #5_MMC+/MMCM/RSMMC/MMC/SD #6_MMC+/MMCM/RSMMC/MMC/SD #7_MMC+/MMCM/RSMMC/MMC/SD #8_MMC+/MMCM/SD #9_MMC+/MMCM/SD #10_MMC+/MMCM #11_MMC+/MMCM #12_MMC+/MMCM #13_MMC+/MMCM
10
U32
10
U33
VCC
1 IO1 IO2 IO3 GND GND NC.4 IO4 6 NC.4 IO4 4 6 IO5 7 IO3 IO5 3 7 IO6 8 IO2 IO6 2 8 NC.9 IO1 NC.9 2 3 4
R165 NO-POP R166 NO-POP
VCC
16 17 18 19 20 21 22 23 24 25 26 27 28 14 15
#1_miniSD #2_miniSD #3_miniSD #4_miniSD #5_miniSD #6_miniSD #7_miniSD #8_miniSD #9_miniSD #10_miniSD #11_miniSD GND1 GND2 SD_WP CD
R164 NO-POP TPD6E001RSE TPD6E001RSE
SD/MMC Connector 6 in 1 MMC+, MMCMobile, SD, MMC, miniSD, RS-MMC

DSK_3V3
R167 10K
R168 10K
19 MMC_SD_WP 19 MMC_SD_INS

4 3 2
OMAP-L137 EVM SD/MMC CARD INTERFACE DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
A-21
JTAG_TCK T_TCK JTAG_TRSTn
2A 5
U35
14 Pin Emulation Header C146 .1 uF
1 15 S OE GND 8
SN74CBTLV3257PWR DSK_3V3 C147 0.1uF
JTAG_TRSTn
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_RTCK
JTAG_TCK
U57 Embedded_USB DSK_3V3 R380 0 R381 0 R382 0 R383 0
2 4 6 8 10 12 14 16 18 20 1 T_AIN1 T_AIN2 T_AIN3 1 1

JTAG_TRSTn JTAG_TDI JTAG_TMS JTAG_TCK JTAG_RTCK JTAG_TDO SAMTEC-TSM-110-DV R179 10K
1 3 5 7 9 11 13 15 17 19
4
SN74LVC1G04
A-22
4 3 2 1
R169 10K
DSK_3V3
JTAG MULTIPLEXERS
DSK_3V3 C143 U34 0.1uF DSK_3V3 C144 NO POP
D
JTAG_TRSTn
R170
NO POP
J4 JTAG_TDI JTAG_TMS JTAG_TDI JTAG_TMS T_TMS T_TDI
VCC 1A 7
DSP_TMS 10 DSP_TMS
16 4
DSP_TDI 10 DSP_TDI C145 0.1uF
JTAG_TDO JTAG_RTCK JTAG_TCK
3A 4 12
DSP_TRST# 10 SN74LVC1G32 DSP_TRST# R171 33 DSP_TCK
9 1 2
2 4 6 8 10 12 14 TRSTn TMS GND.1 TDI GND.2 TVD GND.3 TDO GND.4 RTCK GND.5 TCK EMU1 EMU0
T_TRSTn DSP_TCK 10
1 3 5 7 9 11 13 4A
EMU_STS
2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
U36 JTAG_EMU0 T_EMU0 JTAG_TDO T_TDO JTAG_EMU1 T_EMU1 JTAG_RTCK T_TCK_RET JTAG_EMU0
JTAG_EMU1
VCC 1A 2A 3A 4A GND 8 12
DSP_RTCK 10 DSP_RTCK
16 4
DSP_EMU0 10 DSP_TDO DSP_EMU1 10 10
C
DSP_EMU0 DSP_TDO DSP_EMU1
7 9
2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE 1 15

SN74CBTLV3257PWR
DSK_3V3 DSK_3V3 DSK_3V3 R172 1.5K R173 150 USB1
EMU_STS
DSK_3V3 C148 0.1uF U37 DS5 DSK_3V3 VCC_5V
R174 10K
DSP_RS_OUT_ODn
EMU_STS
2 1 3.3V
Green
DSK_3V3
C149 .1 uF
SN74AHC1G14DCKRG4
5V
GND
GND
T_TRSTn T_TMS T_TDI T_TCK T_TCK_RET T_TDO T_EMU0 T_EMU1
T_TRSTn T_TMS T_TDI T_TCK T_TCK_RET T_TDO T_EMU0 T_EMU1
R175 10K
B
DSK_3V3
RESET_INn
XRSn 31
R178
NO-POP
PONRSnIN 31
R176 0 J5
R177 0
1 T_AIN0
T_IO_POWERONn
DSK_3V3
T_TPD
C25 0.1uF
TP35 TP TP36 TP TP37 TP TP38 TP
2 1
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: ARM_RSTn ARM_RSTn 31 Size: B Date:
4 3 2
OMAP-L137 EVM TI14 PIN/ARM 20 PIN JTAG EMULATION DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
DSK_3V3 L6 BLM21PG221SN1D
+ +
DSK_3V3 L7 C150 10uF VCC_1V8 BLM21PG221SN1D DSK_3V3 GND_AIC .1uF R181 5.6K
+
BLM21PG221SN1D
C151 .1uF C156 .1uF C157 .1uF C155 10uF
C152 .1uF
C153 .1uF
C154 .1uF
5 6
C158 .1uF R180 1uF L9 C162 10uF C164 .1uF 5.6K
Line In 3
C159
L8 C160
BLM21PG221SN1D C165 .1uF
4 2 1
C161 220pF C163 .1uF U38 GND_AIC C166 .1uF R182 5.6K GND_AIC TVL320AIC3106
P3
5 6
Mic In GND_AIC 3
36
L10 R183 5.6K
DVDD.1 DRVSS.1 DRVSS.2

C168
+
DRVDD.1 DRVDD.2 DRVDD.3 20 21

33uF,6.3V L11 GND_AIC C169
+
16 17 24
P5 GND_AIC BLM21PG221SN1D L12 BLM21PG221SN1D R185 20K GND_AIC
Headphone Out
42 DVSS IOVDD AVDD_DAC LINE1L+ LINE1LLINE1R+ LINE1RLINE2L+ LINE2LLINE2R+ LINE2RMIC3R LEFT_LO+ MIC3L LEFT_LOMICDET RIGHT_LO+ MICBIAS RIGHT_LO33 RESET BCLK WCLK DIN DOUT SDA SCL TPAD SELECT MCLK 49 37
R198 NO-POP
4 2 1
C167 220pF
BLM21PG221SN1D
44 25 26 15 3 4
C170 .1uF
1 2 4 3
R186 20K
P4 GND_AIC R184 330
GND_AIC
33uF,6.3V
AVSS_DAC AVSS_ADC
5 6 HPLOUT HPLCOM HPROUT HPRCOM 23 22 18 19
C171 220pF R189 10K 23 HANDSET_MIC_N 23 HEADSET_MIC_P 23 HEADSET_MIC_N R188 330 23 HANDSET_MIC_P
R187 47K
C172 .1uF
7 8 9 10 MONO_LO+ MONO_LO29 30 14 11 27 28
HEADSET_SPKR_P 23 HEADSET_SPKR_N 23 HANDSET_SPKR_P 23 HANDSET_SPKR_N 23
GND_AIC
GND_AIC
GND_AIC
GND_AIC
1 1
C173
+
TP39 TEST POINT TP40 TEST POINT GND_AIC 10uF,6.3V C174

+
P6 L13 BLM21PG221SN1D 10uF,6.3V L14 BLM21PG221SN1D R192 20K
1 2 4 3
23 MIC_BIAS_HS
MIC_BIAS_HS
R190
12 31 32 35 34 GPIO1 GPIO2 13
R191
31 AIC3106_RESETn R194 R195 R196 R197 10 10 10 10 AIC_BCLK AIC_WCLK AIC_DIN AIC_DOUT
1 1
2 T_AIC_BCLK 2 T_AIC_WCLK 2 T_AIC_DIN 2 T_AIC_DOUT
38 39 40 41 2 1 43
TP7 TEST POINT TP8 TEST POINT
R193 20K
4,16,24,27,28,30 I2C0_SDA 4,16,24,27,28,30 I2C0_SCL
MFP0 MFP1 MFP2 MFP3
45 46 47 48
DSK_3V3
GND_AIC
GND_AIC
R199 NO-POP
R200 NO-POP
R201 NO-POP
1 1 1 1
TP9 TEST POINT TP10 TEST POINT TP11 TEST POINT TP12 TEST POINT
DSK_3V3 R202 20K R203 NO-POP
DSK_3V3
R204 NO-POP
R205 NO-POP
R206 2K
R207 2K
C175 U39 R208 2K .1uF
1 2
EN GND
VCC OUT
24.576 MHz
4 3
R209 22
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: OMAP-L137 EVM AIC3106 AUDIO INTERFACE
ISOLATE GROUNDS AND CONNECT AT SINGLE LOCATION IN THE GROUND PLANE
2 T_AIC_MCLK
R210
22 Size:B GND_AIC Date: Monday, November 24, 2008 Sheet 22 o f DWG NO 511342-0001
6 5
6 5
Line Out Revision: B 32
A-23
C196 0.01uF
C197 0.01uF
R232 0
RJ9-4
GND_AIC
GND_AIC
A-24
4 3 2 1
22 MIC_BIAS_HS
MIC_BIAS_HS R211 2.2K
22 HANDSET_MIC_P P14 R213 10K 1% R214 10K 1%
C176
0.22uF
C177
0.22uF
C178
0.47uF
D
5
0.47uF PHONOJACK_ST R216 NO-POP
TIP
VCC_5V 22 HANDSET_MIC_N R212 1 C179 R215

+
C180 0.22uF
C181 0.22uF
C182
2 RING 1 SLEEVE
18pF 20K C183 22uF GND_AIC C184 0.1uF GND_AIC
22 MIC_BIAS_HS R390 0
MIC_BIAS_HS
R217
U40 R218 10K
22 HANDSET_SPKR_N
C185
0.47uF
4 ININ+ BYPASS SHUTDOWN

TPA4861D GND_AIC
VDD VO1 V02 GND 7

C187 0.01uF C188 0.01uF
6 5 8
R220 R221 0 0
GND_AIC
GND_AIC
P15
22 HANDSET_SPKR_P R222 0
C186
0.47uF
R219
10K
3 2 1
TIP
2 RING 1 SLEEVE
PHONOJACK_ST GND_AIC
C
R224 10K GND_AIC GND_AIC
C189 0.1uF
GND_AIC 22 MIC_BIAS_HS MIC_BIAS_HS R225 2.2K
22 HEADSET_MIC_P R226 10K 1% R227 10K 1%
C190
0.22uF
C191
0.22uF
C192
0.47uF
22 HEADSET_MIC_N
C193 0.22uF
C194 0.22uF
C195
0.47uF
R228
NO-POP
B
22 MIC_BIAS_HS
MIC_BIAS_HS
R229
0 P8 R230 R231 0 0
22 HEADSET_SPKR_P 22 HEADSET_SPKR_N
4 3 2 1

4 3 2
OMAP-L137 EVM AIC3106 RJ9-4/ PHONO INTERFACES DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
DSK_3V3
U42
3 2
Differential Pair
U41A R233 1K
4
P1LED3 P1LED2 26 26
VCC 1 1
RXP1 RXM1 TXP1 TXM1 P2LED3 P2LED2 26 26 26 26 26 26
OUT
DSK_3V3 R234 R235 TP13 TEST POINT TP14 TEST POINT 220 220 P1LED3 P1LED2
C198
EN
GND
0.01uF R236 2.2K
P1LED3 P1LED2 P1LED1 P1LED0 99 96 SPIS_N SPIQ

Differential Pair
25 1 2 3 45 46 48 49
R239 R240
Differential Pair
50.000 MHz
R237 49.9 R238 49.9
RXP1 RXM1 TXP1 TXM1

TXP1 TXM1 220 220 P2LED3 P2LED2
RXP1 RXM1
3 B_RMII_MDIO_D 3 B_RMII_MDIO_CLK
95 94 MDIO MDC P2LED3 P2LED2 P2LED1 P2LED0 RXM2 RXP2

Differential Pair
20 4 5 6 52 53
RXM2 RXP2 TXM2 TXP2 RXM2 RXP2 TXM2 TXP2
1 1
TP15 TEST POINT TP16 TEST POINT 26 26 26 26 R244 NO-POP R245 NO-POP R246 NO-POP R247 NO-POP
3 B_RMII_RXD[0] 3 B_RMII_RXD[1]
R242 R243
49.9 49.9
87 86 85 84 83 82 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 TXM2 TXP2 55 56 SMRXDV SMRXC 81 80
DSK_3V3
3 B_RMII_CRS_DV
R241
49.9
R248 2K
R249 2K
3 B_RMII_MHZ_50 R250 0
3 B_RMII_TXD[0] 3 B_RMII_TXD[1]
3 B_RMII_TXEN
77 76 75 74 73 72 71 SMTXC/REFCLK SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN LEDSEL1 LEDSEL0 ADVFC P2FFC P2MDIXDIS P2MDIX 12 16 28 29
ADVFC P2FFC P2MDIXDIS P2MDIX
23 70
4,16,22,27,28,30 I2C0_SDA 4,16,22,27,28,30 I2C0_SCL
R389 R333
0 0
98 97 SDA SCL P2ANEN P2SPD P2DPX HWPOVR 13 14 15 27
R251 NO-POP P2ANEN P2SPD P2DPX HW POVR
R252 NO-POP
R253 2K
R254 2K
R255 NO-POP
R256 NO-POP
31 ENET_RESET
67 RST_N P1ANEN P1SPD P1DPX P1FFC 36 PWRDN RMII_EN ISET SCONF0 SCONF1 X1 101 PS0 PS1 X2
KSZ8893MQL
DSK_3V3
PS1 = 0, PS0 = 1 (I2C slave mode)

26 89 88
R271 2K R272 NO-POP
30 31 32 33 FXSD1 44
P1ANEN P1SPD P1DPX P1FFC R257 NO-POP R258 NO-POP R259 2K R260 2K R261 NO-POP R262 NO-POP R263 2K R264 2K R265 NO-POP
B
DSK_3V3
61
R266
3.01K
65
DSK_3V3
R267 NO-POP
R268 2K
R269 2K
R270 NO-POP
100
66
R273 10K
R274 NO-POP
R275 2K
R276 NO-POP
R277 NO-POP
R278 NO-POP
R279 NO-POP
R280 NO-POP
R281 NO-POP
R282 NO-POP
Y3
NO-POP
C199 NO-POP C200 NO-POP Title: Page Contents:
NOT POPULATE FOR RMII
R283 2K R287 NO-POP R288 NO-POP
R284 NO-POP
R285 NO-POP
R286 2K
SPECTRUM DIGITAL INCORPORATED OMAP-L137 EVM KSZ8893MQL ETHERNET/PHY/SWITCH Size:B Date: DWG NO 511342-0001 Monday, Novem ber 24, 2008 Sheet 24 o f Revision: B 32
A-25
A-26
ENET_VDDIO
DSK_3V3 L19
2
U41B 1K 0.1uF 0.1uF 10uF 10uF 0.1uF 100uF
D
1
C207 C203
+
BLM21PG221SN1D C204 0.1uF R290 100 C205 C206 C201 + C202 +
R289
DSK_3V3
R291
1K
VDDIO.3 VDDIO.2 VDDIO.1
107 79 8
R292
10K
VDDC.3 VDDC.2 VDDC.1
123 91 22
ENET_VDDC ENET_1V2
L20
R293 C208 C211 + C213 0.1uF 10uF 0.1uF 10uF 0.1uF 0.1uF C212 + C209 C210 BLM21PG221SN1D
1K
DGND.6 DGND.5 DGND.4 DGND.3 DGND.2 DGND.1 VDDARX VDDATX 50 51
122 106 90 78 21 7 2 1
ENET_VDDATR
VDDAP
L21
68 69 92 93 102 103 104 105 108 109 110 111 112 113 114 115 116 117 118 119 120 121 124 125 126
DSK_3V3
UNUSED.68 UNUSED.69 UNUSED.92 UNUSED.93 UNUSED.102 UNUSED.103 UNUSED.104 UNUSED.105 UNUSED.108 UNUSED.109 UNUSED.110 UNUSED.111 UNUSED.112 UNUSED.113 UNUSED.114 UNUSED.115 UNUSED.116 UNUSED.117 UNUSED.118 UNUSED.119 UNUSED.120 UNUSED.121 UNUSED.124 UNUSED.125 UNUSED.126 63 2
BLM21PG221SN1D C215 0.01uF 0.1uF 47uF C216 C214
+
DSK_3V3
R294 NO-POP
R295 NO-POP
R296 NO-POP
R297 NO-POP
9 10 11 17 18 19 24 34 35 NC.9 NC.10 NC.11 NC.17 NC.18 NC.19 NC.24 NC.34 NC.35 VDDA.3 VDDA.2 VDDA.1 57 43 38
60 59 40 41 TEST2 TEST1 MUX1 MUX2
AGND.8 AGND.7 AGND.6 AGND.5 AGND.4 AGND.3 AGND.2 AGND.1
64 62 58 54 47 42 39 37
ENET_VDDAP
L22
ENET_1V2
R298 NO-POP
R299 NO-POP
R300 NO-POP
R301 NO-POP
2 127 128 TESTEN SCANEN

C218 0.001uF R302 1K KSZ8893MQL R303 1K 0.1uF C219 C217 10uF / 16V
+
1
BLM21PG221SN1D
ENET_VDDA
L23
ENET_1V2
2 1
BLM21PG221SN1D
C222 0.1uF 0.1uF
C223
C224 0.1uF
C220 10uF
C221 + 10uF

4 3 2
OMAP-L137 EVM KSZ8893MQL ETHERNET POWER DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
DSK_3V3
SILKSCREEN: ETHERNET
C225 P9 0.1uF 24 24 P1LED2 P1LED3 R304 49.9 R305 49.9 RJ45 HALO HFJ11-2450E-L21
12 11 10 9 LED2LED2+ LED1LED1+ NC1 GND 7 8
Differential Pair
24 TXM1 RXP1
TXP1
TXP1
24
TXM1
1 4 2 TXD+ TXD-CT TXD-
24
RXP1
MH1 MH2
RXD+ RXD-CT RXDMH1 MH2 SH1 SH2 SH1 SH2
24
Differential Pair
RXM1
RXM1
3 5 6
C226 1000pF 2kV ENET_VDDATR

+
C227 GND_E_ENET GND_E_ENET 10uF

C
R306 49.9
R307 49.9
C228 0.1uF
DSK_3V3
SILKSCREEN: ETHERNET
C229 P10 0.1uF 24 24 P2LED2 P2LED3 R308 49.9 R309 49.9 RJ45 HALO HFJ11-2450E-L21
12 11 10 9 7 8
LED2LED2+ LED1LED1+ NC1 GND

B
Differential Pair
24 TXM2 RXP2 RXM2

Differential Pair
TXP2
TXP2
24
TXM2
1 4 2 3 5 6
TXD+ TXD-CT TXD-
24
RXP2
MH1 MH2
RXD+ RXD-CT RXD-
C230 1000pF 2kV ENET_VDDATR

+
C231 GND_E_ENET GND_E_ENET R311 49.9 10uF
R310 49.9
C232 0.1uF Title: Page Contents: Size: B Date:

4 3 2
MH1 MH2
SH1 SH2
SH1 SH2
24
RXM2
SPECTRUM DIGITAL INCORPORATED OMAP-L137 EVM KSZ8893MQL ETHERNET PORTS DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
A-27
2,3,4,5,8,16,19,31 BOOT_DISABLEn
1 3
A-28
4 3 2 1 D
VCC_5V DSK_3V3 P11
VCC_5V
C233 .1uF 3,14 SEL_ENETn_MCASP0 2 T_AMUTE0 T_AMUTE0 EXP1_AFSX0 T_AFSR0 T_ACLKR0 2 2 2,6 T_ACLKX0 T_ACLKX0 T_ACLKR0 T_AFSR0 I2C0_SDA 4,16,22,24,28,30 I2C0_SCL 4,16,22,24,28,30 EXP_AHCLKR0 3
2 U43 SN74CBTLV1G125
T_AFSX0
3 3 3 3 3 3 3 3 T_AXR0_11/AXR2_0/GPIO3_11 EXP1_AMUTE2 8 8 AHCLKR2
EXP_AXR0[0] EXP_AXR0[1] EXP_AXR0[2] EXP_AXR0[3] EXP_AXR0[4] EXP_AXR0[5] EXP_AXR0[6] EXP_AXR0[7]
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
EXP_AXR0[8] 3 EXP_AXR0_9 4 EXP_AXR0_10 4 EXP1_AXR0_12 8 EXP1_AXR0_13 8 EXP1_AXR0_14 8 EXP1_AXR0_15 8 T_AXR0_11/AXR2_0/GPIO3_11 2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
5 EXP1_SPI1_SCSn 5 EXP1_SPI1_CLK 2 T_AMUTE1 T_AMUTE1 2 T_AHCLKR1 2 2 EXP_ACLKX1 T_AXR1[1] T_AXR1[2] T_AXR1[6] T_AXR1[7] T_AXR1[8] T_AXR1[9] T_AXR1[10] T_AXR1[11] VCC_5V T_ACLKR1 EXP_AFSX1 T_AFSR1
EXP1_SPI1_ENAn 5 EXP1_SPI1_SIMO 5 EXP_SPI1_SOMI 5 EXP_AHCLKX1 2 T_AFSR1 T_ACLKR1 2 2 T_AXR1[6] 2 T_AXR1[7] 2 T_AXR1[8] 2 T_AXR1[9] 2 T_AXR1[10] 2 T_AXR1[11] 2 SEL_SPI1_EXP1 5
B
2 EXP_AXR1[0] 2 T_AXR1[1] 2 T_AXR1[2] 2 EXP_AXR1[3] 2 EXP_AXR1[4] 2 EXP_AXR1[5] 2 EXP1_SEL_MCASP1 28,29,31 EXP_RESETn VCC_5V
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
89 MH1 81 82 83 84 85 86 87 88 85 86 87 88 MH2 81 82 83 84
90
QSE-040-01-L-D-A
Mounting holes 0.250 pad 0.125 drill
SPECTRUM DIGITAL INCORPORATED
Z2
Z1 Title: Page Contents: Size: B Date:
OMAP-L137 EVM AUDIO / EXPANSION COINNECTOR 1 DWG NO 511342-0001 Monday, Novem ber 24, 2008
3 2 1

4
VCC_5V P12
VCC_5V
5 EXP2_SPI1_SOMI 5 EXP2_SPI1_SIMO 5 EXP2_SPI1_CLK 5 EXP2_SPI1_SCSn 5 EXP2_SPI1_ENAn I2C0_SCL 4,16,22,24,27,30 I2C0_SDA 4,16,22,24,27,30
EXP2.SPI0_SOMI 16 EXP2.SPI0_SIMO 16 EXP2.SPI0_CLK 16 EQEP0A 16 EQEP0B 16
5 SEL_SPI1_EXP2 2 EXP_EQEP1A 2 EXP_EQEP1B 2 SEL_EXP2_QEP1 4 EXP2_UART1_RXD 4 EXP2_UART1_TXD SEL_EXP2_QEP0 16 EXP2_TMP64P0_OUT12 4 EXP2_TMP64P0_IN12 4 SEL_SPI1_EXP2_B 5 SEL_EXP2_TIMER 4,14 VCC_5V 4,14 SEL_EXP2_UART1 27,29,31 EXP_RESETn VCC_5V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
41 42 41 42 43 44
43 44
QSE-020-01-L-D-A
Z3
Z4

4 3 2
OMAP-L137 EVM EXPANSION 2 DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
A-29
A-30
4 3 2 1
VCC_5V P13
VCC_5V
D
19 EXP3_SEL_MEMD0_7 8 EXP3_SEL_MEM EXP3_SEL_MEM_CTL 8 EXP_EMIFA_D1 EXP_EMIFA_D3 EXP_EMIFA_D5 EXP_EMIFA_D7 EXP_EMIFA_D1 EXP_EMIFA_D3 EXP_EMIFA_D5 EXP_EMIFA_D7 EXP_EMIFA_D9 8 EXP_EMIFA_D11 8 EXP_EMIFA_D13 8 EXP_EMIFA_D15 8 EXP3_EMIFA_WEn_DQM0 8 EXP3_EMIFA_WEn_DQM1 8 EMIFA_SDCKE 8 19 19 19 19 EXP_EMIFA_D9 EXP_EMIFA_D11 EXP_EMIFA_D13 EXP_EMIFA_D15 19 19 19 19 8 EXP_EMIFA_D8 8 EXP_EMIFA_D10 8 EXP_EMIFA_D12 8 EXP_EMIFA_D14 8,14 EXP3_SEL_MEMD8_D11 8,14 EXP3_SEL_MEMD12_D15 8 EXP3_EMIFA_CLK EXP_EMIFA_D8 EXP_EMIFA_D10 EXP_EMIFA_D12 EXP_EMIFA_D14 EXP_EMIFA_D0 EXP_EMIFA_D2 EXP_EMIFA_D4 EXP_EMIFA_D6 EXP_EMIFA_D0 EXP_EMIFA_D2 EXP_EMIFA_D4 EXP_EMIFA_D6
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
8 EXP3_EMIFA_OEn 8 EXP3_EMIFA_WEn 8 EMIFA_WAIT0 8 EXP_EMIFA_CS0n EMIFA_CS2n 8 EXP3_EMIFA_CS3n 8 EXP_EMIFA_A2
EXP_EMIFA_CS4n 19 EXP_EMIFA_CS5n 19
8 EMIFA_BA0 8 EMIFA_BA1 19 EXP_EMIFA_A1 8 EMIFA_A3 8 EMIFA_A5 8 EMIFA_A7 8 EMIFA_A9 8 EMIFA_A11 EXP_EMIFA_A1 27,28,31 EXP_RESETn VCC_5V VCC_5V EXP3_SEL_MEM_CTL2 8
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
EMIFA_A0 8 EXP_EMIFA_A2 19 EMIFA_A4 8 EMIFA_A6 8 EMIFA_A8 8 EMIFA_A10 8 EMIFA_A12 8
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
89 MH1 81 82 83 84 85 86 87 88 85 86 87 88 MH2 81 82 83 84
90
QSE-040-01-L-D-A
Z5

4 3 2
OMAP-L137 EVM EXPANSION 3 DWG NO 511342-0001 Monday, Novem ber 24, 2008
1
VCC_5V VCC_1V2 0.025 CPU_1V2
VCC_3V3 R312
DSK_3V3
R314 NO-POP
TP17 TP-60
0.025
R313
TP18 TP-60 CPU_3V3

D
VCC_5V
TP19 TP-60
TP20 TP-60
R315 1K
+
0.025 C234 10uF L15 VCC_5V R317 C235 0.1uF VCC_3V3 VCC_1V8 L16 R321
+
R316
VLDO2
ALT_3V3
BLM41P750SPT
TP21 TP-60 VCC_1V8 0.025
TP22 TP-60 DSK_1V8 R318
VCC_5V
R319 1K 2.2uH NO-POP C236 22uF R322 NO-POP
R320
NO-POP
TP23 TP-60
TP24 TP-60 CPU_1V8 0.025 R323
ALT_3V3
R324 NO-POP
TP25 TP-60
TP26 TP-60 R325 10K R326 10K
41
40 39 38 37 36 35 34 33 32 31
VCC_3V3 U44
VCC_5V
+
C238 10uF L17 L18 2.2uH 2.2uH
AGND1 LOWBAT_SNS PWRFAIL_SNS VCC VINDCDC2 L2 PGND2 VDCDC2 DEFDCDC2 PWRFAILn
PWR_PAD
C237 22uF
I2C0_SDA 4,16,22,24,27,28 I2C0_SCL 4,16,22,24,27,28 1 SYS_RESETn 31 ALT_3V3 C239 0.001uF VCC_5V
TP27 TP-60
VCC_5V VCC_1V2
+ +
C240
1 2 3 4 5 6 7 8 9 10 DEFDCDC3 VDCDC3 PGND3 L3 VINCDDC3 VINDCDC1 L1 PGND1 VDCDC1 DEFCDCD1
SDAT SCLK INTn RESPWRONn TRESPWRON DCDC1_EN DCDC2_EN DCDC3_EN LDO_EN LOWBATn
29 30 28 27 26 25 24 23 22 21
10uF C241 22uF VCC_5V
R327 2K R330 NO-POP
HOT_RESETn DEFLDO1 DEFLDO2 VSYSIN VBACKUP VRTC AGND2 VLDO2 VINLDO VLDO1
R328 47K
R329 10K
11 12 13 14 15 16 17 18 19 20
TPS65023 CPU_RTC_1V8
ENABLE_1V2 31 ENABLE_1V8 31 ENABLE_3V3 31
R331 10K VCC_5V
R332 10K
+
1
C242 22uF
C267 NO-POP TP28 TP VLDO2 VCC_5V R338 10K VCC_5V
C268 0.1uF
C269 0.1uF
VCC_5V
R339 NO-POP
R340 NO-POP
R336 NO-POP
0 R337 NO-POP 0
. DEFLDO2 DEFLDO1 0 1 1 0 1 1
VLDO1 VLDO2 1.3 V 3.3 V 2.8 V 3.3 V 1.3 V 1.8 V 1.8 V 3.3 V
1
VRTC
+
C243 2.2uF 10K R343 0 C245

+ +
VCC_5V R387 SW4 R344 0
TP29 TP C244 Title: 10uF 2.2uF Page Contents: R342 NO-POP
SPECTRUM DIGITAL INCORPORATED OMAP-L137 EVM CORE POWER
R341 1K
A A1
B B1
PUSHBUTTON SW
R345
33 Size: B PB_RESET 31
4 3 2
DWG NO Date:
511342-0001 Monday, Novem ber 24, 2008

1
A-31
ALT_3V3 ALT_3V3 C247 0.1uF ALT_3V3 C246 U45 0.1uF
SENSE1 5
U46 DSK_1 V2_SYS_OKAY 21 ARM_RSTn
TPS3808G09DBVRG4
SENSE1 CT 5
U49
VDD RESET GND 1

ALT_3V3 TP31
C251 0.1uF DSK_1 V8_SYS_OKAY DSK_3V3_SYS_OKAY
R351 10K 1%
4 1 2 1 4 2 3
1G08 R352 30 SYS_RESETn R354 R357 R358 33 33 33 R388 0 33 TP47 TP C252
3 MR
TPS3808G09DBVRG4
Reset Threhold 0.84 Volts
0.1uF
ALT_3V3 ALT_3V3 C253 U50 0.1uF R353 10K DSK_3V3_SYS_OKAY TP32
R335 10K
DSK_3V3
AIC3106_RESETn 22
R350
4.99K
R349 10K
CPU_RESET
R363
2.2K
4
U51 SN74AHC14DCKRG4
4
U52 SN74AHC14DCKRG4
4
U53 SN74AHC14DCKRG4
1uF NO-POP
DSK_1 V2_SYS_OKAY R361
DSK_3 V3_SYS_OKAY ENABLE_1V8 30
R362
NO-POP
DSK_1 V2_SYS_OKAY
R364
NO-POP SPECTRUM DIGITAL INCORPORATED

A
DSK_1 V8_SYS_OKAY ENABLE_3V3 30
R365
NO-POP
A-32
5 VDD RESET 4 2
1G08 U47 C249 0.1uF ALT_3V3
D
CPU_1V2
R347
6 1 2 1
TP30 21 XRSn
R346 10K
R348 10K 1%
4 CT MR GND
C248
0.1uF
ALT_3V3
1 4
ALT_3V3 1G08 CPU_RESET
DSK_1V8
ALT_3V3 C250
CPU_RESET 10,14
U48 0.1uF
R355
20K
5 SENSE1 CT MR 1
TPS3808G09DBVRG4
VDD RESET GND 2 1
ENET_RESET 24 EXP_RESETn 27,28,29 PONRSnIN 21
R356 10K 1%
4
C254
0.1uF
30 PB_RESET R334 NO-POP
BOOT_DISABLE 2,3,14,16,19 ALT_3V3 ALT_3V3 C256 0.1uF ALT_3V3 C257 0.1uF C255 .1uF TP48 TP
B
DSK_1V8_SYS_OKAY R359
NO-POP
DSK_3 V3_SYS_OKAY ENABLE_1V2 30 C258
R360
NO-POP
2 1
2 1
2 1
BOOT_DISABLEn 2,3,4,5,8,16,19,27
Title: Page Contents: Size: B Date:
OMAP-L137 EVM POWER IN DWG NO 511342-0001 Monday, Novem ber 24, 2008
3 2 1

4
TP33 TP-30 VCC_5V
SW6 SW ITCH
8 3 1 6 4
R368 220
+
2 5 7
C259 47uF
SILKSCREEN: 5V IN
J6 F1
1
F_4.0A NO-POP R366 DS7 LED GRN
CENTER SHUNT SLEEVE
2.5 MM JACK RASM712
D1 SMCJ6A
Z8
Z7
Z9
Z10
ALTERNATE 1.2V Power Supply

TP34 TP U54 ALT_CPU_1V2 VCC_5V VCC_5V
VLDO2
1 VIN VOUT
C260
TPS79901-ADJ
GND EN 2
C262 10uF R374 220 R373 220K 1%
10uF
3 FB
R372 15K 1% VCC_3V3
C261 5.6pF
R367 360
R370 360
B
DS6 LED GRN VCC_1V2 VCC_1V8
DS8 LED GRN
DS9 LED GRN
R369
1K
1 2
Q1 FJV3109R
R371
1K
1 2 1
TP45 TP
3
Q2 FJV3109R
Vout = ((R1+R2)/R2) *1.193
TP41 TP
TP42 TP
TP43 TP
TP44 TP
TP46 TP SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date: OMAP-L137 EVM POWER IN DWG NO 511342-0001 Monday, Novem ber 24, 2008 Sheet 32 o f Revision: B 32
A
A-33
A-34
Appendix B Mechanical Information
This appendix contains the mechanical information about the OMAP-L137 EVM produced by Spectrum Digital.
B-1
B-2
THIS DRAWING IS NOT TO SCALE
Printed in U.S.A., November 2008 511345-0001 Rev A

EVMOMAPL137 TechRef Revg

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EVMOMAPL137 TechRef Revg

Uploaded by

Copyright:

Available Formats

OMAP-L137 Evaluation Module

DSP Development Systems

OMAP-L137 Evaluation Module Technical Reference

511345-0001 Rev. A November 2008

Copyright 2008 Spectrum Digital, Inc.

Table 1: Manual History Revision A Beta History

Table 2: Board History PWB Revision D Beta Release History

Chapter 1 Introduction to the OMAP-L137 EVM

Spectrum Digital, Inc

Serial Exp. I2C ROM BOOT CFG RTC PWR

Micrel ENET PHY + Switch

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Figure 1-2, OMAP-L137 EVM

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Chapter 2 Board Components

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Figure 2-1, OMAP-L137 EVM CODEC INTERFACE

Spectrum Digital, Inc

Figure 2-2, OMAP-L137 MAC Address

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Chapter 3 Physical Description

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Figure 3-1, OMAP-L137 EVM, Interfaces Top Side 3-3

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Figure 3-2, J1, USB Capacitance Select

Table 2: J1, USB Capacitance Select

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Figure 3-3, 14 Pin External JTAG Connector

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

Table 8: P3, Line In Interface

Table 9: P4, Microphone In Interface

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Table 10: P5, Headphone Out Interface

Table 11: P6, Audio Line Out Stereo Jack

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference

Spectrum Digital, Inc

1 N7 N7 N11 N11 N11 N11

Spectrum Digital, Inc

OMAP-L137 EVM Technical Reference