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Introduction to VLSI Design, VLSI I, Fall 2011 4.

CMOS Transistor Theory

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4. CMOS Transistor Theory


J. A. Abraham
6D0 epartment

of Electrical and Computer Engineering The University of Texas at Austin EE 382M.7 VLSI I Fall 2011
September 7, 2011

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ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

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Electrical Properties
Necessary to understand basic electrical properties of the MOS transmismtor to desig4n0 useful 80 100 circ6u0its Deal with non-ideal devices Ensure that the circuits are robust Create working layouts Predict delays and power consumption As circuit dimensions scale down, electrical effects b6e0come more important, even for digital circuits
1.65 GHz square wave from an 8H0DMI Interface (Source: Dunnihoo, EE Times Asia, 8/25/2005)
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 1 / 31

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Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, September 7, 2011

Introduction to VLSI Design, VLSI I, Fall 2011 4. CMOS Transistor Theory

The nMOS Transistor


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Terminal Voltages Modes of operation depend on Vg , Vd , Vs


60 Vgs = Vg Vs Vgd = Vg Vd Vd s = Vd Vs = Vgs Vgd

Source and drain are symmetric diffusion terminals


By convention, source is terminal at lower voltage, so Vds 0 8 0 n M OS body is grounded for simple designs; assume source is 0

Three regions of operation: Cutoff, Linear, Saturated


ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 2 / 31

Modes in nMOS Structure


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ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

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Department of Electrical and Computer Engineering, The University of Texas at Austin J. A. Abraham, September 7, 2011

Introduction to VLSI Design, VLSI I, Fall 2011 4. CMOS Transistor Theory

nMOS Transistor Operation


Positive voltage on Gate produces electric field across substrate attractsmm electrons to the Gate and repels holes
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With sufficient voltage, region under Gate changes from p- to n-Type conducting path between the Source and Drain Inversion layer is field-induced junction, unlike a PN junction w40hich is metallurgical

Horizontal component of electric field associated with Vds > 0 is responsible for sweeping electrons from channel to drain Thres6h0old Voltage The gate voltage at which conduction takes place is the Threshold Voltage, Vt Current flow occurs when the drain to source voltage Vds > 0, a8n0d consists almost entirely of majority-carriers (electrons), that flow through the channel A depletion region insulates the channel from the substrate
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 4 / 31

Conducting nMOS Transistor


No significant current through the substrate because of reverse mm biased PN40junction wit6h0 the channel80 100 120 As the voltage from drain to source is increased, the resistive drop along the channel begins to change the shape of the channel characteristic 40 At source end of the channel, the full gate voltage is effective in inverting the channel At drain end of the channel, only the difference between the gate and the drain voltage is effective

Conduction when Vgs > Vt and Vds > 0

If Vds > Vgs Vt , then Vgd < Vt , and the channel is pinched d6o0wn (the inversion layer no longer reaches the drain)
In this case, conduction mechanism of electrons voltage; as the negative accelerated towards the

is brought about by the drift under the influence of positive drain electrons leave the channel, they are drain

V80oltage across the pinchdown channel tends to remain fixed at (Vgs Vt ), and the channel current remains constant with increasing Vds
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 5 / 31

Department of Electrical and Computer Engineering, The University of Texas at Austin J. A. Abraham, September 7, 2011

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