Multi-Octave Practical Power Amplifier Realization using GaN on SiC

WMG: Broadband PAs for Wireless Communications

D. Runton, T. Driver, K. Krishnamurthy, M. LeFevre, K. Shallal

Agenda

Motivation RFMD GaN Technology PA Design Topology Overview PA Design Methodologies

Design Examples
Summary

Motivation

Milcom and Public Mobile Radio Amplifiers

Market Drivers Improved battery life / reliability Multi-standards for inter-operability Wide-band architecture Leverage COTS components Why GaN? Higher efficiency Reduce heatsink requirements, smaller size Increase battery life Wide bandwidth Replace 3 or more amplifiers with 1 amplifier

PMR Portable Radio

JTRS Radio

Power Frequency Limit

Property Eg (eV) vs (10 7 cm/s)

Si 1.1 0.7

GaAs 1.4 0.8

GaN 3.4 2.5

Pmax

4 2 Eg vs

F2

Power Bandwidth Limit

High power density (V, I) enables high impedance Low pF/W enables broadband
Wideband HPAs covering multiple communication bands

Fhigh Flow
LDMOS LDMOS LDMOS

Fo

QL ln()

Transistor Parameters

2500 Vgs: +1V to -4V 2000

Ids (mA)

2.2 mm device
Parameter Value 1000 225 -3.5 >450 11 18 7.5 16.5 71 31.4+j46.1 Units mA/mm mS/mm V V GHz GHz W/mm W % W Id-max Peak gm Vp

1500 1000 500 0 0 10 20 30 Vds (V) 40 50 60

Vbr(GD) ft fmax Power Density Peak Power Peak Drain Eff Optimum load

40 GMax (dB) 30
Gain (dB)

|H(2,1)| (dB)

20 10 0 -10 .1 1 10 Frequency (GHz) 100

[1] Class AB Bias: Vds=48V, Ids = 20 mA/mm

ft

fmax

[2] frequency = 2.14 GHz

Broadband Topologies
Topology Resistive FB Advantages - lumped implementation - good S22 Disadvantages - Output not designed for Zopt - Tuning Zload affects gain flatness and S11 - Rf Pdiss / leakage issues

RLC Lossy Match

- Simple/lumped design - output optimized for Zopt - Input optimized for gain - All-pass network at input implies excellent S11

- Lumped circuit, so flatness thermal design is critical

Distributed Amp - best bandwidth and gain - dissipation spread out - Zload optimization for each cell is complicated - poor efficiency - implementation feasibility issues

Internal Design Match Topology and Design

Input Match options as shown above
Use standard DOE design principles

Output no matching
Provides most flexibility Takes advantage of GaN high impedances
Max Gain (dB) Max Gain (dB)
18 17 16 15 14 13 12 freq, GHz

dB(SParam_PassiveMatch_PE1D278C..S(1,1)) dB(SParam_PassiveMatch_PE1D278B..S(1,1)) dB(SParam_PassiveMatch_PE1D278A..S(1,1)) dB(SParam_PassiveMatch_PE1D2789..S(1,1))

SParam_PassiveMatch_SE1D278C..MaxGain1 SParam_PassiveMatch_SE1D278B..MaxGain1 SParam_PassiveMatch_SE1D278A..MaxGain1 SParam_PassiveMatch_SE1D2789..MaxGain1

-5 -10 -15 -20 -25 -30

7 Passive Model, S11 (dB) Input Return Loss, S11

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

-35 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 freq, GHz

Internal Design Simulation Methodology

Design Methodology Design/Simulate Input circuitry

Assume Ideal Match (choose load impedance)

Practical Output Matching

Transformer Balun

Lumped Element

Design Example 45W, 20-1000MHz

25 20
dB(S(2,1))

50 47
Output Power (dBm)

80 70
Gain (dB), PAE (%)

0
dB(S(2,2)) dB(S(1,1))

44 41 38 35 32 29 26 14 17 20 23 Pin (dBm) 26 29 32

60 50 40 30 20 10 0

15 10 5 0 0.0

-5 -10 -15 -20 2.0

0.5

1.0 freq, GHz

1.5

Uses 6.6mm device periphery Designed for 25 source and load impedance frequency target is 20-1000MHz Multi-chip module approach with GaAs passive die and GaN HEMT active die. Minimizes SiC die area as the matching circuits are large at low GHz frequencies and below.

Performance Vdq = 50V, Idq = 130mA Bandwidth: 20 1000 MHz Gain: 17.51 dB Input return loss: < 11 dB Output power: 50.3 W at 512 MHz PAE: 70% at 512 MHz

Balun Matching

Two 25W matched unit amplifiers are combined together. Broadband 45W amplifiers are first designed for operating in a 25W system. Two such PAs are combined using a broadband 1:1 Balun at input and output to convert the differential 25W impedance to a 50W system. Gate bias feeds isolated through a resistor, and connected together. The high-Q bias feed inductors at drain of each device are connected together. 300W ferrite (at 100 MHz) at the drain bias feed to extend low frequency performance.

Balun Design
Broadband coiled balun is formed by winding a rigid coax around a ferrite rod Coiling increases self-inductances and the ferrite improves low frequency cut-off Advances in low-loss ferrites make them suitable for GHz range A 43 material ferrite rod from Fair-Rite Corp with 5mm diameter is used - provides high permeability at low frequency and low loss at high frequency 50 coax with 0.22dB/ft loss, that can handle 124W at 500MHz is used The center and outer conductor are connected to unbalanced signal and ground at one end and to the differential balanced signal at the other. The ferrite forces equal and opposing current at the inner and outer conductor and isolates the 180 signal from the input ground at low frequency

For high frequency isolation the coax length is quarter wave long at the upper cut-off frequency. This results in a 4 turn coil for the chosen ferrite diameter.

Balun Performance

Measured performance Insertion loss (back-back) : 0.34 dB Insertion loss per balun : 0.17 dB Return loss: better than 20 dB

90W PA Module CW Performance

Vdq = 50V, Idq = 265mA

Frequency: 100 1000 MHz Gain over band: 15.1 16.3 dB Output power: 82 107.5 W Efficiency: 51.9 73.8 %

Design Example 80W Module, 100-800MHz

Output Power
55 54 53 52 51 50 49 48 47 46 45
0.0 1.0E8 2.0E8 3.0E8 4.0E8 5.0E8 6.0E8 7.0E8 8.0E8 9.0E8 1.0E9 1.1E9 1.2E9

Small Signal Sweep 18 17

dB(S(2,1))

0 -5 -10 -15 -20 -25 -30 -35

0.3 0.5 freq, GHz 0.7 0.9 1.0

Pout (dBm)

16 15 14 13 12 11
0.1

dB(S(2,2)) dB(S(1,1))

RFfreq

Uses 15.5mm device periphery designed for 50W source, 12.5W load impedance frequency target is 100-800MHz Multi-chip module approach with GaAs passive die and GaN HEMT active die. Minimizes SiC die area as the matching circuits are large at low GHz frequencies and below.

Simulated Performance Vdq = 48V, Idq = 300mA Frequency: 100 800 MHz Gain: 111 dB Input return loss: < 11 dB Output power: 80W across the band PAE: >50% across the band

Transformer Matching

Single 50W matched amplifier Broadband 80W amplifier is designed for operating with a 50W input impedance. Amplifier is designed based on ideal 12.5W output impedance. The challenge is to create this impedance The PA drives a broadband 4:1 transformer to convert the 12.5W impedance to a 50W system.

Transformer Match

XMB0220B5050 Features:
30-1000 MHz 4:1 Transformer (50 to 12.5 ) Broadband Defense Applications High Power > 100W Very Low Loss < 0.5dB

80W PA Module CW Performance

Vdq = 48V, Idq = 300mA (class-AB) Performance Frequency: 100 800 MHz Gain: >10dB Input return loss: <-12 dB Output power: 80W Efficiency: 52.5 57.7%

Design Example Unmatched FETs

Lumped Element Match

Single 50W matched amplifier Broadband design generally hitting target impedances. The challenge is to create this impedance Determine Target Impedances
Z0= 10

Actual impedance from loadpull Non-linear model simulation results

Wirebond model
Efficiency 2.0GHz Pin = 35dBm
4

60 52

48

Z0(gamma_ld1_imag)

56

54

60

64
2

52

50

64
1

54

60
0

60
52

5648

Unit Cells with manifold model

46

56 50

50 56 48
4 5 6 7 8 Z0(gamma_ld1_real) 9 10

-1

Package Model 11

Eff Meas

Eff Sim

Data Point

Lumped Element Topology

L+C Match

uStrip+C Match
strip

strip

strip

Q=1. 0

VSWR=1. 7

30W PA Module 700-2400MHz Simulations

Simulated Performance Frequency: 700 2400 MHz Gain: >10dB Input return loss: <-12 dB Output power: 30W Efficiency: >25%

Output Impedance S11 Match to 50

30W PA Module CW Performance

2.0pF

0.4pF

1.0pF 2.7pF

Performance Frequency: 700 2400 MHz Gain: >10dB Input return loss: <-12 dB Output power: 30W Efficiency: >28%

Combination Matching

Two 25W matched unit amplifiers are combined together.

Broadband 100W peak power amplifiers are first designed for operating in a 6.25W system. Two such PAs are combined using a broadband 4:1 Transformer followed by a balun to convert the differential 25W impedance to a 50W system. Gate bias feeds isolated through a resistor, and connected together.

The high-Q bias feed inductors at drain of each device are connected together.

100W PA Module 30-512MHz Simulations

Freq (MHz)

Pin (W)

Zload

Zs

PAE (%)

Pdel (W)

30 65
100 225 380 512

31 31
31 31 31 31

7+j0 8+j0
7+j0 8.4 +j 0 7+j1 7+j3

13 + j 4.7 9+j9
9 + j 7.4 7+j6 2 + j 4.1 2.6 +j 2.7

41 43.6
44 50 52 55

52 51.7
52 52 52.5 52

Design Target Frequency: 30 512 MHz Gain: >16dB Input return loss: <-7 dB Output power: 100W PEP Efficiency: >18%

Determine Target Impedances

Actual impedance from loadpull Non-linear model simulation result

Notice Zload is almost purely real at 7-8

This drives 4:1 topology at 6.25 per side

100W PA Module 30-512MHz Simulations

Simulated Performance Frequency: 30 512 MHz Gain: >16dB Input return loss: <-7 dB Output power: 100W PEP Efficiency: >18%

100W PA Module 2-tone Performance

Performance Frequency: 30 700 MHz Gain: >16dB Input return loss: <-7 dB Output power: 100W PEP Efficiency: >18%

Summary

Emerging SDR architectures require wideband, high power amplifiers with high efficiency, compact size and low cost GaN-on-SiC technology adoption continues for high power commercial and military applications Demonstrations include:
90W (dual device module), 1001000 MHz, >51% drain efficiency 80W (single device), 100-800MHz, >51% drain efficiency 30W (single device), 700-2400MHz, >28% drain efficiency

100W peak power (dual device), 30-700MHz, >18% drain efficiency