Bi Bo Co

Mn Th Ngim K Thut S
Trng i hc Bch Khoa TP HCM
TP.HCM --- 2013
Nhm 3

Khoa: in-in T
Thnh vin nhm:
H V Tn:

MSSV

1. Tn Tht Nguyn Phong41102555

2. L Quang Sn......41102924

Bi th nghim 1
Switches, Lights, Multiplexers
1.Thnghim1.1:
Thc hin mch th nghim c ng vo l 10 cng tc SW 90 , v ng ra l 10 n LED mu
LEDR 90 dng c trng thi ca cc ng vo.

Cc bc cn thc hin:

1. To project mi.
2. Vit chng trnh Verilog cho bi TN
3. Gn chn & bin dch project.
4. Np project vo kit TN. Th mch.

Chng trnh ca nhm:

module TN1_1 (SW, LEDR);
input [9:0] SW;
output [9:0] LEDR;
assign LEDR = SW;
endmodule

pg. 1

2.Thnghim1.2:
Cho mch multiplexer 2 sang 1 nh hnh 2 vi ng vo chn knh s. Nu s = 0 ng ra m
s bng ng vo x, v nu s = 1 th ng ra m = y.
x

m
s
y

a) S mch
s
s

0
1

x
y

x
y

b) Bng s tht

c) K hiu

Hnh 2. Mch multiplexer 2

sang 1. Mch c th m t dng m Verilog nh sau:
assign m = ( s&x) (s& y);
Dng 4 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 2 sang 1 - 4 bit nh
hnh 3a. Mch c 2 ng vo nh phn 4 bit X v Y, v ng ra 4 bit M. Nu s = 0 th M = X ,
cn s = 1 th M = Y.
s

x3
y3

X3

Y3

m3

m2

1
4

x0

y0

m0

pg. 2

Cc bc cn thc hin:
1. To project mi.
2. Vit chng trnh Verilog vi:
i. s = SW9 v ni vi LEDR9
ii. X = SW3-0 v ni vi LEDR3-0
iii. Y = SW7-4 v ni vi LEDR7-4
iv. M = LEDG3-0

2. Gn chn
3. Bin dch project.
4. Np project vo kit TN.
5. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .

Chng trnh ca nhm:

module TN1_2(SW,LEDR,LEDG);
input [9:0]SW;
output [9:0]LEDR;
output [3:0]LEDG;
assign LEDR=SW;
Mux21(SW[9],SW[0],SW[4],LEDG[0]);
Mux21(SW[9],SW[1],SW[5],LEDG[1]);
Mux21(SW[9],SW[2],SW[6],LEDG[2]);
Mux21(SW[9],SW[3],SW[7],LEDG[3]);
endmodule
module Mux21(S,X,Y,M);
input S,X,Y;
output M;
assign M=(~S&X)|(S&Y);
endmodule

pg. 3

3.Thnghim1.3:
Dng 3 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 4 sang 1
nh hnh 4a.
Mch c 4 ng vo u, v, w v x; 1 ng ra m; 2 ng vo chn knh s1 s0

Tng t dng 2 mch multiplexer 4 1 nh hnh 4a thc hin mch

multiplexer 4 1 - 2 bit nh hnh 5
s1
s0

u
v

w
x

a) s mch

s1 s0

0
0
1
1

u
v
w
x

0
1
0
1

s1
s0
u
x
v
w

00
01
10
11

b) bng s tht

c) k hiu
Hnh 4. Mch multiplexer 4 sang 1

Cc bc cn thc hin:
1. To project mi.
2. Vit chng trnh Verilog vi:
s 1 s 0 = SW9-8 v ni vi LEDR9-8
U-X = SW7-0 v ni vi LEDR7-0
M = LEDG1-0
3. Gn chn
4. Bin dch project.
5. Np project vo kit TN.
6. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .

pg. 4

Chng trnh ca nhm:

module TN1_3(SW,LEDR,LEDG);
input [9:0]SW;
output [9:0]LEDR;
output [1:0]LEDG;
assign LEDR=SW;
Mux41(SW[8],SW[9],SW[0],SW[2],SW[4],SW[6],LEDG[0]);
Mux41(SW[8],SW[9],SW[1],SW[3],SW[5],SW[7],LEDG[1]);
endmodule
module Mux41(S0,S1,U,V,W,X,M);
input S0,S1,U,V,W,X;
output M;
wire t1,t0;
Mux21(S0,U,V,t0);
Mux21(S0,W,X,t1);
Mux21(S1,t0,t1,M);
endmodule
module Mux21(S,X,Y,M);
input S,X,Y;
output M;
assign M=(~S&X)|(S&Y);
endmodule

pg. 5

4.Thnghim1.4:
Thc hin b gii m c 2 ng vo c1 c0 v 7 ng ra t 0 n 6 dng hin th cc k t
trn b hin th 7 on nh hnh 6.
Bng 1 lit k cc k t cn hin th (gm H,E,L v k t O) tng ng vi
cc ng vo c1 c0 . Cc ng ra tch cc mc logic 0.

0
5
7-segment
decoder

c1
c0

1
2

Hnh 6. B gii m
7 on
c1 c0

K t

00
01
10
11

H
E
L
O

Bng 1. Bng m ch

Cc bc cn thc hin:
1. To project mi.
2. Vit chng trnh Verilog vi:
o Cc ng vo c1 c0 ni vi cc cng tc SW1-0
o Cc ng ra 0 6 ni vi HEX00, HEX01..HEX06
3. Gn chn
4. Bin dch project.
5. Np project vo kit TN.
6. Th mch bng cch thay i cc cng tc SW10 ri quan st b hin th 7 on.

pg. 6

Chng trnh ca nhm:

module TN1_4(SW,HEX0);
input [1:0]SW;
output [6:0]HEX0;
reg [6:0] HEX0;
always @ (SW[1:0])
begin
case (SW[1:0])
2'b00: HEX0= 7'b0001001;
2'b01: HEX0= 7'b0000110;
2'b10: HEX0= 7'b1000111;
2'b11: HEX0= 7'b1000000;
default: HEX0= 7'b1111111;
endcase
end
endmodule

pg. 7

5.Thnghim1.5:
Thc hin mch in hin th ch xoay nh hnh 7 hot ng theo bng 2.
Cc cng tc SW 70 dng to k t v SW 98 dng chn k t hin th.

SW9
SW8
SW7 6

SW5 4

SW3 2

SW1 0

0
00
01
10

7-segment
decoder

1
2

Hnh 7. Mch c th chn & hin th 1 trong 4 k t.

SW9 SW8
0
0
1
1

0
1
0
1

Hin th
H
E
L
O

Bng 2. Hin th ch xoay HELLO.

Cc bc cn thc hin:
1. To project mi.
2. Vit chng trnh Verilog vi:
3. Gn chn
4. Bin dch project.
5. Np project vo kit TN.
6. Th mch bng cch thay i cc cng tc SW10 ri quan st b hin th 7 on.

Chng trnh ca nhm:

module TN1_5(SW,HEX0,HEX1,HEX2,HEX3);
input [9:0]SW;
output [6:0]HEX0;
output [6:0]HEX1;
output [6:0]HEX2;
output [6:0]HEX3;
pg. 8

wire [1:0]A,B,C,D;
Mux412b(SW[9:8],SW[1:0],SW[7:6],SW[5:4],SW[3:2],A);
Mux412b(SW[9:8],SW[3:2],SW[1:0],SW[7:6],SW[5:4],B);
Mux412b(SW[9:8],SW[5:4],SW[3:2],SW[1:0],SW[7:6],C);
Mux412b(SW[9:8],SW[7:6],SW[5:4],SW[3:2],SW[1:0],D);
ganchu(A,HEX0);
ganchu(B,HEX1);
ganchu(C,HEX2);
ganchu(D,HEX3);
endmodule
module Mux412b(S,U,V,W,X,M);
input [1:0]S,U,V,W,X;
output [1:0]M;
Mux41(S[0],S[1],U[0],V[0],X[0],W[0],M[0]);
Mux41(S[0],S[1],U[1],V[1],X[1],W[1],M[1]);
endmodule
module Mux41(S0,S1,U,V,W,X,M);
input S0,S1,U,V,W,X;
output M;
wire t1,t0;
Mux21(S0,U,V,t0);
Mux21(S0,W,X,t1);
Mux21(S1,t0,t1,M);
endmodule
module Mux21(S,X,Y,M);
input S,X,Y;
output M;
assign M=(~S&X)|(S&Y);
endmodule
pg. 9

module ganchu(S,HE);
input [1:0]S;
output [6:0]HE;
reg [6:0] HE;
always @ (S[1:0])
begin
case (S[1:0])
2'b00: HE= 7'b0001001;
2'b01: HE= 7'b0000110;
2'b10: HE= 7'b1000111;
2'b11: HE= 7'b1000000;
default: HE= 7'b1111111;
endcase
end
endmodule

pg. 10

Bi th nghim 2
Numbers & Displays
y l bi th nghim thit k mch t hp thc hin b bin i s nh phn sang s
thp phn v mch cng hai s BCD.
1.Th nghim2.1:
Dng cc n 7 on HEX1 v HEX0 hin th cc s thp phn t 0 n 9. Gi tr hin
th thay i c bng cc cng tc S W 74 v S W 30 tng ng.
Cc bc cn thc hin:
1. To project mi.
2. Vit chng trnh Verilog cho bi TN
3. Gn chn & bin dch project.
4. Np project vo kit TN. Th mch bng cch thay i cc cng tc v quan st cc
n hin th.
Chng trnh ca nhm:
module TN2_1(SW,LEDR,HEX0,HEX1);
input [7:0]SW;
output [6:0]HEX0,HEX1;
output [7:0]LEDR;
assign LEDR=SW;
ganso (SW[3:0],HEX0);
ganso (SW[7:4],HEX1);
endmodule
module ganso(S,M);
input [3:0]S;
output [6:0]M;
reg [6:0]M;
always@(S[3:0])
case(S[3:0])
4'b0000: M=7'b1000000;
4'b0001: M=7'b1001111;
4'b0010: M=7'b0100100;
4'b0011: M=7'b0110000;
pg. 11

4'b0100: M=7'b0011001;
4'b0101: M=7'b0010010;
4'b0110: M=7'b0000010;
4'b0111: M=7'b1111000;
4'b1000: M=7'b0000000;
4'b1001: M=7'b0010000;
default: M=7'b1111111;
endcase
endmodule

2.Th nghim2.2:
Thc hin 1 phn ca mch chuyn i s nh phn 4 bit V = v 3 v2 v1 v0 thnh s thp phn
D = d1 d0 n h hnh 1, b n g 1. Mch bao gm mch so snh ( kim tra V > 9), mch
multiplexer v mch A (cha cn thc hin mch B v b gii m 7 on). Mch s c ng
vo V 4 bit, ng ra M 4 bit v ng ra z.
Binary value

Decimal digits

0000
0001
0010
...

0
0
0
...

1001
1010
1011
1100
1101
1110
1111

0
1
1
1
1
1
1

0
1
2
..
.
9
0
1
2
3
4
5

Bng 1. Bng gi tr chuyn i nh phn thp phn.

Cc bc cn thc hin:
1. To project mi. Vit chng trnh
2. Bin dch project v thc hin m phng
3. Vit thm on chng trnh cho mch B v mch gii m 7 on. Dng cc
cng tc S W30 nhp s nh phn V v cc n 7 on HEX1, HEX0
hin th s thp phn d 1 d0
4. Bin dch li ri np project vo kit TN.
5. Th mch: thay i gi tr V v quan st cc n hin th.

pg. 12

d1
z

Comparator
Circuit B

4
v3

m3

1
2

d0
v2

m2

0
7-segment
decoder

4
v1

v0

m1

m0

1
2

Circuit A

Chng trnh ca nhm:

Hnh 1. Mch chuyn i nh phn-thp phn.

module TN2_2(SW,LEDR,HEX0,HEX1);
input [3:0]SW;
output [3:0]LEDR;
output [6:0]HEX0,HEX1;
assign LEDR=SW;
wire [3:0]M,N;
ss4bvoi9(SW,M,N);
ganso(M,HEX0);
ganso(N,HEX1);
endmodule
module ss4bvoi9(B,M,N);
pg. 13

input [3:0]B;
output [3:0]M,N;
reg [3:0]M;
reg [3:0]N;
always@(B[3:0] or M or N)
if (B[3:0]<=4'b1001)
begin M=B;
N=4'b0000; end
else
begin M=B+4'b0110;
N=4'b0001; end
endmodule
module ganso(S,M);
input [3:0]S;
output [6:0]M;
reg [6:0]M;
always@(S[3:0])
case(S[3:0])
4'b0000: M=7'b1000000;
4'b0001: M=7'b1001111;
4'b0010: M=7'b0100100;
4'b0011: M=7'b0110000;
4'b0100: M=7'b0011001;
4'b0101: M=7'b0010010;
4'b0110: M=7'b0000010;
4'b0111: M=7'b1111000;
4'b1000: M=7'b0000000;
4'b1001: M=7'b0010000;
default: M=7'b1111111;
endcase
endmodule
pg. 14

3.Thnghim2.3:
Cho mch cng ton phn (FA) nh hnh 2a v i c c n g v o a, b, and ci , c c ng ra s v
co .
c o s = a + b + ci .
Dng 4 mch cng FA nh trn thc hin mch cng 4 bit nh hnh 2d.
Ci
s

ci

a
b

a) Mch cng FA

b a ci

co s

0
0
0
0
1
1
1
1

0
0
0
1
0
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

c) Bng s tht

b3

a3

FA

c out s S3
C

co

co

FA

b) K hiu

c3

b2

a2

c2

FA

b1

a1

c1

b0

FA

s2

a0

c in

FA

s1

s0

d) Mch cng 4 bit

Hnh 2. Mch cng.

Cc bc cn thc hin:
1. To project mi v vit chng trnh Verilog cho mch cng:

Ni cc ng vo A, B v cin vi cc cng tc tng ng S W 74 , S

W 30 v S W8 v vi cc n LED mu LEDR

Ni cc ng ra c out v S vi cc n LED mu xanh LEDG

2. Gn chn, bin dch v np project vo kit TN

3. Th mch bng cch thay i cc gi tr khc nhau ca A, B v c in, quan st cc n
hin th.

pg. 15

Chng trnh ca nhm:

module TN2_3(SW,LEDR,LEDG);
input [8:0]SW;
output [8:0]LEDR;
output [4:0]LEDG;
assign LEDR=SW;
wire [3:1]c;
wire [2:0]s;
FA(SW[4],SW[0],SW[8],c1,LEDG[0]);
FA(SW[5],SW[1],c1,c2,LEDG[1]);
FA(SW[6],SW[2],c2,c3,LEDG[2]);
FA(SW[7],SW[3],c3,LEDG[4],LEDG[3]);
endmodule
module FA(a,b,ci,co,s);
input a,b;
input ci;
output co;
output s;
assign s = a^b^ci;
Mux21(a^b,b,ci,co);
endmodule
module Mux21(S,X,Y,M);
input S,X,Y;
output M;
assign M=(~S&X)|(S&Y);
endmodule

pg. 16

4.Thnghim2.4:
Thc hin mch cng 2 s BCD. Ng vo ca mch l 2 s A, B v ng vo cho s nh cin .
Ng ra l s BCD, tng S1 S0 v s nh c out.
Cc bc cn thc hin:
1. To project mi cho mch cng s BCD. Phi thc hin mch cng 2 s 4 bit A, B
(th nghim 2.3)
v 1 mch chuyn i 5 bit tng s3s2s1s0co thnh 2 s BCD S1 S0 (th nghim 2.2)
2. Vit chng trnh Verilog:
Ni cc ng vo A, B v cin vi cc cng tc tng ng S W 74 , S W 30
v S W8 v vi cc n LED mu LEDR70
Ni cc ng ra c out v S vi cc n LED mu xanh LEDG40
Dng cc n 7 on HEX3, HEX2 hin th gi tr ca 2 s A v B v
HEX1, HEX0 hin th kt qu S1 S0 .
3. Gn chn, bin dch v np project vo kit TN
4. Th mch bng cch thay i cc gi tr khc nhau ca A, B v c in, quan st cc n
hin th.

Chng trnh ca nhm:

module TN2_4(SW,LEDR,LEDG,HEX0,HEX1,HEX2,HEX3);
input [8:0]SW;
output [4:0]LEDG;
output [9:0]LEDR;
output [6:0]HEX0,HEX1,HEX2,HEX3;
wire [4:0]a;
assign LEDR=SW;
assign a[4:0] = SW[7:4] + SW[3:0] + SW[8];
assign LEDG = a;
reg [3:0]c;
reg [3:0]b;
always @ (a or c or b)
if (a <5'b01010)
begin c = a;
b = 4'b0000; end
else if (a<5'b10100)
begin c = a + 4'b0110;
pg. 17

b = 4'b0001; end
else if (a<5'b11110)
begin c = a + 4'b1100;
b = 4'b0010; end
else begin c=4'b0000;
b= 4'b0011;end
ganso(SW[7:4],HEX3);
ganso(SW[3:0],HEX2);
ganso(b,HEX1);
ganso(c,HEX0);
endmodule
module ganso(S,M);
input [3:0]S;
output [6:0]M;
reg [6:0]M;
always@(S[3:0])
case(S[3:0])
4'b0000: M=7'b1000000;
4'b0001: M=7'b1001111;
4'b0010: M=7'b0100100;
4'b0011: M=7'b0110000;
4'b0100: M=7'b0011001;
4'b0101: M=7'b0010010;
4'b0110: M=7'b0000010;
4'b0111: M=7'b1111000;
4'b1000: M=7'b0000000;
4'b1001: M=7'b0010000;
default: M=7'b1111111;
endcase
endmodule

pg. 18

5.Thnghim2.5:
Thit k mch t hp chuyn i 1 s nh phn 6 bit thnh s thp phn di dng 2 s BCD.
Dng cc cng tc
S W 50 nhp s nh phn v cc n 7 on HEX1 v HEX0 hin th s thp phn.
Chng trnh ca nhm:
module TN2_5(SW,LEDR,HEX0,HEX1);
input [5:0]SW;
output [9:0]LEDR;
output [6:0]HEX0,HEX1;
wire [5:0]a;
assign LEDR=SW;
assign a[5:0] = SW[5:0];
reg [5:0]c;
reg [5:0]b;
always @ (a or c or b)
if (a <6'b001010)
begin c = a;
b = 6'b000000; end
else if (a<6'b010100)
begin c = a + 6'b00110;
b = 6'b000001; end
else if (a<6'b011110)
begin c = a + 6'b001100;
b = 6'b000010; end
else if (a<6'b101000)
begin c = a + 6'b010010;
b = 6'b000011; end
else if (a<6'b110010)
begin c = a + 6'b011000;
pg. 19

b = 6'b000100; end
else if (a<6'b111100)
begin c = a + 6'b011110;
b = 6'b000101; end
else begin c=a + 6'b100100;
b= 6'b000110;end
ganso(b,HEX1);
ganso(c,HEX0);
endmodule
module ganso(S,M);
input [3:0]S;
output [6:0]M;
reg [6:0]M;
always@(S[3:0])
case(S[3:0])
4'b0000: M=7'b1000000;
4'b0001: M=7'b1001111;
4'b0010: M=7'b0100100;
4'b0011: M=7'b0110000;
4'b0100: M=7'b0011001;
4'b0101: M=7'b0010010;
4'b0110: M=7'b0000010;
4'b0111: M=7'b1111000;
4'b1000: M=7'b0000000;
4'b1001: M=7'b0010000;
default: M=7'b1111111;
endcase
endmodule
pg. 20

Bi th nghim 3
Latches, Flip-flops, Registers
1.Thnghim3.1:
Hnh 1 m t mch RS latch dng cng logic.
C 2 cch dng Verilog m t mch ny: dng cng logic (hnh 2a) v dng cng thc
logic (hnh 2b).
R

R_g
Qa (Q)

Clk
Qb
S_g

Hnh 1. Mch RS latch dng cng logic.

// A gated RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
and (R_g, R, Clk);
and (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule
Hnh 2a. Dng cng logic m t mch RS latch.
// A gated RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
assign R_g = R & Clk;
assign S_g = S & Clk;
assign Qa =

(R_g Qb);

assign Qb =

(S_g Qa);

assign Q = Qa;
endmodule
Hnh 2b. Dng cng thc logic m t mch RS latch.
pg. 21

C 2 cch thc hn: dng 1 LUT 4 ng vo (hnh 3a) v dng 4 LUT 2 ng vo (hnh 3b).
Qa (Q)

Clk
4-LUT

(a) RS latch ch dng 1 bng tham chiu 4 ng vo.

R_g

Qa (Q)

4-LUT

4-LUT

Clk
S_g
4-LUT

4-LUT

Qb

(b) RS latch dng 4 bng tham chiu 2 ng vo.

Hnh 3. Cc cch thc hin mch RS latch

Cc bc cn thc hin:
1. To project RS latch
2. Vit chng trnh Verilog theo hai cch 2a v 2b.
3. Bin dch. Dng tin ch RTL Viewer so snh vi s mch hnh 1. Dng tin
ch Technology Viewer so snh vi s mch hnh 3b.
4. To Vector Waveform File (.vwf) cho cc ng vo/ra. To dng sng cho cc
ng vo R v S ri dng tin ch Quartus II Simulator quan st cc dng sng
R_g, S_g, Qa v Qb

Chng trnh ca nhm:

module TN3_1(Clk,R,S,Q);
input Clk,R,S;
output Q;
wire R_g,S_g,Qa,Qb;
and (R_g,R,Clk);
and (S_g,S,Clk);
nor (Qa,R_g,Qb);
nor (Qb,S_g,Qa);
assign Q=Qa;
endmodule

pg. 22

2.Thnghim3.2:
Cho mch D latch dng cng nh hnh 4.
D

S_g
Qa (Q)

Clk
Qb
R

R_g

Hnh 4. Mch D latch dng cng logic.

Cc bc cn thc hin:
1.
2.
3.
4.
5.
6.

To project mi vi chng trnh Verilog dng 2b cho mch D latch.

Bin dch chng trnh. Dng tin ch Technology Viewer kho st mch.
M phng kim tra hot ng ca mch.
Dng cng tc SW0 cho ng vo D, v SW1 cho ng vo Clk. Ni ng ra Q n LEDR0.
Bin dch chng trnh li v np project vo kit TN.
Th mch bng cch thay i cc ng vo D, Clk v quan st ng ra Q.

Chng trnh ca nhm:

module TN3_2(SW,LEDR,LEDG);
input [1:0]SW;
output [1:0]LEDG,LEDR;
assign LEDR=SW;
wire S,R,R_g,S_g,Qa,Qb;
assign S=SW[0];
not (R,SW[0]);
nand (S_g,S,SW[1]);
nand (R_g,R,SW[1]);
nand (Qa,S_g,Qb);
nand (Qb,R_g,Qa);
assign LEDG[0]=Qa,LEDG[1]=Qb;
endmodule

pg. 23

3.Thnghim3.3:
Cho mch master-slave D flip-flop hnh 5.
Master
D

Clock

Clk Q

Slave
Qm

Clk Q

Qs

Q
Q

Hnh 5. Mch master-slave D flip-flop.

Cc bc cn thc hin:
1. To project mi dng 2 D flip-flop ca th nghim 3.2.
2. Dng cng tc SW0 cho ng vo D, v SW 1 cho ng vo Clk. Ni ng ra Q n LEDR0.
3. Bin dch chng trnh.
4. Dng tin ch Technology Viewer kho st mch. M phng kim tra hot ng
ca mch.
5. Th mch bng cch thay i cc ng vo D, Clk v quan st ng ra Q.

Chng trnh ca nhm:

module TN3_3(SW,LEDG,LEDR);
input [1:0] SW;
output [1:0] LEDR,LEDG;
assign LEDR=SW;
wire t1,t0;
Dlatch1(SW[0],~SW[1],t1,t0);
Dlatch1(t1,SW[1],LEDG[0],LEDG[1]);
endmodule
module Dlatch1(D,Clk,Q,Q0);
input Clk,D;
output Q,Q0;
wire S,R,R_g,S_g,Qa,Qb;
assign S=D;
not (R,D);
nand (S_g,S,Clk);
nand (R_g,R,Clk);
nand (Qa,S_g,Qb);
nand (Qb,R_g,Qa);
assign Q=Qa,Q0=Qb;
endmodule
pg. 24

4.Thnghim3.4:
Cho mch in hnh 6 vi D latch, D flip- flop kck cnh ln v D flip- flop kck cnh xung.
D
Clock

Qa

Clk Q

Qb

Qb

Qc

Qc

(a) S mch
Clock
D
Qa
Qb
Qc

(b) Gin d thi gian

Hnh 6. S mch v dng sng ca th nghim 3.4.
Cc bc cn thc hin:
1.
2.
3.
4.
5.

To project mi.
Vit chng trnh da trn on chng trnh gi nh hnh 7.
Bin dch chng trnh.
Dng tin ch Technology Viewer kho st mch.
M phng kim tra hot ng ca mch. So snh hot ng ca cc phn
t trong mch.
pg. 25

Chng trnh ca nhm:

module TN3_4(SW,LEDG,LEDR);
input [1:0] SW;
output [2:0] LEDG,LEDR;
assign LEDR=SW;
Dlatch1(SW[0],SW[1],LEDG[0]);
Dflipflop(SW[0],SW[1],LEDG[1]);
Dflipflop(~SW[0],SW[1],LEDG[2]);
endmodule
module Dflipflop(Clk,D,Q);
input Clk,D;
output Q;
wire t1;
Dlatch1(~Clk,D,t1);
Dlatch1(Clk,t1,Q);
endmodule
module Dlatch1(Clk,D,Q);
input Clk,D;
output reg Q;
always @(Clk,D)
if (Clk) Q=D;
endmodule

pg. 26

Bi th nghim 4
Counters
1. Thnghim4.1:
Cho mch m ng b 4 bit dng 4 T flip-flops nh hnh 1.

Enable
Clock

Q
Q

Q
Q

Q
Q

Clear

Hnh 1. B m 4 bit.
Cc bc cn thc hin:
1. To project mi thc hin b m 16 bit dng 4 mch m nh hnh 1. Bin dch
chng trnh. Ghi nhn s phn t logic (LEs) c dng? Tn s hot ng ti a
(Fmax) ca mch m l bao nhiu?
2. M phng hot ng ca mch.
3. Gn thm nt nhn KEY0 lm ng vo Clock, cc cng tc S W 1, S W 0 lm ng vo
Enable, Reset v cc n 7 on HEX3-0 hin th gi tr thp lc phn ca ng ra
mch m.
4. Bin dch li v np project vo kit TN.
5. Th hot ng ca mch bng cch thay i cc cng tc v quan st cc n 7 on.
6. Thc hin mch m 4 bit ri dng tin ch RTL Viewer quan st mch v so snh vi
mch in hnh 1.

Chng trnh ca nhm:

moduleTN4_1(SW,LEDR,LEDG);
input [1:0]SW;
output [3:0]LEDR,LEDG;
assign LEDR=SW;
wire Q0,Q1,Q2,Q3,T1,T2,T3;
Tflipflop(SW[0],SW[1],Q3);
and (T1,Q3,SW[1]);
Tflipflop(SW[0],T1,Q2);
and (T2,Q2,T1);
Tflipflop(SW[0],T2,Q1);
and (T3,Q1,T2);
Tflipflop(SW[0],T3,Q0);
pg. 27

assign LEDG[3]=Q0,LEDG[2]=Q1,LEDG[1]=Q2,LEDG[0]=Q3;
endmodule
module Tflipflop(Clk,T,Q);
input T,Clk;
output Q;
wire D;
xor (D,T,Q);
Dflipflop(Clk,D,Q);
endmodule
module Dflipflop(Clk,D,Q);
input D,Clk;
output Q;
wire t1;
Dlatch1(~Clk,D,t1);
Dlatch1(Clk,t1,Q);
endmodule
module Dlatch1(Clk,D,Q);
input Clk,D;
output Q;
wire S,R,R_g,S_g,Qa,Qb;
assign S=D;
not (R,D);
nand (S_g,S,Clk);
nand (R_g,R,Clk);
nand (Qa,S_g,Qb);
nand (Qb,R_g,Qa);
assign Q=Qa;
endmodule

2.Thnghim4.2:
Thc hin li th nghim 4.1 dng m Verilog sau:
Q <= Q + 1;
Bin dch chng trnh.
So snh s phn t logic (LEs) c dng, tn s hot ng ti a (Fmax)
ca mch m. Dng RTL Viewer kho st v nhn xt nhng khc bit
so vi th nghim 4.1.

pg. 28