A Flexible ADC Approach for Mixed-signal SoC Platforms

Athon Zanikopoulos, Pieter Harpe, Hans Hegt and Arthur van Roermund
Mixed-signal Microelectronics Group, Eindhoven University of Technology, Eindhoven, The Netherlands, email: a.zanikopoulos@tue.nl

Abstract Time-to-market pressure and increased design complexity created what is called a design gap [1] in the design of systems-on-chip (SoC). As a solution to that problem the Platform-Based Design (PBD), based on the design-reuse methodology, has been proposed [2], and successfully applied to digital systems. However, nowadays, the analog part of SoC does not take advantage of PBD and therefore dominates the overall design time, cost and risk. In this paper we propose a Mixed-signal FPGA (FPMA) platform as a solution to the problems described above. Specically, we address the feasibility of a exible reprogrammable/recongurable ADC platform based on the pipelined architecture. We discuss the programmability issues with respect to the performance-exibility trade-offs, we justify our decisions and we demonstrate several possible ADC architectures.

I. I NTRODUCTION Every year IC technology provides a higher transistor density, increasing approximately with 60% per year. The designers cannot keep pace with that because the design efciency (engineering skills, productivity of tools and methods) is increasing with only approximately 20% per year [1]. Furthermore, time-to-market pressure and cost of ownership of masks drives us to more disciplined design styles, employing design reuse from gate level up to IP block level. However, as the complexity of the IC designs increases continuously (above 100million transistors) and time-to-market becomes even more important, a new, more advanced and abstract, reuse methodology becomes imperative. Therefore, as a natural progression of this line of thinking, the PlatformBased Design (PBD) has been proposed [3]. It is a new design reuse methodology based on architecture reuse. A platform is a library of components that can be assembled to generate a design at that level of abstraction. We call a platform instance a set of components that are selected from the library and whose parameters are set. Platforms allow design reuse from the functional level down to the circuit and layout level and, nally, real hardware level reuse. We can address the FPGAs (Field-Programmable Gate Arrays) as the most successful example of a platform that includes full hardware reuse. FPGAs are digital systems and the physical layer can be decoupled from the functional layer. In parallel with the design reuse methodology evolution, the recent rapid progress of integrated circuit technology allows the integration of a whole System on a single Chip. The
The work is sponsored by Stichting Technische Wetenschappen.

SoC trend nally implies the single-chip integration of analog and digital functions. Especially with the rise of the Personal Internet Products (PIPs), such as cable modems, ADSL, cell phones, PDAs etc, this becomes even more indispensable, because most of the PIPs have a real-time analog input and/or analog output [4]. However, this SoC trend interferes with the design reuse and the PBD methodology, because analog/mixed-signal platforms are hardly available yet and as a consequence the design of the analog part dominates the design time, cost and risk. The fundamental reason for this is that in the analog case the physical effects have signicant inuence on the performance and functionality of the system and the physical layer cannot be decoupled from the functional layer. Moreover, the lowvoltage environment of the digital CMOS technologies, along with the absence of components, such as capacitors, resistors, with good analog characteristics, prevents the transferring of existing analog designs to digital technologies. Therefore, we should adopt a new approach that utilizes the benets of the low voltage, high speed and low cost digital logic. Taking into account the PBD necessity and the SoC trend, we propose a way to implement an analog platform for ADCs in a FPGA, constructing a FPMA. The design complexity will be hidden from the end user, who, via a software interface, will be able to congure the hardware in conformity with his/her needs. The implementation of the analog platform in the FPGA gives us the possibility to employ the benets of the existing digital correction methods that can be implemented in a FPGA. Existing developments in the direction of exible or programmable ADCs are based on either FPAA (FieldProgrammable Analog Arrays) with high granularity which offer high exibility but low performance [5], [6] or recongurable ADC solutions with limited coverage of resolution range [7], [8]. We aim to cover the range of resolutions from 8bits up to 14bits with optimum speed, using a exible ADC platform. The following graph (g. 1) gives a picture of our target related to other popular ADC architectures. II. T HE P ROPOSED S OLUTION A. The Flexible Matrix Several designs have proven that the pipelined architecture is one of the most successful architectures for high-speed, low-power analog-to-digital conversion. It provides high modularity and regularity and it is the most suitable for telecom

0-7803-8834-8/05/$20.00 2005 IEEE.

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Conversion Rate (MSPS)

2E3 1E3 500 200 100 50 20 10 Pipelined SAR 1 6 8 10 12 14 16 18 20 Resolution (bits) Flexible ADC Target Flash Folding/ Interpolation

during the normal operation of the ADCs do not change state, except for some special situations mentioned below. This converter architecture provides means to achieve parallelization along different axes, such as time parallelization, hardware parallelization and algorithm parallelization. According to the dimensions and the target utilization of the matrix, it is necessary to integrate a number of front-end Sample and Hold (S&H) circuits. At least one S&H should comply with the maximum desirable resolution The BBs that are not in use during the operation can be switched-off to save power B. The Basic Block (BB) The matrix consists of basic blocks and an interconnection network. The arrow on each BB points into the signal direction of the cell. A BB is composed of a ash sub-ADC, a sub-DAC, a subtraction block and a Sample and Hold (S&H) amplier.
A n a lo g in p u t

Fig. 1.

Flexible ADC target

applications, which are the main focus of the FPGAs users. Moreover, it is a mature architecture, very well documented and it allows many (analog and/or digital) techniques to enhance its performance. Therefore, we propose a realization of a exible reprogrammable/recongurable ADC based on the pipelined architecture. Figure 2 depicts our proposal with a 6x6 matrix of basic blocks [patent led]. Our idea is not restricted only to those matrix dimensions, but we can easily employ smaller or larger dimensions, according to our needs.

+
s u b -A D C s u b -D A C

M D A C x 2
R e s id u e

S & H A m p

1 .5 b
Fig. 3. Internal view of a basic block (BB)

S/H

Fig. 2.

Flexible recongurable matrix composed of BBs

A number of identical basic blocks (BB) and an interconnection network construct our matrix. Moreover, for the functionality of the structure is necessary at least one frontend S&H. Every second row of the matrix is ipped in the layout, as indicated by the arrow, which allows closest neighbors connectivity to keep the interconnection lines as short as possible and, hence, to increase the analog signal integrity and to ease the routing of the analog lines. We try to keep the number of switches to minimum, and even more important, to minimize their effect on the analog signal quality. For that reason, we choose to use a fully hardwired BB with only the essential for its operation internal switches (not shown in g. 2). The external switches are in general used only for the interconnections of the blocks, which

Usually, the functions of digital-to-analog conversion, subtraction and S&H amplication are implemented in one single circuit called multiplying DAC (MDAC) [9]. Typically, a closed-loop switched-capacitor realization of that circuit is employed We use identical BBs for the whole structure. The resolution of every block is equal to 1.5bit, which means an effective resolution of 1bit plus 0.5bit reserved for digital correction [9] This choice improves the modularity and exibility of the matrix allowing many combinations, while at the same time it ensures robustness. Furthermore, the use of a single block minimizes design risk and time and allows easier IP-reuse The implementation of this matrix into a high-performance FPGA permits extensive use of digital correction algorithms. We propose the use of three distinct correction methods: - Digital correction [9], which employing bit redundancy (0.5bit in our case), greatly relaxes the sub-ADCs comparators offset specications; - Digital calibration [10], which employing stage redundancy, corrects offset and linear errors in sub-DAC, residue amplier and S&H stage; - Digital non-linearity calibration [11], which using a digital algorithm, corrects static non-linearities, in the residue amplier and S&H stage. Using the above techniques, we essentially translate the analog precision problem into the digital domain. This is in line with

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the trend of the new digital technologies that offer high speed, but worse voltage resolution. Furthermore, the digital systems become smaller and cheaper, while the analog counterparts suffer from the low voltage environment. Therefore, several advantages arise due to the translation of the analog problems to the digital domain. We expect potential power savings and/or speed improvements and it may help to overcome future scaling problems. It is clear that the above-mentioned correction methods relax the analog design and especially the non-linearity calibration algorithm allows us to use an open-loop residue amplier, instead of the standard closed-loop realization. The potential of open-loop structures for high-speed applications has been demonstrated [12], as well as the capability to achieve lower power dissipation for specic speed, [11]. Furthermore, we can employ a frequency-to-voltage (f/V) or a frequency-tocurrent (f/I) converter to sense the clock frequency and to adjust automatically the bias current of the ampliers to the smallest value that is necessary for the stages to settle to the appropriate level, as to keep the power consumption to a minimum level. III. S EVERAL C ONFIGURATIONS OF THE M ATRIX The matrix of gure 2 gives us the possibility to combine the blocks in several ways to implement different analogto-digital algorithms (serial or parallel) with extensive time and hardware parallelization. A number of possibilities is illustrated below. A. One or More Standalone Pipelined ADCs Figure 4 shows the proposed implementation of a standalone pipelined ADC. We indicate with solid lines the BBs that are active and the switches that are constantly on and with dashed lines the inactive BBs and the turned-off switches.
S/H

B. One or More Time-Interleaved ADCs Figure 5 depicts a proposed implementation of a three channel Time-Interleaved (TI) ADC on the matrix. This conguration aims for high speed applications. As one can see, our matrix gives the possibility to use less or more BBs in series, providing exibility in the resolution of the converter.
S/H S1

S2

S3

Fig. 5.

Time-Interleaved ADC

The front-end S&H is clocked three times faster than a single BB. The active BBs and the turned-on switches are indicated with solid lines, and the inactive BBs and the turnedoff switches with dashed lines. The switches S1 , S2 and S3 take actively part in the functionality of the TI ADC, since they implement an analog demultiplexer. In this case, we have parallel simultaneous operating hardware, in different time slots, employing a parallel algorithm. Like in the case of the pipelined conguration, we can implement more that one time-interleaved ADC dependent on the size of the matrix and the available S&Hs. C. Cyclic ADC The conguration of the matrix that allows the realization of a cyclic converter, aiming for high resolution, low speed and low power applications, is shown in the following gure.
S2 S/H S1

Fig. 4.

Standalone pipelined ADC

By connecting or disconnecting BBs we can respectively increase or decrease the resolution of the ADC. In this case, we have parallel simultaneous operating hardware, in different time slots, employing a serial algorithm. The matrix gives us the possibility to implement more than one standalone pipelined ADC, depending on the size of the matrix and the number of available S&Hs.

Fig. 6.

Cyclic ADC

We use only two BBs and a front-end S&H while the rest of the BBs are switched off (dashed BBs). The switches S1

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and S2 take active part in the implementation of the cyclic algorithm. This realization of the cyclic converter has some differences from the typical case [13]. The main deviation from the typical case is that we use two blocks instead of one, because when the analog output of a BB is valid, the same BB cannot sample this output. Another difference is that we use 1.5bit per block, instead of just 1bit. The front-end switch (S1 ) switches on, the rst BB samples the output of the S&H, and then the switch in parallel with the BBs (S2 ) turns on and remains on until we resolve the complete digital word. Subsequently, S2 goes off and S1 turns on to provide a new sample from the S&H. In this case, we have the same hardware operating in different time slots, employing a serial algorithm. D. Pipelined ADC Employing Averaging As for some applications, the input-referred thermal noise is not one of the most crucial requirements (e.g. digital imagers, etc), we can under-design our BBs with respect to thermal noise. This approach allows the utilization of smaller capacitors and saves power and area, since the size of the capacitors increases four times for every additional bit of accuracy. However, for applications where the noise is of high concern, our matrix gives us the possibility to lower the input-referred noise, employing noise averaging at the analog outputs of the BBs, as shown in g. 7.
S/H

time. We have paid extra attention on implementing exibility with minimal loss of performance. Several congurations have been shown, aiming for different performance requirements. The Time-Interleaved ADC conguration aims for high-speed applications, the pipelined ADC employing averaging aims for high accuracy, the cyclic ADC aims for low power and nally, the standalone pipelined ADC covers the middle performance space. Therefore, the presented structure provides exibility along many different axes, such as accuracy, speed and power consumption and we are able to cover the performance area pictured in g. 1. R EFERENCES
[1] T. A. C. M. Claassen, Platform design: The next paradigm shift to deal with complexity, in International Symposium on VLSI Technology, Systems and Applications, 2003, Oct. 6 8 2003, pp. 812. [2] H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd, Surviving the SoC Revolution: A Guide to Platform-Based Design. Kluwer Academic Publishers, 1999. [3] A. Sangiovanni-Vincentelli. (2002, Feb.) Dening Platform-Based Design. [Online]. Available: www.eedesign.com/story/OEG20020204S0062 [4] D. Buss et al., SoC CMOS technology for Personal Internet Products, IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 546556, Mar. 2003. [5] E. K. F. Lee and P. G. Gulak, A CMOS Field-Programmable Analog Array, IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 18601867, Dec. 1991. [6] S. Mortezapour and E. K. F. Lee, Recongurable Analog Integrated Circuit Architecture based on Switched-Capacitor Techniques, in Proc. IEEE ISCAS 2001, vol. 4, 2001, pp. 314317. [7] P. Setty, J. Barner, J. Plany, H. Burger, and J. Sonntag, A 5.75b 350MS/s or 6.75b 150MS/s Recongurable Flash ADC for a PRML Read Channel, in Proc. IEEE ISSCC 1998, vol. 1, 1998, pp. 148149, 428. [8] K. Gulati and H.-S. Lee, A Low-Power Recongurable ADC, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 19001911, Dec. 2001. [9] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, A 10-b 20-MSample/s Analog-to-Digital Converter, IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351358, Mar. 1992. [10] A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, A 15-b 1-MSample/s Digitally Self-Calibrated Pipeline ADC, IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 12071215, Dec. 1993. [11] B. Murmann and B. E. Boser, A 12-bit 75-MS/s Pipelined ADC using Open-Loop Residue Amplication, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 20402050, Dec. 2003. [12] K. Poulton et al., A 20 GS/s 8-b ADC with a 1 MB memory in 0.18m CMOS, in Proc. IEEE ISSCC 2003, vol. 1, 2003, pp. 318496. [13] P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, A ratio-independent algorithmic analog-to-digital conversion technique, IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 828836, Dec. 1984.

Fig. 7.

Standalone pipelined ADC employing averaging

In this conguration, we have parallel simultaneous operating hardware. A part of the hardware (averaging BBs) operates in the same time slot, while the rest of it operates in different time slots, employing a serial algorithm. Depending on the size of the matrix and the accuracy requirements, we can use different numbers of parallelconnected BBs. Using averaging in the pipelined architecture, we aim for high accuracy applications. IV. C ONCLUSIONS In this line of work, the feasibility of a exible ADC matrix, based on a single building block and an interconnection network, has hereby been demonstrated and published for the rst

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