CONTENTS

Ahmed H. Zahran

8086 Interrupts

Contents
1 Introduction to Interrupts 2 8086 Interrupts
2.1 2.2 8086 Interrupt vector Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Introduction to Interrupts
Interrupts are special type of CALLS. That is to say that interrupts stops instruction sequential execution to execute a subroutine (usually called

Interrupt handler).

interrupt service routine (ISR) or

Interrupt processing is an alternative to polling.

The adderss of the ISR is stored in an then CS of the ISR.

interrupt vector, which is 4-byte containing the IP

ELC-203: Computer II

Lecture Notes

Ahmed H. Zahran

Intel processors have

256 interrupt types

whose interrupt vectors are stored in the rst

1000 bytes of the memory.

table.

These 1000 bytes are commonly knows as

Interrupt vector

Interrupts are two types

 

Software generated interrupts; e.g. INT 21. Software interrupts are commonly used to perform system procedures. hardware generated interrupts. For example interrupts generated by external devices such as the keyboard and mouse.

NMI (Non Maskable Interrupts) such as power faillure INTR (Interrupts)

ELC-203: Computer II

Lecture Notes

Ahmed H. Zahran

INTA is used to acknwledge the interrupt by the processor. the processor performs the following operations if

After completing every instruction,

an interrupt is detected [IF = 1 and INTR active (HIGH)]

    

FLAGS is pushed onto the stack Both the interrupt (IF) and trap (TF) ags are cleared, which disables the INTR pin and the trap or single-step feature. The CS and IP are pushed onto the stack. The processor generates

IN T A

LOW twice, each time for about one cycle to trigger

receiving the type of the interrupt in the second The interrupt vector contents starting at and execution resumes in the ISR.

IN T A

cycle

(n*4) are fetched and loaded into CS and IP

Interrupt service routine

  

ISR is a typical assembly program but it should be terminated by return instruction)

IRET

(Interrupt

On executing the IRET instruction, CS, IP and FLAGS are popped freom the stack.4 IF and TF are set to the state prior to the interrupt.

ELC-203: Computer II

Lecture Notes

Ahmed H. Zahran

2
2.1

8086 Interrupts
8086 Interrupt vector
Vector number Description

    

2.2

Type 0: Divide Error (Division by zero) Type 1: Debug Interrupt (Single step) Type 2: NMI Interrupt (Emergency events) Type 3: Breakpoint (e.g. INT 3 in the code) Type 4: Interrupt on overow

Type codes 5 through 31 are reserved by the Intel (actually many of them are used in the following Intel processors) Type codes 32-255 can be used.

Example

; The ISR i s w r i t t e n a t o f f s e t Custom ISR o f t h i s program b u t i s not shown h e r e

in al , 3 7 8 ; cmp al , 6 0 j l low cmp al , 8 0 j l e ok jg high low : mov al , 1 out 1 2 7 , al ; t u r n "on" h e a t e r @ p o r t 1 2 7 . jmp ok high : mov al , 0 out 1 2 7 , al ; t u r n " o f f " h e a t e r @ p o r t 1 2 7 ok : IRET ; mov mov mov mov mul mov mov mov add mov
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ax , 0 ;

CISR :

es , ax al , 9 0 h ; i n t e r r u p t # 90 h : bl , 4 h ; m u l t i p l y 90 h by 4 , s t o r e r e s u l t i n ax bl bx , ax si , o f f s e t [ CISR ] ; copy o f f s e t i n t o i n t e r r u p t v e c t o r es : [ bx ] , s i bx , 2 ax , cs ; copy segment i n t o i n t e r r u p t v e c t o r :

4 Lecture Notes

ELC-203: Computer II

2.2

Example

Ahmed H. Zahran

mov es : [ bx ] , ax int 90 h ; t e s t newly c r e a t e d i n t e r r u p t .

References

M. RAFIQUZZAMAN,  Fundamentals of Digital Logic and Microcomputer Design, Fifth Edition.

ELC-203: Computer II

Lecture Notes