INTERNAL ARCHITECTURE OF 32-BIT FLOATING POINT PROCESSOR

UJWAL PATIL Roll No: 16

INTRODUCTION
A digital signal processor (DSP) is a type of microprocessor that is optimized for digital signal processing. The TMS320-C3x, C4x, C67x series of processors (DSP) are high performance CMOS 32-bit floatingpoint devices in the TMS320 family of single-chip DSPs.

TMS Product Generation

TMS DSP Types

Fixed Point DSPs  TMS320C5x & 54x  16-bit DSPs Floating Point DSPs  TMS320C3x, 4x & 67x  16 & 32-bit DSPs Multiprocessor DSPs  TMS320C8x

TMS DSP IC..

TMS 320 C3X
TMX : Experimental device TMP : Prototype TMS : Qualified device C: CMOS Tech with on chip non- volatile memory as ROM E: CMOS tech with on-chip non volatile memory as EPROM nothing : NMOS tech with on-chip non volatile memory as ROM 3 : Generation X : Version number- 0,1,2,3,4x,5,6,7

INTERNAL ARCHITECTURE OF TMS320C3x

1. 2. 3. 4.

Central Processing Unit (CPU) Memory Unit (RAM, ROM, Cache) Peripherals (Serial ports, Timers, etc) and DMA Controller

CENTRAL PROCESSING UNIT

1. 2.

3. 4.

Floating-point/ Integer multiplier Arithmetic and logic unit (ALU) 2.1 32-bit barrel shifter 2.2 Internal busses (CPU1/ CPU2 and REG1/REG2) Auxiliary registers arithmetic unit (ARAU) CPU register file

BLOCK DIAGRAM OF CPU

Floating-Point/Integer Multiplier
The multiplier performs single-cycle multiplications on 24-bit integer and 32-bit floating-point values. When the multiplier performs floating-point multiplication, the inputs are 32-bit floating-point numbers, and the result is a 40-bit floating-point number.

Arithmetic and logic unit (ALU)

The ALU performs single-cycle operations on 32-bit integer, 32-bit logical, and 40-bit floating-point data, including single-cycle integer and floating point conversions. The barrel shifter is used to shift up to 32 bits left or right in a single cycle. Four internal buses, CPU1, CPU2, REG1, and REG2.

Auxiliary Register Arithmetic Units

Two auxiliary register arithmetic units (ARAU0 and ARAU1) can generate two addresses in a single cycle. The ARAUs operate in parallel with the multiplier and ALU. They support addressing with displacements, index registers (IR0 and IR1), and circular and bit-reversed addressing.

CPU Primary Register File

The C3x provides 28 registers in a multiport register file that is tightly coupled to the CPU. Eight extended-precision registers (R0R7)are especially suited for maintaining extended-precision floating-point results. Eight auxiliary registers (AR0-AR7) support a variety of indirect addressing modes and can be used as generalpurpose 32-bit integer and logical registers. The remaining registers provide such system functions as addressing, stack management, processor status, interrupts, and block repeat.

CPU Primary Register File..

Register Name R0 R7 AR0 AR7 DP IR0 IR1 BK SP ST IE IF IOF RS RE RC Assigned Function Extended precision registers Auxiliary registers Data pointer Index registers Block-size register Stack pointer Status register CPU/DMA interrupt-enable register CPU interrupt flag I/O flag Repeat start-address Repeat end-address Repeat counter

Extended-Precision Registers (R7R0)

It can store and support operations on 32-bit integers and 40-bit floating-point numbers. Any instruction that assumes the operands are:
 

floating-point numbers then bits 390 are used, either signed or unsigned integers then bits 310 are used; bits 3932 remain unchanged.

Auxiliary Registers (AR7AR0)

The primary function of the auxiliary registers is the generation of 24-bit addresses. They can also operated as loop counters in indirect addressing or as 32-bit general purpose registers that can be modified by the multiplier and ALU.

Data-Page Pointer (DP)

The data-page pointer (DP) is a 32-bit register that is loaded using the load data page (LDP) instruction. The eight LSBs of the data-page pointer are used by the direct addressing mode as a pointer to the page of data being addressed.

Index Registers (IR0, IR1)

The 32-bit index registers (IR0 and IR1) are used by the ARAU for indexing the address. Block Size (BK) Register The 32-bit block size register (BK) is used by the ARAU in circular addressing to specify the data block size.

System-stack Pointer (SP)

It contains the address of the top of the system stack.

The program counter is pushed onto the system stack on subroutine calls, traps, and interrupts. It is popped from the system stack on returns. The system stack can be pushed and popped using the PUSH, POP, PUSHF, and POPF instructions.

Status Register (ST)

The status (ST) register contains global information about the state of the CPU. Operations usually set the condition flags of the status register according to whether the result is 0, negative, etc.

CPU/DMA Interrupt-Enable register (IE)

The CPU/DMA interrupt-enable (IE) register of the C3X are 32-bit registers. The CPU interrupt-enable bits are in locations 100 for C30 and C31 devices, and 110 for C32 devices.

Fig: CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31)

The direct memory access (DMA) interruptenable bits are in locations 2616 for C30 and C31 devices, and 3116 for C32 devices.

Fig: CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31)

CPU interrupt flag register (IF)

A 1 in a CPU IF register bit indicates that the corresponding interrupt is set. The IF bits are set to 1 when an interrupt occurs. They may also be set to 1 through software to cause an interrupt. A 0 indicates that the corresponding interrupt is not set. If a 0 is written to an IF register bit, the corresponding interrupt is cleared.

Other Registers
Program-counter (PC) is a 32-bit register containing the address of the next instruction to fetch. Instruction register (IR) is a 32-bit register that holds the instruction opcode during the decode phase of the instruction.

Memory Organization
The total memory space of the C3x is 16M (million) 32-bit words. Program, data, and I/O space are contained within this 16M-word address space. The C3xs separate program, data, and DMA buses allow for parallel program fetches, data reads and writes, and DMA operations.

Peripherals
All C3x peripherals are controlled through memory-mapped registers on a dedicated peripheral bus. This peripheral bus is composed of a 32-bit data bus and a 24-bit address bus.

Peripheral Modules

Direct Memory Access (DMA)

The on-chip DMA controller can read from or write to any location in the memory map without interfering with the CPU operation. The DMA controller contains its own address generators, source and destination registers, and transfer counter.

DMA Block Diagram

TMS320C-30/31/32 differences
Feature External bus C30 Two buses: Primary bus: 32-bit data 24-bit address Expansion bus: 32-bit data 13-bit address 4k 2k 16M x 32 8K x 32 1 channel 2 2 5V C31 One bus: 32-bit data 24-bit address C32 One bus: 32-bit data 24-bit address

ROM On-chip RAM Off chip memory DMA Serial ports Timers Voltage

NO 2k 16M x 32 1 channel 1 2 5V/3.3V

NO 512k 16M x 32/16/8 2 channels 1 2 5V

REFERENCES
Technical reference manual for TMS320C3x by Texas Instrument. Book on Digital signal processors by B. Venkataramani and M Bhaskar. www.wikipedia.com

Question Bank
Explain the internal architecture of 32-bit floating point DSP processor ? Explain the CPU of TMS320C3x ? Explain the CPU register file of TMS320C3x ? Explain the different types of buses used in TMS320C3x architecture ? Compare the different processor of TMS320C3x family of DSP ?

THANK YOU !