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ECE 410 DIGITAL SIGNAL PROCESSING D. Munson
University of Illinois Chapter 9
Implementation of Ideal D/A
Consider
y
n
y
a
(t)
D/A
Recall that any D/A we encounter in this course can be modeled by
y
a
(t) = y
n
g
a
(t nT)
n=
(1)
and that the Fourier-domain relation is
Y
a
() = G
a
() Y
d
(T) (2)
For the ideal D/A, we have g
a
(t) = sinc
T
t
|
\
|
.
, giving
y
a
(t) = y
n
n=
sinc
T
(t nT)
(
(3)
and
G
a
() =
T
T
0 else
so that (2) gives
Y
a
() =
TY
d
(T)
T
0 else
(4)
How might we implement the ideal D/A, described by (3)?
9.2
Conceptually, we might think along the lines of:
T
k
y
k
a
(t-kT)
impulse response
a
(t-kT)
k
Ideal
Analog
LPF
g
a
(t) = sinc
T
t
y
n
y
a
(t)
Then:
y
a
(t) = g
a
(t)
*
y
n
n
a
(tnT) = y
n
n
g
a
(tnT) as desired.
For an actual implementation, we might consider approximating the impulse train by a periodic
sequence of very tall, narrow pulses. However, this would be difficult in practice. As a
result, D/As are not implemented as suggested above!
In practice, the ideal D/A is approximated with the following two-stage system:
Zero
Order
Hold
y
a
(t)
y
a
(t)
F
a
()
y
n
in manufacturers catalog just the ZOH may be called a D/A
What is a zero-order hold (ZOH)? It is a D/A that uses rectangular pulses, i.e.,
y
a
(t) = y
n
p
a
(t nT)
n
(5)
where
9.3
p
a
(t)
1
T
t
y
0
y
1
y
2
y
3
_
y
a
(t)
t
T
Thus, the ZOH output is a staircase approximation to the desired y
a
(t). This staircase must be
smoothed by F
a
() to produce the proper y
a
(t).
The Fourier-domain relation for the ZOH has the form given by (2), but now
G
a
() =
0
T
1 e
jt
dt
=
e
jt
j
T
0
=
e
jT
1
j
=
e
j
T
2
e
j
T
2
e
j
T
2
|
\
|
.
|
j
= e
j
T
2
2 sin
T
2
= T e
j
T
2
sinc
T
2
Thus,
Y
a
() = T e
j
T
2
sinc
T
2
|
\
|
.
Y
d
(T) (6)
Before deciding how to choose F
a
(), which follows the ZOH, lets see how the effect of the
ZOH differs from the ideal D/A, in the Fourier domain.
Example
Suppose have
9.4
Y
d
()
1
Sketch Y
a
(), the Fourier transform of the output of an ideal D/A, and Y
a
(), the Fourier
transform of the output of a ZOH.
Using (4), we have for the ideal D/A:
Y
a
()
T
For the ZOH, lets plot Y
a
() . The terms in (6) look like:
1
4
T
3
T
2
T
2
T
4
T
Y
d
(T)
sinc
T
2
3
T
Ya () is T times the product of the above two curves:
T
4
T
3
T
2
T
2
T
3
T
4
T
Y
a
()
9.5
Notice that unlike Y
a
() for the ideal D/A, Y
a
() for the ZOH has frequency content that
extends all the way to = . This is not surprising, since y
a
(t), for the ZOH, is a staircase
function with discontinuities. Sharp edges (discontinuities) always correspond to a frequency
content extending to .
Now, if we have Y
a
() from the ZOH, how do we choose F
a
() to produce Y
a
()? The above
sketches suggest that we need F
a
() to be a LPF with cutoff at
c
=
T
. To investigate this
thoroughly, note that for the ZOH system we have
Y
a
() = F
a
() Y
a
()
= F
a
() T e
j
T
2
sinc
T
2
|
\
|
.
Y
d
(T) (7)
For the ideal D/A, the relation is given by (4). To have (7) correspond to (4) we must have
F
a
() T e
j
T
2
sinc
T
2
|
\
|
.
Y
d
(T) =
T Y
d
(T)
T
0 else
or
F
a
() =
e
j
T
2
sinc
T
2
|
\
|
.
T
0 >
T
The first zero-crossing of sinc
T
2
occurs when
T
2
= =
2
T
.
9.6
2
T
T
2
T
sinc
T
2
So, F
a
() looks like:
F
a
()
Thus, the ideal F
a
() is a LPF that emphasizes the higher frequencies in its passband.
(Surprising!)
F
a
() has finite support f
a
(t) has infinite support. f
a
(t) might look something like:
f
a
(t)
T
2
t
In practice, we would use a filter with a causal impulse response f
a
(t) with f
a
(t) f
a
(td) u
a
(t)
(delayed and truncated version of f
a
(t)).
9.7
t
d
f
a
(t)
Using f
a
(t) will delay the desired output by d seconds, but this is no problem in most
applications if d is small.
Notes:
1. In cheaper D/As, we may use a very simple R-C network to crudely approximate the
desired F
a
().
2. The high-frequency emphasis within the passband of F
a
() can be performed digitally as
part of the digital filter function. For example, if wish to realize an analog LPF using
T
D/A
x
a
(t)
H
d
()
y
a
(t)
then instead of using
H
d
()
c
could use
9.8
H
d
()
c
c
In this case, we still need an F
a
() after the ZOH, but now F
a
() can be a regular LPF
with a flat response in the passband:
F
a
()
T
A/D and D/A Circuits
A/D consists of sample and hold followed by a quantizer.
In catalogs, just the quantizer is called an A/D (unless A/D is referred to as a sampling A/D).
As we shall see, the sample and hold is very simple, whereas the quantizer is much more
complicated.
Sample and Hold:
transistor switch
controlled by
a clock
voltage follower
high input impedance,
low output impedance
+
x
s
(t)
x
a
(t)
A/D (Quantizer)
Uses comparators:
9.9
2
(t)
2
(t)
x
1
(t)
x
2
(t)
1 x
1
(t)x
0 x
1
(t)< x
+
-
Two popular types of A/Ds:
a) Successive Approximation
~ for low and medium sampling rates; uses a D/A!
+
Successive
Approximation
Register
Binary
Output
Word
Clock
D/A
UP/DOWN COUNTER
x (t)
s
Runs at a much higher
frequency than
1
T
Here, x
s
(t) is the input from the sample and hold. The above system quantizes x
s
(t) to fit into a
computer register. The comparator output signal causes the up-down counter to either increment
or decrement, at a high rate, until it contains a binary approximation of x
s
(t). When the counter
has settled around the correct digital representation of x
s
(t), it simply toggles back and forth in
its least significant bit until the value of x
s
(t) changes.
Succcessive approximation A/Ds are fairly slow (and thus used for low and medium bandwidth
applications) because it may take several clock cycles for the counter to settle on a new value of
x
s
(t).
b) Parallel or Flash A/D
For high speed (8 bits/sample at 500 MHz is currently possible).
Uses 2
N
1 comparators for N-bit output word.
9.10
Example 2 bit quantizer:
+
X
Y
Z
0 or 1
0 or 1
0 or 1
MSB = Y
Digital
Logic
3
4
V
1
4
V
x
s
(t)
LSB = X or (Z and Y)
1
2
V
Here, 0 x
s
(t) <
1
4
is mapped to (0, 0),
1
4
x
s
(t) <
1
2
is mapped to (0, 1),
1
2
x
s
(t) <
3
4
is
mapped to (1, 0), and x
s
(t)
3
4
is mapped to (1, 1).
D/A Converters ~ Zero Order Hold (ZOH)
The contents of a binary register containing y
n
are the input to a D/A. Let B
0
, B
1
, B
2
, , B
N1
| |
be the binary representation of y
n
. The B
i
change with period T as y
n+1
replaces y
n
in the D/A
input register.
9.11
One popular type of D/A uses a resistor ladder (can also use a capacitor ladder):
Vout
+
R R R
2R 2R 2R 2R 2R
Vref
Rf
+
V
0
V
1
V
2
V
N1
B
0
B
1
B
2
B
N1
The switches are transistors, where the B
i
control whether the transistors conduct to ground (left
position, B
i
= 0) or to the op amp (right position, B
i
= 1). The op amp then adds all signals input
to its minus terminal, with a weighting determined by the resistor values. To find the exact
relationship between V
out
and the B
i
, first apply KCL at Node N1 at the upper right, to give:
V
N1
2R
+
V
N1
2R
+
V
N1
V
N2
R
= 0
V
N1
+ V
N1
V
N2
= 0 V
N2
= 2 V
N1
Similarly: V
n1
= 2V
n
n = 1, 2, , N2
V
n
= V
N1
2
N1n
Using KCL at the minus terminal of the op amp gives:
1
2R
i=0
N1
B
i
V
i
=
0 V
out
R
f
where each B
i
is 0 or 1.
9.12
V
out =
R
f
2R
i =0
N1
B
i
V
N1
2
N1i
=
R
f
2R
V
N1
2
N1
B
0
+ 2
N2
B
1
++ 2 B
N2
+ B
N1
| |
So, V
out
is proportional to the number stored in the binary register representing y
n
. This number
changes according to a clock (y
n
y
n+1
), so V
out
(t) is a staircase function (edges wont be
perfectly square, though op amp has a nonzero rise time).
The ZOH is followed with the analog LPF, below, as discussed previously.
T
F
a
()