B GIO DC V O TO TRNG..

Lun vn
Nghin cu v thc hin b iu khin PID trnPLC S7-300

LI M U
Nc ta ang trong cng cuc cng nghip ha, hin i ha tng bc bt kp s pht trin cng cc nc trong khu vc cng nh cc nc trn th gii v mi mt kinh t, k thut v x hi. Cng nghip sn xut hng ha ng vai tr quan trng trong vic pht trin cc mt k trn. Vic t ng ha l s la chn ng n trong mi lnh vc nhm to ra sn phm hng lot, c cht lng cao, tng kh nng cnh tranh mnh m trn th trng. Cng vi cc ngnh sn xut khc th ngnh cng nghip nng ng vai tr quan trng nht trong vic a nc ta c tr thnh mt nc cng nghip tin b hay khng. V ngnh gia cng kim loi chnh xc cng gp mt phn nh b ca mnh vo xu hng trung . Nhng hin nay trang thit b my mc phc v trong cng nghip nc ta a s cn lc hu song do vn u t cn hn hp. Nn vic ci tin khng th tin hnh thay th mt cch ng loi m chng ta phi kt hp trn nhng nn tng vn c v thay th mt s trang thit b sao cho vn u t l nh nht, nhng dy truyn vn khng lc hu m vn ph hp vi xu th hin nay. V vy nghin cu v a PLC S7-300 vo s dng l mt gii php ci tin ng n cho iu khin ngnh cng nghip Vit Nam hin nay. Vic nghin cu v thc hin b iu khin PID trnPLC S7-300 l ni dung n tt nghip m em trnh by. n ca em gm 3 chng nh sau:

CHNG I: TNG QUAN V PLC S7-300

CHNG II : TP LNH LADER CA PLC S7-300 Ch-ng 3: b bin i PID trn S7-300

CHNG I: TNG QUAN V PLC S7-300

Trm tch cc cn gi l trm ch c chc nng kim sot vic giao tip vi cc trm t n qun l hoc c th giao tip vi cc trm tch cc khc trong mng. Hay ni cch khc cc trm ch c kh nng kim sot truyn thng trn bus. Mt trm ch c th gi thng tin khi n gi quyn truy nhp bus. Cc trm ch l cc thit b iu khin c tch hp mt cch tng th di tn l SIMATIC. l cc SIMATIC S7, SIMATIC M7, SIMATIC C7, SIMATIC S5... 1.1. cu trc c bn ca mt trm Simatic s7-300. SIMATIC S7 - 300 l h PLC mini, ng dng phn ln trong iu kin mi trng lm vic khc nghit nh rung lc mnh , nhit , m cao hoc trong mi trng bi bn, v d nh: Qun l v iu khin h thng n tn hiu giao thng. H thng x l nc thi. Bo qun hng ng lnh. Cc ngnh ng st. Ngnh ho cht... tng tnh mm do trong ng dng thc t, cc b iu khin PLC c thit k khng b cng ho v cu hnh , chng c chia nh thnh cc module. S lng cc module c s dng nhiu hay t ty thuc vo tng bi ton iu khin c th, tuy nhin bao gi cng phi c mt module chnh , l module CPU. Cc module cn li l nhng module truyn ,nhn tn hiu vi i tng iu khin, cc module chuyn dng nh PID, iu khin ng c...c gi l cc module m rng. Cc module c g trn cc thanh rack.

Hinh1: cu hnh b CPU * Module CPU: l loi module c cha b vi x l, h iu hnh, b nh, cc b thi gian, b m, cng truyn thng (RS485)...v c th c mt vi cng vo ra s. SIMATIC S7 - 300 c kh nng tnh ton nhanh, b lnh hon chnh, kt ni a im (MPI) v c kh nng ni mng qua mng SIMATIC NET LAN. C cc hm lp sn, kh nng chn on ton din, bo v bng mt m, h thng kt ni thun tin. Module CPU c th qun l c 3 rack, cc ng tn hiu c tch hp vo trong module v cc h thng kt ni c sn. S7-300 c hai loi module CPU chnh l: Loi CPU ch c mt cng truyn thng phc v cho vic kt ni vi cc thit b lp trnh, mng. Loi ny khng thc hin iu khin phn tn c. Loi CPU c hai cng truyn thng, trong cng truyn thng th hai c chc nng chnh l phc v vic ni mng phn tn. * Module m rng: Bao gm 5 (nm) loi chnh: Module ngun (PS - Power Supply) c ba loi: 2A, 5A,10A. Module tn hiu (SM - Sign Module ) bao gm:

Module tn hiu vo s (DI - Digital Input). S lng cc cng vo s trn mi module c th l 8, 16 hoc 32 ty thuc vo tng loi. Module tn hiu ra s (DO - Digital Output). S lng cc cng ra s trn mi module c th l 8, 16 hoc 32 ty thuc vo tng loi. Module tn hiu vo /ra s (DI/DO - Digital Input/ Digital Output). S lng cc cng vo /ra s trn mi module c th l 8 vo /8 ra hoc 16 vo /16 ra ty thuc vo tng loi. Module tn hiu vo tng t (AI - Analog Input). Thc cht chnh l cc b chuyn i tng t s. S lng cc cng vo tng t trn mi module c th l 2, 4 hoc 8 ty thuc tng loi. Module tn hiu ra tng t (AO - Analog Output). Thc cht chnh l cc b chuyn i s tng t. S lng cc cng ra tng t trn mi module c th l 2, 4 ty thuc tng loi. Module tn hiu vo /ra tng t (AI/AO - Analog Input/Analog Output). S lng cc cng vo /ra tng t trn mi module c th l 4 vo /2 ra hoc 4 vo /4 ra ty thuc vo tng loi. Module ghp ni (IM - Interface Module) y l loi module chuyn dng c nhim v ni tng nhm cc module m rng li vi nhau thnh mt khi v c qun l chung bi mt module CPU. Module chc nng (FM - Function Module) c chc nng iu khin ring nh: module iu khin ng c bc, ng c servo, module PID... Module truyn thng (CP - Communication Module) phc v truyn thng trong mng gia cc PLC vi nhau hoc gia PLC vi my tnh. 1.2. cu trc ca trm tch cc trong phng th nghim. Cc thit b ch c lp t trong phng th nghim ca trng bao gm bn trm SIMATIC S7C - 300, CPU 315 - 2DP. Mi trm SIMATIC S7 -300, CPU 315 - 2DP lp t trong phng th nghim ca trng c cu trc nh sau: Module ngun PS (Power Supply), loi 10A.

Module x l trung tm CPU, loi CPU 315 - 2DP. Module ghp ni IM (Interface module), loi IM153 - 1. Module m FC (Function module), loi FC - 350. Tt c cc module c t trn thanh rack, mi module chim mt khe cm (slot) trn rack. Vic giao tip gia CPU v cc module m rng c thc hin thng qua mt bus ni b t trn rack (back plane bus). 1.3. cc thnh phn ca trm Simatic S7-300. a. Rack. M s: 6ES7 390 - 1AF30 - 0AA0. Cc module c t ln thanh rack. Mi rack cho php t ti a l 11 module theo mt th t nht nh. Nh vy l mt CPU c ghp ni cng cc module m rng trn thanh rack, trong vic truy nhp ca CPU vo cc module m rng c thc hin thng qua a ch ca chng. Mt module CPU c kh nng qun l c 4 thanh rack vi ti a 8 module m rng trn mi thanh. Tu thuc vo v tr lp t ca module m rng trn mi thanh rack m cc cng vo /ra trn n c a ch khc nhau. b. Module ngun PS ( Power Supply ). M s: 6ES7 307 - 1KA00 - 0AA0 Module ngun (PS) dng chuyn i tn hiu in 120/ 230VAC thnh 24VDC cung cp cho CPU, cm bin / c cu chp hnh..v.v. S cu trc mch ca Module ngun PS307 (10A).

Hnh 1.2: Module ngun PS Bng: Thng s k thut. 5

u vo in p u vo. Gi tr bin thin in p. Di in p cho php. Thi gian qu p cc tiu. Tn s lm vic. Gi tr nh mc. Gi tr cho php. Dng u vo. Gi tr nh mc 230VAC. Gi tr nh mc 120VAC. u ra in p u ra Gi tr nh mc. Gi tr cho php. Dng u ra Gi tr nh mc. Thng s chung Tn hao cng sut Nhit lm vic

120/ 230VAC 93 n 132VAC/ 187 n 264VAC 20ms 50/ 60 Hz. 47 n 63 Hz. 1,7 A 3,5 A

24VDC. 24VDC + 5 % 10A. 30 W. 0 60 C

c. Module x l trung tm CPU 315 - 2 DP. Module CPU 315 2DP l loi c hai cng truyn thng, cng th nht phc v cho vic ghp ni vi cc thit b ngoi vi nh my tnh , my in...cng th hai phc v cho vic ni mng phn tn. M t: Mt trc ca module CPU 315-2DP gm: H thng ch th (Status and fault LEDs). Cng tc chn ch hot ng. Cng truyn thng phc v cho vic kt ni vi MPI Cng truyn thng phc v cho vic kt ni vi PROFIBUS -DP. Ngun v ni t ( Terminals for power supply and functional ground).

H thng ch th: H thng ch th bo cc trng thi hot ng ca CPU , bao gm: Hnh 1.3: CPU 315 - 2 DP

SF: Ch th trng thi cc li. BATF: Ch th trng thi li ca ngun nui. DC 5V: Bo trng thi ngun +5VDC. RUN: bo CPU ang trong ch hot ng. STOP: bo CPU ang trong ch dng. BUSF: Ch th trng thi li bus. Cng tc chn ch hot ng: Cng tc chn ch hot ng l mt nm xoay c 4 v tr, tng ng vi 4 ch : RUN - P: ti ch ny CPU s t quyt nh ch , RUN hoc STOP. RUN: t CPU vo ch hot ng.

STOP: t CPU vo ch dng. MRES: Xo chng trnh trong CPU v sao chp chng trnh t card nh sang CPU. Cng truyn thng kt ni vi MPI: CPU kt ni vi MPI (Multi Poit Interface) bng giao din RS485, 9 chn n phc v cho vic truyn thng gia cc trm vi nhau v cc trm vi my tnh. Cng truyn thng kt ni vi PROFIBUS DP: CPU kt ni vi PROFIBUS - DP bng giao din RS485, 9 chn n phc v cho vic ni mng phn tn. Cu trc. CPU B nh chng trnh trnh Khi vi x l trung tm + H iu hnh Timer B m Bt c Cng vo ra onboard Cng ngt v m tc cao Bus Qun l ghp ni

B m vo / ra

Hnh 1.4: S cu trc chung ca mt b iu khin logic kh trnh (PLC) Bao gm cc thnh phn c bn nh sau: Khi vi x l trung tm v h iu hnh: tnh ton, x l v thc hin iu khin ton b hot ng ca PLC. H iu hnh chng trnh c lu trong ROM.

B nh chng trnh: lu gi chng trnh, c th lm b m cho qu trnh x l v tnh ton. Thng thng b nh chng trnh dng loi RAM, EEPROM... B m vo ra: phc v cho vic truy xut cc tn hiu vo /ra s, cn cc tn hiu vo /ra tng t c truy xut trc tip. B thi gian (Timer): to thi gian tr mong mun gia tn hiu logic u vo v tn hiu logic u ra. B m (Counter): thc hin chc nng m sn xung ca cc tn hiu u vo Cng vo /ra Onboard: l cc cng vo /ra c gn ngay trn module CPU Cng ngt v m tc cao: qun l cc loi ngt v chng trnh x l ngt, qun l cc b m tc cao. Qun l ghp ni: qun l vic ghp ni ca CPU vi cc module m rng, cc thit b ngoi vi... Bus: phc v cho vic truyn thng ni b v gia CPU vi cc thit b ngoi vi.... Cc chc nng chnh. Trong CPU c ci t sn h iu hnh ca chng trnh , thc hin tt c cc chc nng iu khin thi gian thc, truyn thng, chun on v kim tra, qun l thng tin, lu tr v bo v...v.v. CPU c b nh chng trnh v RAM tc cao (tc x l lnh tng i nhanh, thc hin mt lnh nh phn trong khong thi gian 300ns) cung cp mt dung lng ln (64Kbyte) cho chng trnh ngi s dng. C kh nng m rng mt cch linh hot, ln ti 32 module m rng nm trn 4 racks. Chc nng lu tr thng tin: CPU c th lu tr tt c cc thng tin v cu hnh h thng, cc chng trnh ng dng (chng trnh chnh, con, ngt...). Trong mt s trng hp c bit CPU cn c kh nng lu tr s

liu m khng cn pin. Ngoi ra c th sao chp d phng chng trnh mt cch n gin nh card nh, dung lng ca card nh c th ln ti 4MB. Chc nng bo v: CPU cung cp password nhm xc nh quyn truy cp cho chng trnh v cc d liu. Nu khng c password th khng th thc hin vic quan st, sao chp, xo chng trnh ng dng. Chc nng kim tra, chun on v thng bo cc tnh trng k thut ca h thng cho ngi vn hnh: CPU c kh nng kim tra v chun on cc tnh trng k thut ca h thng, bao gm c v cu hnh cng v li trong cc chng trnh ng dng. Ngoi ra CPU cn dnh mt vng m lu tr cc kt qu kim tra v chun on, 100 li v cc s kin ngt mi nht c lu tr ti vng m phc v cho vic kim tra tip theo. Sau khi thc hin vic kim tra v chun on th CPU s thng bo cc trng thi li cho ngi vn hnh bng n LED. Cc n LED ch ra li phn cng, li chng trnh, li thi gian, li vo /ra hay li ca pin v cc trng thi hot ng nh RUN, STOP... Chc nng thng tin: c th s dng thit b lp trnh (PC, PG...) quan st s thay i trng thi ca cc tn hiu trong qu trnh thc hin chng trnh, thm ch c th thay i cc bin s mt cch c lp vi chng trnh ca ngi dng. Ngoi ra thit b lp trnh cn c th c dng cung cp cho ngi s dng cc thng tin v dung lng b nh, ch hot ng ca CPU, b nh lm vic v b nh s liu ang c s dng , thi gian qut hin ti v ni dung ca vng m kim tra...v.v. Chc nng truyn thng: cc chc nng truyn thng chnh: Truyn thng vi thit b lp trnh /OP. Truyn thng s liu ton cc. Truyn thng c s. Truyn thng m rng. Truyn thng tng thch vi S5. Truyn thng theo chun.

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Cc cng truyn thng trn CPU hu ht l RS485. CPU kt ni vi thit b lp trnh (PC) bng MPI (Multi Point Interface), cc I /O phn tn, OP...thng qua cng RS485. Giao din a im (MPI) c th thc hin ti 4 kt ni tnh vi cc thit b lp trnh (PCs, OPs), 8 kt ni ng ng thi vi s7 300/400, c th thit lp mt mng n gin gm 16 CPU kt ni vi nhau v thc hin c truyn thng s liu ton cc. Giao din PROFIBUS DP ca CPU cho php thc hin vic iu khin phn tn. Ngoi ra cn c mt s chc nng c tch hp sn trn CPU nh: b m, o tn s, iu khin v tr, iu khin khi chc nng...v.v. Bng thng s k thut ca CPU 315 2DP. B x l trung tm vi gn 3 bytes) B nh s liu. + Built - in. + Plug - in. Sao chp s liu d phng. + Khng c pin in. + C pin in. ng h thi gian thc Ngn ng lp trnh Cu trc trng trnh Cc kiu khi. 4K bytes bao gm b nh bit, b m, b thi gian, d liu. Tt c cc khi d liu. C STEP 7 Cu trc tuyn tnh. - Khi t chc (OB). - Khi hm (FBs). - Hm (Functions) (FC). - Khi d liu (DB). - Cc hm h thng (SBF, SFC). S lng ti a cc khi 128 FC, 128 FB, 127 DB. 96 Kbytes RAM. 512 Kbytes FEPROM. CPU 315 - 2DP 16K_lnh RAM ( built in ) RAM (mt cu lnh tng ng 64Kbytes

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X l chng trnh

- Theo vng qut t do (OB1). - Theo thi gian (OB 35). - Theo thi gian thc (OB 10). - Theo ngt (OB 40). - Khi khi ng li (OB 100).

B lnh

Binary logic, parenthesis command, resultn assignment, save, count, load, rotate... transfer, compare, shift,

Bo v chng trnh ca ngi dng Cc hm h thng (SFC)

Bo v bng mt m Bao gm cc hm kim sot li v ngt, sao chp s liu, cc hm ng h thi gian thc, cc hm kim tra, gn thng s cho cc module, chuyn ch hot ng.

Thi gian thc hin i vi: + Cc lnh tc ng ln bit. + Cc lnh tc ng ln t. + Cc lnh thi gian / b m. + Cng du chm tnh. + Cng du chm ng. + Thi gian vng qut B nh bt + S bt c duy tr (gi nguyn trng thi sau khi mt in) khi c pin in. + S bt c duy tr (gi nguyn trng thi sau khi mt in) khi 0 n 2048 (C th la chn t M0.0 n M255.7). 0, 3 n 0,6 s 1 s 12 s 2 s 50 s 150 ms (preset), c th t 1 n 6000 ms 2048 0 n 2048 (C th la chn t M0.0 n M255.7).

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khng c pin in S lng b m + S b m c duy tr khi c pin in. + S b m c duy tr khi khng c pin in. + Di m S lng b thi gian . + S timer c duy tr khi c pin in + S timer c duy tr khi khng c pin in + Di t thi gian Giao din a im (MPI) 32 trm trn MPI bus, bao gm cc thit b lp trnh / PCs, OP, cc S7 300/ 400, M7 300/ 400, C7 ln ti 4 kt ni tnh, 8 kt ni ng. + Tc truyn d liu + Khong cch gia hai trm 187,5 kbit/ s - Khng c b lp: 50m. - C 2 b lp: 1100m. - C 10 b lp tip ni: 9100 m qua cp quang: 23,8 km (vi 16 couples hnh sao hay OLM). Cc u vo / ra On-board + u vo / ra s, tng t Tng s a ch I / O Tng s u vo / ra s Tng s u vo / ra tng t S module ti a trong h thng 256/ 256 bytes 1024 knh 128 knh 32 + S lng ti a cc trm 10ms n 9990s C th chn t 0 n 127 1 n 999 128 C th chn t 0 n 127 C th chn t 0 n 63 64 C th chn t 0 n 63

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S ng ni DP trn CPU S trm DP trn mt CPU ch Khng gian a ch cho mt trm DP S module trn mt ET 200 Kt ni DP (master/ slave) in p ngun + Di in p + Di in p cho php Dng tiu th Cng sut tn hao Kch thc (W x H x D) (mm) Trng lng + CPU + Card nh Module c th i km + FM + CP, point-to-point + CP, LAN Phn mm + Phn mm iu khin + Kim tra qu trnh + S7 - GRAPH + S7 - HiGraph + S7 - SCL + CFC

1/ 1 64/ 32 122bytes 8 1 (CPU 342 - 5) 1(built-in, master/ slaver) 24 VDC 20, 4 n 28,8 VDC 1A 8W 80 x 125 x 130 530 16 8 4 2 c c c c c c

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CHNG II : TP LNH LADER CA PLC S7-300

2.1. Tng quan Bit Logic M t: Bit logic lm vic vi hai ch s, 1 v 0. Hai ch s to thnh c s ca mt h thng gi l h thng s nh phn. Hai ch s 1 v 0 c gi l ch s nh phn hoc bit. Trong th gii ca a ch lin lc v cun dy, 1 cho thy kch hot hoc c in, v mt 0 cho bit khng c kch hot hay khng c in. Cc bit logic gii thch tn hiu ca 1 v 0 v kt hp chng theo logic Boolean. Nhng kt hp ny to ra mt kt qu ca 1 hay 0 m c gi l kt qu "kt qu ca logic" (RLO). Cc hot ng logic c kch hot bi cc hng dn bit logic thc hin mt lot cc hm. Bit logic thc hin cc chc nng sau y: --- | | --- (a ch) thng m --- | / | --- (a ch) thng ng --- (SAVE) Lu RLO vo b nh BR Bit c quyn XOR OR --- () u ra --- (#) --- trung bnh u ra --- | NOT | --- o ngc ngun vo Cc trng hp RLO ca 1: --- (S) cun nh --- (R) cun Reset SR Set-Reset Flip Flop Thit lp li RS-Set Flip Flop

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2.1.2 Tham s a ch

tip im thng m Kiu d liu BOOl Vng nh I,Q,M,L,D,T,C M t Kim tra bit

--- | | --- (thng m) c ng li khi gi tr bit c lu gi ti <a ch> bng "1". Khi tip im c ng li, hot ng logic (RLO) = "1". Nu tnh trng tn hiu <a ch> quy nh l "0", tip im c m ra. Khi tip im c m, kt qu hot ng logic (RLO) = "0". Khi c s dng trong b, --- | | --- ni ni tip vi RLO bi logic AND . V c ni song song vi RLO bi logic OR. Trng thi BR Kt qu Tip im thng ng Kiu d liu BOOl Vng nh I,Q,M,L,D,T,C M t Kim tra bit _ CC1 _ CC) _ OV _ OS _ OR X STA X RLO X /FC 1

2.1.3 Tham s a ch

--- | / | --- (Thng ng) c ng li khi gi tr bit c lu gi ti <a ch> quy nh bng "0". Khi tip im c ng li kt qu hot ng logic(RLO)="1". Nu tnh trng tn hiu <a ch > quy nh l "1",tip im c m ra. Khi tip im c m ra , in khng chy qua tip im v kt qu hot ng logic(RLO)="0". Khi c s dng trong b, --- | / | --- c ni tip vi bit RLO bi logic AND. Khi c ni song song vi bit RLO bi logic OR.

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 trng thi BR Kt qu 2.1.4. lnh XOR Bit ring ca OR i vi chc nng XOR, mt network phi c to nh hnh v sau: Address1 Address1 Address2 Address2 _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

Tham s < address1> < address2> M t

Kiu d liu BOOl BOOl

Vng nh I,Q,M,L,D,T,C I,Q,M,L,D,T,C

M t Qut bit Qut bit

XOR (Bit Exclusive OR) to ra mt RLO ="1" nu tn hiu ca hai bit ch nh l khc nhau. 2.1.5 . --|NOT|-- lnh o ngc bit ngun vo K hiu: --|NOT|---|NOT|-- (o ngc ngun vo) ph nh bit RLO. Trng thi: BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR _ STA 1 RLO X /FC _

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2.1.6. ---( ) cun dy xut K hiu: Tham s < address> M t --- () (Output Coil) hot ng ging nh mt cun dy trong mt s logic relay. Nu c dng in cc cun dy (RLO = 1), cc bit v tr <address> c thit lp "1". Nu khng c in cc cun dy (RLO = 0), cc bit v tr <address> c thit lp "0". Mt cun dy xut ch c th c t cui bn phi ca mt ci dng lnh ca ladder. Mt u ra ph nhn c th c to ra bng cch s dng | --- NOT | -- (dng in o ngc) u vo. MCR (Master Control Relay) ph thuc ch c kch hot nu mt cun dy u ra c t bn trong mt MCR hot ng . MCR l tt, logic "0" c ghi vo a ch quy nh bt k cc tip im ca Role c gi tr nh th no th cc cun giy trong MCR u c gi tr l 0. Trng thi: BR Vit _ CC1 _ CC0 _ OV _ OS _ OR 0 STA X RLO _ /FC 0 ---( ) Kiu d liu BOOl Vng nh I, Q, M, L, D M t Gn bit

2.1.7. ---( # )--- Lnh u ra trung bnh K hiu: ---( # )--Tham s < address> Kiu d liu BOOl Vng nh I, Q, M, *L, D M t Gn bit

* Mt a ch L din tch ch c th c s dng nu n c khai bo TEMP trong bng khai bo bin ca mt khi logic (FC, FB, OB).

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 M t: --- (#) --- (u ra trung bnh) l mt phn t trung gian m tit kim Bit RLO (trng thi dng in) n mt <address> quy nh. u ra trung bnh lu kt qu hp l ca cc yu t nhnh trc . Trong mt lot vi cc a ch lin lc, --- (#) --- c chn nh cc a ch lin lc. mt --- (#) -- yu t khng bao gi c th c. mt u ra ph nhn c th c to ra bng cch s dng | --- NOT | --- (o ngc gi tr) . MCR (Master Control Relay) ph thuc MCR ph thuc ch c kch hot nu mt cun dy u ra trung bnh c t bn trong ca MCR hot ng. Trong thi gian m MCR c kch hot, nu MCRang bt trng thi ca u ra trung bnh c t gi tr nh c thit lp bnh thng. Nu MCR ang tt, a ch quy nh u nhn logic "=0" bt k gi tr thit lp c thay i nh th no. Trng thi: BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA X RLO _ /FC 1

2.1.8. ---( R ) Lnh Reset K hiu: ---( R ) Tham s < address> M t --- (R) (cun Reset) c thc hin ch khi RLO trc l "1" (dng in trong cun dy). Nu dng in cho cun dy (RLO l "1"), cc quy nh <address> ca mt phn t c t li thnh "0". Mt RLO ca "0" (khng c dng in cun dy) khng c tc dng v tnh cht ca a ch quy Kiu d liu BOOl Vng nh M t

I, Q, M, L, D, T, Reset bit C

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nh khng thay i. Cc <address> cng c th l mt b m th i gian (T no) c gi tr l thit lp li b m thi gian n. "0" hoc mt truy c p (C no.) C gi tr l thit lp li truy cp ti "0". MCR (Master Control Relay) ph thuc MCR ph thuc ch c kch hot nu mt cun dy u ra trung bnh c t bn trong ca MCR hot ng. Trong thi gian m MCR c kch hot, nu MCRang bt trng thi ca u ra trung bnh c t gi tr nh c thit lp bnh thng. Nu MCR ang tt, a ch quy nh u nhn logic "=0" bt k gi tr thit lp c thay i nh th no. Trng thi: BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA X RLO _ /FC 0

2.1.10. RS Reset-Set Flip Flop K hiu: R S S R Bin s <address> S R Q M t RS (Reset Flip Flop-Set) l thit lp li nu nh tn hiu v ca chn R= 1 v tn hiu vo ca S= 0.Ngc li nu u vo ca R=0 v u vo Kiu d liu BOOL BOOL BOOL BOOL B nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D M t Bit thit lp hoc thit lp li Cho php lp li chng trnh Cho php lp li chng trnh Tn hiu tr v a ch Q

20

chn S=1 th cc flip flop c thit lp. Nu RLO l "1" c hai u vo, theo th t l c tm quan trng chnh. Cc RS flip flop thc hin u tin hng dn thit lp li sau hng dn t <address> quy nh, a ch ny vn cn t cho phn cn li ca chng trnh qut. S (Set) v R (Reset) c thc hin ch khi RLO l "1". RLO "0 " khng c tc dng v a ch cc quy nh trong hng dn ny vn khng thay i. MCR (Master Control Relay) ph thuc MCR ph thuc ch c kch hot nu mt flop RS flip c t bn trong mt khu MCR hot ng. Trong thi hn mt khu MCR kch hot, nu MCR on, cc bit a ch Reset ="0"hoc Set = 1 nh m t trn. Nu MCR off, trng thi hin ti ca a ch quy nh khng thay i bt k gi tr u vo. Trng thi BR Kt qu 2.1.12. Tham s < address> _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

---( N )--- lnh pht hin sn khng tch cc ca RLO Kiu d liu BOOl B nh M t thi tn hiu trc ca RLO

K hiu: ---( N )--I, Q, M, L, D im ni nh, lu tr trng

M t --- (N) --- (Ph nh RLO khi pht hin im ni thay i ) pht hin mt s thay i tn hiu trong cc a ch t "1" thnh "0" v hin th n nh l RLO = "1" sau khi ch th. Nu a ch t 0 thnh 1 th RLO hin th l 1.

21

 Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA X RLO X /FC 1

2.1.13. Tham s < address>

---( P )--- Lnh pht hin sn tch cc ca RLO Kiu d liu BOOl B nh M t thi tn hiu trc ca RLO

K hiu : ---( P )--I, Q, M, L, D im ni nh, lu tr trng

M t --- (P) --- (Pht hin sn tch cc ca RLO) pht hin mt s thay i tn hiu trong cc a ch t "0" n "1" v hin th n nh l RLO = "1" sau khi ch th. Nu a ch thay i t 1n 0 th hin th RLO l 1. Trng thi: BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA X RLO X /FC 1

2.1.14. --- (SAVE) Lnh lu RLO vo b nh BR K hiu: --- (SAVE) M t: --- (SAVE) (Lu RLO vo b nh BR) lu trng thi RLO vo bit BR. Cc bit kim tra u tin / FC l khng t li. V l do ny, tnh trng ca cc bit BR c bao gm trong hot ng logic v trong mng tip theo. Hng dn i vi "SAVE" (LAD,FBD, STL), sau khi p dng v khng s dng c ngh quy nh ti s gip hng dn v trc tuyn: Chng ti khng khuyn bn nn s dng SAVE v sau kim tra cc bit BR trong

22

cng mt khi hoc trong khi cp di, bi v cc bit BR c th c sa i theo hng dn / p xy ra nhiu. l khuyn khch s dng cc hng dn SAVE trc khi thot mt khi, t sn lng ENO (= BR bit) sau c t thnh gi tr ca bit RLO v sau bn c th kim tra xem c sai st trong khi. Trng thi: BR Kt qu X CC1 _ CC0 _ OV _ OS _ OR _ STA _ RLO _ /FC _

2.1.15. NEG Lnh pht hin a ch khng tch cc K hiu:

address1 NEG Q address2 M_BIT

Bin s <address1> <address2>

Kiu d liu BOOL BOOL

B nh I, Q, M, L, D I, Q, M, L, D

M t Qut tn hiu M_BIT cnh b nh bit, lu tr trng thi tn hiu trc ca <address1> u ra

Q M t

BOOL

I, Q, M, L, D

NEG (pht hin a ch khng tch cc) so snh tnh trng tn hiu ca <address1> vi tnh trng tn hiu qut trc c lu tr trong <address2>. Gi tr RLO hin nay l "1" v gi tr trc ca RLO l "0" (pht hin tng cnh), cc bit RLO s l "1" sau khi hng dn ny.

23

 Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR X STA 1 RLO X /FC 1

2.1.16. POS Lnh pht hin a ch tch cc K hiu

address1
POS Q

address2

M_BIT

Bin s <address1> <address2>

Kiu d liu BOOL BOOL

B nh I, Q, M, L, D I, Q, M, L, D

M t Qut tn hiu M_BIT cnh b nh bit, lu tr trng thi tn hiu trc ca <address1> u ra

Q M t

BOOL

I, Q, M, L, D

POS (Pht hin a ch tch cc) so snh tnh trng tn hiu ca <address1> vi tnh trng tn hiu t qut trc c lu tr trong <address2>. Nu gi tr RLO hin nay l "1" v gi tr trc ca RLO l "0" (pht hin tng cnh), cc bit RLO s l "1" sau khi hng dn ny. Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR X STA 1 RLO X /FC 1

24

2.2. Lnh So snh 2.2.1. Tng quan v so snh M t IN1 v IN2 c so snh c cc kiu so snh sau cho ta chon. == IN1 bng IN2 <> IN1 khng bng IN2 > IN1 IN2 ln hn <IN1 l t hn IN2 > = IN1 ln hn hoc bng IN2 <= IN1 l t hn hoc bng IN2 Nu so snh l ng, cc RLO ca hm l "1". Cc RLO c ni ni tip bi Logic AND cn ni song song th c ni bi logic OR Cc hng dn so snh sau y c sn: CMP? I so snh s nguyn CMP? D So snh i s nguyn CMP? R So snh s thc 2.2.2. CMP? I Lnh so snh s nguyn K hiu
CMP
I IN1 IN2

CMP
I IN1 IN2

CMP
I IN1 IN2

CMP
I IN1 IN2

CMP
I IN1 IN2

CMP
I IN1 IN2

25

Tham s

Kiu d liu

Vng nh

M t

box input

BOOL

I, Q, M, L, D Kt qu ca cc hot ng logic trc I, Q, M, L, D Kt qu so snh, ch tip tc nu RLO ti u vo = 1 I, Q, M, L, D Gi tr u tin so snh Gi tr th hai so snh

box output

BOOL

IN1

INT

IN2 M t

INT

I, Q, M, L, D

CMP? I (So snh cc s nguyn) c th c s dng nh mt lin lc bnh thng. N c th c t bt k v tr m mt s lin lc bnh thng c th c t. IN1 v IN2 c so snh theo kiu so snh bn chn. Nu so snh l ng, cc RLO ca hm l "1". Cc RLO c ni ni tip bi Logic AND cn ni song song th c ni bi logic OR Trng thi BR Kt qu X CC1 X CC0 X OV 0 OS _ OR 0 STA X RLO X /FC 1

26

2.2.3. CMP ? D Lnh so snh hai s nguyn K hiu

CMP
D IN1 IN2 IN1 IN2

CMP
D

CMP
D IN1 IN2

CMP
D IN1 IN2

CMP
D IN1 IN2

CMP
D IN1 IN2

Tham s

Kiu d liu

Vng nh

M t

box input

BOOL

I, Q, M, L, D Kt qu ca cc hot ng logic trc I, Q, M, L, D Kt qu so snh, ch tip tc nu RLO ti u vo = 1 I, Q, M, L, D Gi tr u tin so snh Gi tr th hai so snh

box output

BOOL

IN1

INT

IN2 M t

INT

I, Q, M, L, D

CMP? D (So snh hai s nguyn) c th c s dng nh mt lin lc bnh thng. N c th c t bt k v tr m mt s lin lc bnh thng c th c t. IN1 v IN2 c so snh theo kiu so snh bn chn. Nu so snh l ng, cc RLO ca hm l "1". Cc RLO c ni ni tip bi Logic AND cn ni song song th c ni bi logic OR

27

Trng thi BR Kt qu X CC1 X CC0 X OV 0 OS _ OR 0 STA X RLO X /FC 1

2.2.4. K hiu

CMP ? R Lnh so snh gi tr thc

CMP
R IN1 IN2

CMP
R IN1 IN2

CMP
R IN1 IN2

CMP
R IN1 IN2

CMP
R IN1 IN2

CMP
R IN1 IN2

Tham s

Kiu d liu

Vng nh

M t

box input

BOOL

I, Q, M, L, D Kt qu ca cc hot ng logic trc I, Q, M, L, D Kt qu so snh, ch tip tc nu RLO ti u vo = 1 I, Q, M, L, D Gi tr u tin so snh Gi tr th hai so snh

box output

BOOL

IN1

INT

IN2 M t

INT

I, Q, M, L, D

CMP? I (So snh s thc) c th c s dng nh mt lin lc bnh thng. N c th c t bt k v tr m mt s lin lc bnh thng c

28

th c t. IN1 v IN2 c so snh theo kiu so snh bn chn. Nu so snh l ng, cc RLO ca hm l "1". Cc RLO c ni ni tip bi Logic AND cn ni song song th c ni bi logic OR Trng thi BR Kt qu X CC1 X CC0 X OV 0 OS _ OR 0 STA X RLO X /FC 1

2.3. H-ng dn chuyn i M t Cc hng dn chuyn i c ni dung ca cc tham s IN v chuyn i hoc thay i cc k hiu. Kt qu c th c truy vn ti tham s OUT. Cc hng dn chuyn i sau y c sn: BCD_I I_BCD BCD_DI I_DINT DI_BCD BCD ti s nguyn s nguyn ti BCD BCD ti hai s nguyn s nguyn ti hai s nguyn hai s nguyn ti BCD

DI_REAL hai s nguyn ti du phy ng Nhm lnh chuyn i 2.3.1. lnh BCD_I K hiu

BCD_I EN IN ENO OUT

29

Tham s EN ENO IN OUT M t

Kiu d liu BOOL BOOL WORD INT

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output BCD number Integer number value of BCD

Chuyn i t s nh dng di dng BCD ( cha 3 Digit) sang s nguyn 16 Bit, S BCD c tm (+/- 999) cha trong 12Bit. Trng thi BR Kt qu K hiu 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

2.3.2. Lnh I_BCD

I_BCD EN IN ENO OUT

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D M t Enable input Enable output Integer number BCD number value of integer

Tham s EN ENO IN OUT M t

Kiu d liu BOOL BOOL WORD INT

Chuyn i t s nguyn sang s c nh dng di dng BCD ( cha 3 Digit), do s BCD ti a 999 nn s nguyn phi ti a 999

30

Trng thi BR Kt qu 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

2.3.3. Lnh I_DINT K hiu

I_DINT EN IN ENO OUT

Tham s EN ENO IN OUT M t

Kiu d liu BOOL BOOL WORD INT

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output Integer value to convert Double integer result

Chuyn i s nguyn t 16Bit sang s nguyn 32 Bit thc hin cho cc php ton trn s 32 Bit. Trng thi BR Vit 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

2.3.4. Lnh BCD_DI K hiu

BCD_DI EN IN ENO OUT

31

Tham s EN ENO IN

Kiu d liu BOOL BOOL WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output BCD number

OUT

INT

I, Q, M, L, D

Double integer value of BCD number

M t Chuyn i t s nh dng di dng BCD ( cha 7 Digit)sang s nguyn 32 Bit Trng thi BR Kt qu 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

2.3.5. Lnh DI_BCD K hiu

DI_BCD EN IN ENO OUT

Tham s EN ENO IN OUT

Kiu d liu BOOL BOOL WORD INT

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output Double integer number BCD value of a double integer number

32

M t Chuyn i t s nguyn 32 Bit sang s c nh dng di dng BCD ( cha 7 Digit), do s BCD ti a 9999999 nn s nguyn phi ti a 9999999 Trng thi BR Vit 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

2.3.6. Lnh DI_REAL K hiu

DI_REAL EN IN ENO OUT

Tham s EN ENO IN

Kiu d liu BOOL BOOL WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output Double integer value convert to

OUT M t

INT

I, Q, M, L, D

Floating-point number result

Chuyn i t s nguyn 32 Bit sang s thc phc v cho cc php ton trn s thc. Trng thi BR Kt qu 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

33

2.3.7. Lnh INV_I K hiu

INV_I EN IN ENO OUT

Tham s EN ENO IN OUT M t

Kiu d liu BOOL BOOL WORD INT

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output Integer input value Ones compelement of the integer

o tt c cc Bit ca s nguyn 16 Bit Trng thi BR Vit 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

3.8. Lnh INV_ID K hiu

INV_ID EN IN ENO OUT

34

Tham s EN ENO IN

Kiu d liu BOOL BOOL WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Enable input Enable output Double integer input value

OUT M t

INT

I, Q, M, L, D

Ones compelement of the Double integer IN

o tt c cc Bit ca s nguyn 32 Bit Trng thi BR Kt qu 1 CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 1

2.4. COUNTER 2.4.1. Hng dn tng quan. B nh trong: C mt khu vc dnh ring cho Counter trong b nh ca CPU. Vng b nh ny d tr mt t 16-bit cho mi a ch truy cp. Cc thit lp logic ladder hng dn h tr 256 counters. Cc counters truy cp l cc chc nng duy nht m c th truy cp vo vng b nh truy cp. Gi tr m: Bits 0 n 9 ca t truy cp c cha gi tr s trong m nh phn. Gi tr tnh c chuyn n t truy cp khi truy cp c thit lp. Phm vi gi tr s l 0-999. Bn c th thay i gi tr s nm trong phm vi ny bng cch s dng theo hng dn truy cp:

35

 S_CUD S_CD S_CU ---( SC ) ---( CU ) ---( CD )

b m tin li b m tin b m li b nh m cun m tin cun m li

Cu hnh bit counter Bn cung cp mt truy cp vi mt gi tr nh sn bng cch nhp mt s 0-999, v d nh 127, nh dng sau: C # 127. C # l vit tt ca nh dng m nh phn thp phn (dng BCD: mi b bn bit c cha m nh phn cho mt gi tr thp phn). Bits 0 n 11 ca cha truy cp cc gi tr tnh trong nh dng m nh phn thp phn.

Nhng con s sau y cho thy ni dung ca cc truy cp sau khi bn ti cc gi tr tnh 127, v ni dung ca cc counter sau khi truy cp c thit lp.

36

2.4.2. B S_CUD K hiu

Tham s C no

Kiu d liu COUNTER

Vng nh C

M t Lt truy cp, phm vi truy cp ph thuc vo CPU

CU CD S

BOOL BOOL BOOL

I, Q, M, L, D m ln I, Q, M, L, D m xung I, Q, M, L, D Thit lp nh u vo ca counter I, Q, M, L, D Nhp gi tr truy cp nh C # v constant <value> trong khong 0-999 I, Q, M, L, D Ti gi tr thit lp couter I, Q, M, L, D Reset u vo I, Q, M, L, D Truy cp hin ti gi tr, s thp lc phn I, Q, M, L, D Truy cp hin ti gi tr, m BCD I, Q, M, L, D Trng thi ca cc truy cp

PV

WORD

PV R CV

WORD BOOL WORD

CV_BCD

WORD

Q M t

BOOL

S sn xung m c , c ghi vo thanh ghi 2 byte ca b m, gi l thanh ghi C-Word. Ni dung ca thanh ghi C-Word c gi l gi tr m tc thi ca b m v k hiu bng CV v CV_BCD. B m bo trng thi ca C-Word ra ngoi C-bit qua chn Q ca n. Nu CV<>0, C-bit c gi tr

37

1. Ngc li khi CV= 0, bit nhn gi tr 0. CV lun l gi tr khng m. B m s khng m li khi CV=0. i vi Counter, gi tr t trc PV ch c chuyn vo C -Word ti thi im xut hin sn ln ca tn hiu ti chn S. B m s c xa tc thi bng tn hiu xa R(Reset). Khi b m c xa c C-Word v C-bit u nhn gi tr 0. Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

2.4.3. B S_CU K hiu

Tham s C no CU S PV PV R CV CV_BCD Q

Kiu d liu Vng nh COUNTER BOOL BOOL WORD WORD BOOL WORD WORD BOOL C

M t Lt truy cp, phm vi truy cp ph thuc vo CPU

I, Q, M, L, D m ln I, Q, M, L, D Thit lp nh u vo ca counter I, Q, M, L, D Nhp gi tr truy cp nh C # v constant <value> trong khong 0-999 I, Q, M, L, D Ti gi tr thit lp couter I, Q, M, L, D Reset u vo I, Q, M, L, D Truy cp hin ti gi tr, s thp lc phn I, Q, M, L, D Truy cp hin ti gi tr, m BCD I, Q, M, L, D Trng thi ca cc truy cp

38

 M t S_CU (Up Counter) l ci sn vi gi tr ti PV u vo nu c mt cnh tch cc u vo S. Truy cp c thit lp li nu c gi tr"1" ti R u vo v gi tr s sau c thit lp v. S lt truy cp l tng thm mt khi thay i tn hiu ti CU u vo t "0" n "1" v gi tr ca cc truy cp t hn "999". Nu truy cp c thit lp v nu RLO = 1 ti u vo CU, vic Counter s tnh ph hp trong chu k qut tip theo. Tn hiu ti u ra Q l "1" nu m s ln hn s khng v "0" nu khng th Q=0 Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

2.4.4. B S_CD K hiu

39

Tham s C no

Kiu d liu COUNTER C

Vng nh

M t Lt truy cp, phm vi truy cp ph thuc vo CPU

CD S

BOOL BOOL

I, Q, M, L, D m li I, Q, M, L, D Thit lp nh u vo ca counter I, Q, M, L, D Nhp gi tr truy cp nh C # v constant <value> trong khong 0-999 I, Q, M, L, D Ti gi tr thit lp couter I, Q, M, L, D Reset u vo I, Q, M, L, D Truy cp hin ti gi tr, s thp lc phn I, Q, M, L, D Truy cp hin ti gi tr, m BCD I, Q, M, L, D Trng thi ca cc truy cp

PV

WORD

PV R CV

WORD BOOL WORD

CV_BCD

WORD

Q M t

BOOL

S_CU (Up COUNTER) l ci sn vi gi tr ti PV u vo nu c mt cnh tch cc u vo S.truy cp c thit lp li nu c mt "1" ti R u vo v gi tr s sau c thit lp v. S lt truy cp l tng thm mt khi nh nc thay i tn hiu ti CU u vo t "0" n "1" v gi tr ca cc truy cp t hn "999". Nu truy cp c thit lp v nu RLO = 1 ti u vo CU, vic truy cp s tnh ph hp trong chu k qut tip theo. Tn hiu ti u ra Q l "1" nu m s ln hn s khng v "0" nu khng th Q=0

40

 Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

2.4.5. Tham s <C no.>

---( SC ) nh gi tr Counter ---( SC ) Kiu d liu COUNTER Vng nh C M t S lng truy cp s c ci sn

K hiu

<prese value> M t

WORD

I, Q, M, L, D or Gi tr xc lp cho constant BCD(0 n 999)

--- (SC) (nh gi tr counter) ch thc hin nu c gi tr tch cc trong RLO. Vo thi im , gi tr nh sn chuyn vo truy cp c ch nh. Trng thi BR Kt qu 0 CC1 _ CC0 _ OV _ OS _ OR 0 STA X RLO _ /FC 0

2.4.6. ---( CU ) b m ln k hiu Tham s <C no.> M t --- (CU) (Up Counter Coil) C mi xung cnh ln trong RLO, b m COUNTER s tng 1 n v. Khi gi tr tng n 999 th tn hiu kch tng khng cn tc dng. <Cno.> ---( CU ) Kiu d liu COUNTER Vng nh C M t Lt truy cp m s; phm vi ph thuc vo CPU

41

 Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA _ RLO _ /FC 0

2.4.7. ---( CD ) b m xung K hiu <Cno.> ---( CD ) Tham s <C no.> M t --- (CD) (Down Counter Coil) C mi xung cnh ln trong RLO, b m Counter s gim 1 n v. Khi gi tr gim n 0 th tn hiu kch gim khng cn tc dng, ng thi lc ---( CD ) s OFF. Nu b m khc 0, ---( CD ) s ON. Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA _ RLO _ /FC 0 Kiu d liu COUNTER Vng nh C M t Lt truy cp m s; phm vi ph thuc vo CPU

2.5. khi d liu 2.5.1. ---(OPN) Lnh m khi d liu :DB hay DI K hiu Bin s <DB no.> <DI no.>
<DB no.> or <DI no.> ---(OPN)

Kiu d liu BLOCK_DB

B nh DB, DI

M t S DB / DI; phm vi ph thuc vo CPU

42

--- (OPN) (Open a Data Block) s m ra mt khi d liu c chia s (DB) hoc d liu V d mt khi (DI). Cc --- (OPN) chc nng l mt cuc gi v iu kin ca mt khi d liu. S lng cc khi d liu c chuyn vo DB hoc ng k DI. Cc DB DI lnh tip theo v truy cp vo cc khi tng ng, tu theo ni dung ng k. Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR _ STA _ RLO _ /FC _

2.6. nhm lnh nhy 2.6.1. ---(JMP)--- Lnh nhy v iu kin K hiu <tn nhn>

---( JMP )
M t Nhy nu RLO=1,Nu RLO=1 chng trnh s nhy n nhn nhy Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR _ STA _ RLO _ /FC _

2.6.2. ---(JMP)--- Lnh Nhy c iu kin K hiu M t --- (JMP) (nhy trong vng cm khi 1) chc nng nh mt bc nhy c iu kin khi RLO ca cc hot ng logic trc y l "1". Mt im n (nhn) cng phi tn ti cho mi --- (JMP). Tt c cc hng dn gia cc hng dn nhy v nhn khng c thc thi. 43 <tn nhn>

---( JMP )

Nu mt bc nhy c iu kin l khng c thc hin, nhng thay i RLO ti "1" sau khi hng dn nhy Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 0

2.6.3. ---( JMPN ) Lnh Jump-If-Not

K hiu

<nhn>

---( JMPN ) M t
Nhy nu RLO=0,Nu RLO=0 chng trnh s nhy n nhn nhy

Trng thi BR Kt qu 2.6.5. _ CC1 _ CC0 _ OV _ OS _ OR 0 STA 1 RLO 1 /FC 0

LABEL Lnh nhn

K hiu M t LABEL l nhn din cho ch n ca mt ch dn nhy.Cc k t u tin phi l ch ci, cc k t khc c th l ch ci hoc s. Mt nhn nhy (LABEL) phi tn ti cho mi --- (JMP) hoc --- (JMPN). 2.7. lnh Time 2.7.1. Lnh S_PULSE K hiu
S TV R
T no.

S_PULSE

Q BI BCD

44

Tham s T no.

Kiu d liu Vng nh TIMER T

M t M s timer:phm vi ph thuc vo CPU Bt u u vo Gi tr thi gian nh sn Thit lp li u vo gi tr thi gian cn li, nh dng s nguyn gi tr thi gian cn li, nh dng BCD Trng thi ca Timer

S TV R BI

BOOL S5TIME BOOL WORD

I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

BCD

WORD

I, Q, M, L, D

BOOL

I, Q, M, L, D

M t Nu tn hiu u vo S l 1 Timer c kch hot chy, khi tn hiu u vo S l 0 hoc chy thi gian t TV th Timer dng hoc tn hiu u vo R l 1 th Timer cng dng. Timer ch c tn hiu chy li khi c tn hiu u vo S( tc l u vo S chuyn trng thi t 0 ln 1). Tn hiu ra ca Q l 1 khi m Timer ang chy Ngc li Timer ngng chy th Q c tn hiu ra l 0 u ra BI lu gi tr m ca Timer theo dng Integer u ra BCD lu gi tr m ca Timer theo dng BCD Chc nng Timer ny l to xung c thi gian c t sn S thi gian c im ca mch xung hn gi

45

 Trng thi BR CC1 Kt qu 2.7.2 . _ _

CC0 _

OV _

OS _

OR X

STA X

RLO X

/FC 1

Lnh S_PEXT
T no.

K hiu

S_PEXT S TV R

Q BI BCD

Tham s T no. S TV R BI BCD Q

Kiu d liu Vng nh TIMER T BOOL S5TIME BOOL WORD WORD BOOL I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t M s timer:phm vi ph thuc vo CPU Bt u u vo Gi tr thi gian nh sn Thit lp li u vo gi tr thi gian cn li, nh dng s nguyn gi tr thi gian cn li, nh dng BCD Trng thi ca Timer

46

 M t Timer kch c nh, khi c tn hiu cnh ln u vo S Timer chy. nu thi gian t ti TV th Timer dng li. Trong qu trnh chy nu c tn hiu mi t u vo S th Timer li c tnh li t u Trong qu trnh chy m c tn hiu u vo R th Timer dng li u ra Q=1 khi Timer ang chy ngc li Q=0 khi Timer khng chy u ra BI lu gi tr hin thi ca Timer theo dng Integer u ra BCD lu gi tr hin thi ca Timet theo dng BCD S thi gian c im ca mch xung hn gi

Trng thi BR Kt qu 2.7.3 . _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

Lnh S_ODT
T no.
S_ODT

K hiu

S TV R

Q BI BCD

47

Tham s T no.

Kiu d liu Vng nh TIMER T

M t M s timer:phm vi ph thuc vo CPU Bt u u vo Gi tr thi gian nh sn Thit lp li u vo gi tr thi gian cn li, nh dng s nguyn gi tr thi gian cn li, nh dng BCD Trng thi ca Timer

S TV R BI

BOOL S5TIME BOOL WORD

I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

BCD

WORD

I, Q, M, L, D

Q M t

BOOL

I, Q, M, L, D

Nu tn hiu vo S l 1 th Timer bt u chy khi thi gian th ngng khi ng ra Q s c tn hiu ra l 1. Nu tn hiu u vo ca S vn gi trng thi tn hiu l 1, khi c tn hiu Reset (tn hiu u vo ca R=1) th tt c phi c Reset v 0 Cc nh BI lu gi tr hin thi ca Timer theo dng Integer, BCD lu gi tr hin thi ca Timer theo dng BCD S thi gian c im ca mch xung hn gi

48

 Trng thi BR CC1 Vit 2.7.4. _ _

CC0 _

OV _

OS _

OR X

STA X

RLO X

/FC 1

Lnh S_ODTS
T no.

K hiu

S_ODTS S TV R Q BI BCD

Tham s T no. S TV R BI BCD

Kiu d liu Vng nh TIMER T BOOL S5TIME BOOL WORD WORD I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t M s timer:phm vi ph thuc vo CPU Bt u u vo Gi tr thi gian nh sn Thit lp li u vo gi tr thi gian cn li, nh dng s nguyn gi tr thi gian cn li, nh dng BCD Trng thi ca Timer

Q M t

BOOL

I, Q, M, L, D

Timer kch c nh, khi c tn hiu xung cnh ln u vo S th Timer bt u chy, ng ra ca Q=1 khi Timer ang chy ngc li Timer dng th tn hiu ra ca Q l 0. Timer ch tt khi c tn hiu Reset v m ht thi gian Trong qua trnh Timer chy nu c s chuyn i tn hiu t u vo S thm 1 ln na th Timer s nh v tip tc chy khi ht thi gian ln trc. Cc nh BI lu gi tr hin thi ca Timer theo dng Integer, BCD lu gi tr hin thi ca Timer theo dng BCD

49

 S thi gian c im ca mch xung hn gi

Trng thi BR Vit _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

2.7.5.

Lnh S_OFFDT
T no.

K hiu

S_OFFDT

S TV R

Q BI BCD

Tham s T no. S TV R BI BCD Q

Kiu d liu Vng nh TIMER T BOOL S5TIME BOOL WORD WORD BOOL I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D 50

M t M s timer:phm vi ph thuc vo CPU Bt u u vo Gi tr thi gian nh sn Thit lp li u vo gi tr thi gian cn li, nh dng s nguyn gi tr thi gian cn li, nh dng BCD Trng thi ca Timer

 M t S_OFFDT u ra Q =1 khi c tn hiu tch cc ca chn u vo S v Timer chy khi bt du sn xung ca u vo S. Q=0 khi thi gian v u vo S vn =0. Khi c tn hiu Reset I0.1 th tt c tn hiu u = 0 Cc nh BI lu gi tr hin thi ca Timer theo dng Integer, BCD lu gi tr hin thi ca Timer theo dng BCD S thi gian c im ca mch xung hn gi

Trng thi BR CC1 Kt qu 2.7.6 . _ _

CC0 _

OV _

OS _

OR X

STA X

RLO X

/FC 1

Xung ---( SP ) <T no..> ---( SP ) <time value>

K hiu

51

Tham s <T no.>

Kiu d liu TIMER

Vng nh T

M t M s timer:phm vi ph thuc vo CPU Gi tr thi gian nh sn

<time value> M t

S5TIME

I, Q, M, L, D

--- (SP) (Pulse Timer Coil) bt u m thi gian quy nh vi <time value> khi c tn hiu cnh tch cc ca RLO. Ng ra ca Tno s On ngay lp tc. Khi ht thi gian ci t (<time value>) m tn hiu vo ca RLO vn l 1 th Tno vn On. Trong trng hp chua < time value> m tn hiu ca RLO l 0 th Time s c Reset v ng ra ca Tno s OFF. Trng thi BR CC1 Kt qu 2.7.7 . _ _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

Xung ---( SE ) <T no.> ---( SE ) <time value>

K hiu

Tham s <T no.>

Kiu d liu TIMER

Vng nh T

M t M s timer:phm vi ph thuc vo CPU Gi tr thi gian nh sn

<time value> M t

S5TIME

I, Q, M, L, D

---( SE ) (Extended Pulse Timer Coil) bt u m thi gian quy nh vi <time value> khi c tn hiu cnh tch cc ca RLO. Ng ra ca Tno s On ngay lp tc v Tno vn tip tc chy cho n khi thi gian c nh trc ngay c khi c s thay i ca RLO ti 0trc khi b m thi gian ht hn.

52

Cc tn hiu ra ca Tno l 1 khi m Tno ang chy. Time s c khi ng li khi c s thay i RLO t 0 n 1 trong khi hn gi ang chy. Trng thi BR Kt qu 2.7.8 . _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

Xung ---( SD ) K hiu <T no.> ---( SD ) <time value> Kiu d liu TIMER Vng nh T M t M s timer:phm vi ph thuc vo CPU Gi tr thi gian nh sn

Tham s <T no.>

<time value> M t

S5TIME

I, Q, M, L, D

---( SD ) (On Delay Timer Coil) bt u m thi gian quy nh vi <time value> khi c tn hiu cnh tch cc ca RLO. Khi thi gian ci t <time value> m khng c bo li th bit u ra ca Tno tc ng l 1. Khi nhng thay i RLO t "1" thnh "0" trong khi b m thi gian ang chy, hn gi c t li. Trong trng hp ny u ra ca Tno lun cho kt qu l 0 Trng thi BR Kt qu _ CC1 _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

53

2.7.9. Xung ---( SS ) K hiu <T no.> ---( SS ) <time value> Tham s <T no.> Kiu d liu TIMER Vng nh T M t M s timer:phm vi ph thuc vo CPU <time value> M t ---( SS ) (Retentive On-Delay Timer Coil) bt u m thi gian quy nh vi <time value> khi c tn hiu cnh tch cc ca RLO. Tn hiu ca Time l 1 nu gi tr thi gian t tri qua. Khi c tn hiu vo ca Reset th gi tr hin ti ca Time cng nh tn hiu u ra ca Ton c Reset v 0 Vic khi ng li b m thi gian vi gi tr thi gian quy nh nu nhng thay i RLO t "0" n "1" trong khi hn gi ang chy. Trng thi BR CC1 Kt qu 2.7.10. K hiu _ _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1 S5TIME I, Q, M, L, D Gi tr thi gian nh sn

Xung ---( SF ) <T no.> ---( SF ) <time value>

Tham s <T no.> <time value>

Kiu d liu TIMER S5TIME

Vng nh T I, Q, M, L, D

M t M s timer:phm vi ph thuc vo CPU Gi tr thi gian nh sn

54

 M t --- (SF) (Off-Delay Timer cun) bt u m thi gian quy nh nu c mt cnh tiu cc v tnh RLO. hn gi ny l "1" khi RLO l "1" hoc min l hn gi ang chy trong khong <time value>. Time thit lp li khi RLO i t "0" n "1" trong khi Time ang chy. Time lun lun khi ng li khi c thay i RLO t "1" thnh "0". Trng thi BR CC1 Kt qu _ _ CC0 _ OV _ OS _ OR X STA X RLO X /FC 1

2.8. cc php tnh trn word 2.8.1. Lnh WAND_W K hiu

WAND_ W EN IN1 IN2 ENO OUT

Tham s EN ENO IN1 IN2

Kiu d liu BOOL BOOL WORD WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

OUT WORD M t Lnh WAND_W thc hin vic giao 2 Word, kt qu c ct vo Word Trng thi BR CC1 Kt qu 1 X

M t Kch hot tnh nng u vo Kch hot tnh nng u ra Gi tr u tin cho hot ng logic I, Q, M, L, D gi tr th hai cho hot ng logic I, Q, M, L, D Kt qu t hot ng logic

CC0 0

OV 0

OS _

OR X

STA 1

RLO 1

/FC 1

55

2.8.2 Lnh WOR_W K hiu

WOR_W
EN IN1 IN2 ENO OUT

Tham s EN ENO IN1 IN2

Kiu d liu BOOL BOOL WORD WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

OUT WORD M t Trng thi BR Vit 2.8.3. 1 CC1 X CC0 0

M t Kch hot tnh nng u vo Kch hot tnh nng u ra Gi tr u tin cho hot ng logic I, Q, M, L, D gi tr th hai cho hot ng logic I, Q, M, L, D Kt qu t hot ng logic

Lnh WOR_W: lnh thc hin vic hp 2 Word, kt qu c ct vo Word

OV 0

OS _

OR X

STA 1

RLO 1

/FC 1

Lnh WAND_DW
WAND_DW EN IN1 IN2 ENO OUT

K hiu

Tham s EN ENO IN1 IN2 OUT

Kiu d liu BOOL BOOL WORD WORD WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Kch hot tnh nng u vo Kch hot tnh nng u ra Gi tr u tin cho hot ng logic I, Q, M, L, D gi tr th hai cho hot ng logic I, Q, M, L, D Kt qu t hot ng logic

56

 M t Lnh WAND_DW : lnh thc hin vic giao 2 Double Word, kt qu c ct vo Double Word. Trng thi BR Vit 1 CC1 X CC0 0 OV 0 OS _ OR X STA 1 RLO 1 /FC 1

2.8.4. Lnh WOR_DW K hiu

WOR_DW EN IN1 IN2 ENO OUT

Tham s EN ENO IN1 IN2 OUT M t

Kiu d liu BOOL BOOL WORD WORD WORD

Vng nh I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t Kch hot tnh nng u vo Kch hot tnh nng u ra Gi tr u tin cho hot ng logic gi tr th hai cho hot ng logic Kt qu t hot ng logic

Lnh WOR_DW : lnh thc hin vic hp 2 Double Word, kt qu c ct vo Double Word. Trng thi BR Kt qu 2.8.5. K hiu 1 CC1 X CC0 0 OV 0 OS _ OR X STA 1 RLO 1 /FC 1

Lnh WXOR_W
WXOR_W EN IN1 IN 2 ENO OUT

57

Tham s EN ENO IN1

Kiu d liu BOOL BOOL WORD

Vng nh

M t

I, Q, M, L, D Kch hot tnh nng u vo I, Q, M, L, D Kch hot tnh nng u ra I, Q, M, L, D Gi tr u tin cho hot ng logic I, Q, M, L, D gi tr th hai cho hot ng logic I, Q, M, L, D Kt qu t hot ng logic

IN2

WORD

OUT M t

WORD

Lnh WXOR_W : Lnh thc hin vic Xor Word, kt qu c ct vo Word Trng thi BR Vit 2.8.6. 1 CC1 X CC0 0 OV 0 OS _ OR X STA 1 RLO 1 /FC 1

Lnh WXOR_DW K hiu

WOR_DW
EN IN1 I ENO OUT

k hiu

Tham s EN ENO IN1 IN2 OUT

Kiu d liu Vng nh BOOL BOOL WORD WORD WORD

M t

I, Q, M, L, D Kch hot tnh nng u vo I, Q, M, L, D Kch hot tnh nng u ra I, Q, M, L, D Gi tr u tin cho hot ng logic I, Q, M, L, D gi tr th hai cho hot ng logic I, Q, M, L, D Kt qu t hot ng logic

58

 M t Lnh WXOR_DW : lnh c thc hin vic Xor 2 Double Word, kt qu c ct vo Double Word Trng thi BR Vit 1 CC1 X CC0 0 OV 0 OS _ OR X STA 1 RLO 1 /FC 1

59

Ch-ng 3. b bin i PID trn S7-300

3.1. nhng module pid mm c trong step7 Phn mm Step7 cung cp cc module mm PID iu khin cc i tng c m hnh lin tc nh l, ng c, mc u ra ca i tng c a vo u vo ca b iu khin qua cc cng vo tng t ca cc module vo tng t ca Simatic S7-300/400. Tn hiu ra ca b iu khin c nhiu dng v c a n cc c cu chp hnh qua nhng module vo ra khc nhau nh: Qua cng ra tng t ca module ra tng t (AO), Qua cc cng ra s ca module ra s (DO), hoc Qua cc cng pht xung ra tc cao. Mi module mm PID u c mt khi d liu ring (DB) lu gi cc d liu phc v cho chu trnh tnh ton thc hin lut iu khin. Cc khi hm FB ca module mm PID u cp nht c nhng khi d liu ny mi thi im. Module mm FB PULSEGEN c s dng kt hp vi module FB CONT_C nhm to ra b iu khin c tn hiu dng xung tc cao thch ng vi nhng c cu chp hnh t l. Mt b iu khin PID mm c hon thin thng qua khi hm FB nhiu chc nng to ra tnh linh hot cao trong thit k. Ngi s dng c th chn chc nng ny hoc loi b cc chc nng khng cn cho h thng. Cc chc nng c bn khc nh x l tn hiu ch o, tn hiu qu trnh v tnh ton cc bin khc cng vi b iu khin theo thut iu khin PID cng c tich hp sn trong mt module iu khin mm. Nhng module mm khng ton nng ti mc c th ng dng c vo mi bi ton iu khin. c tnh iu khin v tc x l ca module PID mm ph thuc va loi CPU c chn gii quyt bi ton iu

60

khin. Do khi x l mt mch vng iu khin ngi ta phi thc hin cng vic trch mu tn hiu u vo cho mch vng iu khin (lin quan n tn hiu bo ngt cho chu k thi gian OB30OB38), nn cn phi c s tng thch gia s mch vng iu khin PID v kh nng cng nh tc tnh ton ca CPU. Nu bi ton iu khin yu cu tn sut cp nht cng cao th s vng iu khin phi cng gim. Ch nhng bi ton c s vng iu khin t ngi ta mi c th s dng cc module mm c tn sut truy nhp cao. Tt c cc module PID mm u cung cp nhiu gii php la chn lut iu khin trong khi thit k b iu khin ph hp vi i tng nh: lut iu khin t l P, lut iu khin t l-vi phn PD, lut iu khin t l-tch phn PI Cht lng ca h thng hon ton ph thuc vo cc tham s ca b iu khin. Do , iu kin bt buc m bo thnh cng trong thit k l ngi s dng phi c m hnh i tng chnh xc. cng chnh l nhc im c bn ca phng php iu khin kinh in. Ph thuc vo c cu chp hnh, ngi s dng c th chn c module mm PID tng thch. Ba module PID c tch hp trong phn mm Step7 ph hp vi ba kiu c cu chp hnh nu trn l: 1) iu khin lin tc vi module mm FB41 (tn hnh thc CONT_C) 2) iu khin bc vi module mm FB42 (tn hnh thc CONT_S) 3) iu khin kiu pht xung vi khi hm h tr FB43 (tn hnh thc PULSEGEN). Vi i tng trong ti ny, module mm FB41 cn c tm hiu gii quyt bi ton. 3.2. iu khin lin tc vi fb41 cont_c 3.2.1. Gii thiu chung v FB41 FB41 CONT_C c s dung iu khin cc qu trnh k thut vi cc bin u vo v u ra tng t trn c s thit b kh trnh Simatic. Trong khi thit lp tham s, c th tch cc hoc khng tch cc mt s thnh

61

phn chc nng ca b iu khin PID cho ph hp vi i tng. C th s dng module mm PID nh mt b iu khin vi tn hiu ch o t cng (fed setpoint) hoc thit k mt h thng iu khin nhiu mch vng theo kiu iu khin cascade. Nhng chc nng iu khin c thit k trn c s ca thut iu khin PID ca b iu khin mu vi tn hiu tng t. Cu trc modul mm PID FB41 CONT_C. S cu trc ca module mm FB41 CONT_C c minh ha nh sau:
SP-INT PVPER_ON PV_INT GAIN DEADBAND

0
PV_PER CRP-IN PV-NORM

%
PV-FAC PV-OFF

1
PV

ER

INT

TI, I-ITL-ON I-ITLVAL DIF

1 0.0 0 1 0.0 0 1
0.0
0
D-SEL

P-SEL

LMN-P DISV

I-SEL

LMN-I

TD,TM,LAG

LMN-D

MAN

MAIL_ON

QLMN-HLM QLMN-LLM LMNLIMIT LMN_NORM CRP_OUT

LMN

%
LMN_HLM LMN_LLM LMN_FAC LMN_OFF

LMN_PER

Hnh 3.1: S cu trc modul mm FB41 Module mm PID bao gm tn hiu ch o SP-INT, tn hiu ra ca i tng PV-PER, tn hiu gi m phng tn hiu ra ca i tng PV-IN, cc bin trung gian trong qu trnh thc hin lut v thut iu khin PID nh PVPER-ON, P-SEL, I-SEL, D-SEL,MAN-ON

62

Tn hiu ch o SP-INT: c nhp di dng du phy ng Tn hiu ra ca i tng PV-PER: Thng qua hm ni ca FB41 c tn CRP-IN, tn hiu ra ca i tng c th dc nhp di dng s nguyn c du hoc s thc du phy ng. Chc nng ca CRP-IN l chuyn i kiu biu din ca PV-PER t dng s nguyn sang s thc du phy ng c gi tr nm trong khong -100 n 100% theo cng thc: Tn hiu ra ca CRP-IN = PV-PER
100 27648

Chun ha: Chc nng ca hm chun ha PV-NORM tn hiu ra ca i tng l chun ha tn hiu ra ca hm CRP-IN theo cng thc: Tn hiu ra ca PV-NORM = (Tn hiu ra ca CRP-IN) PV-FAC-OFF Hai tham tr khng ch di gi tr cho php ca PV-NORM l PV-FAC v PV-OFF. Mc nh PV-FAC ca hm PV-NORM c gi tr bng 1 v PVOFF c gi tr 0. Lc nhiu tc ng trong ln cn im lm vic: Tn hiu sai lch gia tn hiu ch o v tn hiu ra ca i tng. N dc ta ngay ra trong FB41 l du vo ca khi DEADBAND c tc dng lc nhng dao ng nh xung quanh gi tr xc lp. Nu khng mun s dng DEADBAND hoc vi i tng m c th b qua s nh hng ca nhiu trong ln cn im lm vic ta chn DEAD-W=0. Chn lut iu khin trn module FB41 CONT_C Thut PID c thit k theo kiu song song ca ba thut iu khin n l t l (P), tch phn (I), vi phn (D) theo s cu trc sau:
P-SEL GAIN INT

TI, I-ITL-ON I-ITLVAL DIF

0.0 0 1 0.0 0

I-SEL

1
0.0
0
D-SEL

TD,TM,LAG

Hnh 3.2:Thut iu khin PID

63

Chnh v cu trc song song nh vy nn ta c th thng qua cc tham tr P-SEL, I-SEL hay D-SEL m tch hp c cc thut iu khin khc nhau t b iu khin mu ny nh thut iu khin P,PI, PD, PID. Khai bo tham s v cc bin ca Modul mm PID Chng ta c th khai bo tham s v cc bin cho b iu khin trong khi d liu c s thng qua cc bc sau: START SIMATIC STEP7PID PARAMETTER ASIGNMENT Trn thanh cng c trong ca s ca mn hnh son tho c biu tng ca cc hm th vin c trong Step7. Kch chut vo biu tng ny ta nhn c bng danh mc cc khi hm th vin ngay trong ca s mn hnh son tho. t gi tr cho khi FB41 Phn mm cho php chn ch t ng (automatic mode) hoc ch bng tay. ch bng tay cc gi tr ca cc bin c chn bng tay. B tch phn (INT) t thit lp ch LNM-LNM-P-DISV v b vi phn (DIF) t ng v 0. iu m bo vic chuyn ch t thit lp gi tr bng tay v ch t ng khng gy mt bin i t ngt no i vi cc bin c thit lp gi tr bng tay. Cng c th gii hn cho cho cc gi tr c thit lp bng tay nh hm LMNLIMIT.Mt bt c s c gi tr bng 1 khi bin vo coa gi tr vt qu gii hn chn. Hm LMN-NORM s chun ha tn hiu ra ca hm LMNLIMIT theo cng thc: LMN = (Tn hiu ra ca LMNLIMIT) * LMN-FAC + LMN-OFF Mc nh LMN-FAC c gi tr bng 1, cn LMN-OFF c gi tr bng 0. Cc gi tr t bng tay c th theo mt cch biu din ring. Hm CRP OUT c chc nng bin i t kiu biu din s thc du phy ng sang kiu biu din ring theo cng thc: LMN-PER = LMN *
27648 100

Ngoi ra nhiu c th c lc trc bng cch a qua u vo DISV.

64

3.2.2. Khai bo tham bin hnh thc u vo v u ra khi FB41 CONT_C c 26 tham bin hnh thc u vo nh sau: Tn Kiu Phm vi gii hn Gi tr mc nh bin d liu COM- BOOL RST M t chc nng

FALSE COMPLETE RESTART Khi chc nng khi to li h thng hon ton khi u vo complete restart c thit lp gi tr logic true

MAN- BOOL ON

TRUE

MANUAL VALUE ON Khi u vo manual value on c gi tr logic TRUE mch vng iu khin s b ngt, cc fa tr s c thit lp bng tay

PVPE BOOL R-ON

FALSE PROCESS VARIABLE PERIPHERAL ON Khi c bin qu trnh t cc cng vo/ra u vo PV-PER phi c ni vi cc cng vo/ra v u vo process variable peripheral on c gi tr logic TRUE

P-SEL BOOL

TRUE

PROPORTIONAL ACTION ON Hot ng ca b iu khin PID c th tch cc hoc khng tch cc tng phn ring trong thut iu khin PID. Thut iu khin t l khi gi tr logic TRUE c thit lp ti cng vo proportional action on.

65

I-SEL BOOL

TRUE

INTERGRAL ACTION ON Hot ng ca b iu khin PID c th tch cc hoc khng tch cc tng phn ring trong thut iu khin PID. Thut iu khin tch phn c kch hot khi gi tr logic TRUE c thit lp ti cng vo intergral action on

INT- BOOL HOLD

FALSE INTERGRAL ACTION HOLD u ra ca b iu khin tch phn c th b ng lnh (khng c s dng) khi thit lp gi tr logic TRUE cho u vo intergral action hold.

I-ITL- BOOL ON

FALSE INITIALIZATION INTERGRAL ACTION

OFTHE

u ra ca b iu khin tch phn c th c ni vo cng I-ITLVAL nu nh cng vo initialization of the intergral

action on c gi tr logic TRUE. DSEL BOOL FALSE DERIVATE ACTION ON Hot ng ca b iu khin PID c th tch cc hoc khng tch cc tng phn ring trog htut iu khin PID. Thut iu khin vi phn c kch hot khi gi tr logic TRUE c thit lp ti cng vo derivate action on

66

CYCLE TIME 1ms

T#1s

SAMPLING TIME Thi gian ly mu l khong thi gian khng i gia cc ln khi c cp nht

SPINT

REAL -100100% Hoc gi tr vt l

0.0

INTERNAL SETPOINT u vo internal setpoint c s dng thit lp tn hiu ch o (tn hiu mu).

PV-IN REAL -100100% Hoc gi tr vt l

0.0

PROCESS VARIBLE IN Gi tr khi to c th t u vo process variable on hoc t bin qu trnh c biu din di dang s thc du phy ng.

PV- WORD PER

W#16#00 PROCESS VARIABLE 00 PERIPHERAL Bin qu trnh c ni vi CPU thng qua cng vo tng t .

MAN REAL -100100% Hoc gi tr vt l GAIN REAL

0.0

MANUAL VALUE Cng vo manual value c s dng t gi tr bng cc hm gia din.

2.0

PROPOTIONAL GAIN u vo propotional gain c s dng thit lp h s t l cho b iu khin theo lut t l

TI

TIME CYCLE

T#20s

RESET TIME Cng Vo reset time c s dng thit lp hng s thi gian tch phn cho b iu khin tch phn.

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TD

TIME CYCLE

T#10s

DERIVATE TIME Cng vo derivate times dng thit lp hng s thi gian vi phn cho b iu khin vi phn.

TMLAG

TIME CYCLE

T#2s

TIME LAG OF DERIVATE ACTION Thi gian tch cc ca lut iu khin vi phn c chn thng qua cng vo time lag of derivate action.

DEA REAL >=0.0% hoc B-W gi tr vt l

0.0

DEAD BAND WIDTH Mt vng km nhy c s dng x l tn hiu sai lch. rng ca vng km nhy c t thng qua cng vo dead band width.

LMN- REAL LMN-LLM HLM vt l LMN- REAL -100%... LLN LMN-LLM hoc gi tr vt l PV- REAL FAC 100% hoc gi tr

100.0

MANIPULATED VALUE HIGH LIMIT Gi tr hn ch trn c thit lp bng tay qua cng vo manipulated value high limit.

0.0

MANIPULATED VALUE LOW LIMIT Gi tr hn ch di c thit lp bng tay qua cng vo manipulated value low limit.

1.0

PROCESS VARIALE FACTOR Bin qu trnh c nhn vi mt h s cho ph hp vi phm vi qui nh ca bin ny. H s c chn thng qua cng vo process variable factor.

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LMN- REAL FAC

1.0

MANIPULATED VALUE FACTOR Gi tr gii hn c nhn vi mt h s cho ph hp vi phm vi qui nh ca bin qu trnh. H s ny c t qua cng vo manipulated value factor.

LMN- REAL OFF

0.0

MANIPULATED VALUE OFFSET Gi tr gii hn c nhn vi mt h s cho ph hp vi phm vi qui nh ca bin qu trnh. H s ny c t qua cng vo manipulated value offset.

IITLV AL

REAL -100100% Hoc gi tr vt l

0.0

INITIALIZATION

VALUE

OF

THE INTERGRAL ACTION Gi tr u ra ca b iu khin tch phn c c thit lp thng qua cng vo initialization value of the intergral action.

DISV REAL -100100% Hoc gi tr vt l

0.0

DISTURBANCE VARIABLE Khi iu khin h thng bng phng php feedforward th mt gi tr b nhiu c t thng qua cng vo disturbance variable.

PV- REAL OF

1.0

PROCESS VARIALE OFFSET Bin qu trnh c cng vi mt lng b cho ph hp vi phm vi qui nh ca bin ny. Gi tr b c chn thng qua cng vo process variable

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 Khai bo tham bin hnh thc u ra: Tn bin LMN Kiu d liu REAL Mc nh 0.0 M t MANIPULATED VALUE Gi tr ra c thit lp bng tay thng qua cng ra manipulated value. LMN-PER WORD W#16# 0000 MANIPULATED PERIPHERAL Gi tr u ra thit lp bng tay theo kiu biu din ph hp vi cc cng vo/ra tng t c chn qua cng manipulated value peripheral. QLMNHLM BOOL FALSE HIGH LIMIT OF MANIPULATED VALUE

VALUE RACHED Cng ra high limit of manipulated value reached thng bo gi tr bin qua trnh vt qu gi tr gii hn trn.

QLMNLLM

BOOL

FALSE

LOW LIMIT

OF

MANIPULATED

VALUE RACHED Cng ra low limit of manipulated value reached thng bo gi tr bin qua trnh nh hn qu gi tr gii hn di.

LMN-P

REAL

0.0

PROPOTIONAL COMPONENT Tn hiu ra ca b iu khin t l c xut qua cng ra ca propotional component

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LMN-I

REAL

0.0

INTEGRAL COMPONENT Tn hiu ra ca b iu khin vi phn c xut qua cng ra integral component.

LMN-D

REAL

0.0

DERIVATIVE COMPONENT Tn hiu ra ca b iu khin vi phn c xut qua cng ra derivative component.

PV

REAL

0.0

PROCESS VALUE Tn hiu qu trnh c xut qua cng ra process value.

ER

REAL

0.0

ERROR SIGNAL Tn hiu sai lch c xut qua cng ra error signal.

3.3. iu khin bc vi fb42 cont_s 3.3.1. M t chung FB42 CONT_S l module mm c tch hp sn trong phn mm STEP7. FB42 CONT_S c s dng trn c s Simatic S7 -300/400 iu khin cc i tng k thut vi u ra ca b iu khin l tn hiu s. Tn hiu ra s hon ton thch hp i vi cc c cu chp hnh kiu tch phn. Trong khi thit lp tham s, ngi thit k c th tch cc hoc khng tch cc b iu khin PI bc cho ph howpk vi yu cu ca bi ton iu khin t ra. C th s dng module mm FB42 CONT_s nh mt b iu khin theo lut PI vi tn hiu ch o t trc hoc c th s dng trong mch vng iu khin ph trong h thng thit k da trn nguyn tc iu khin cascade. Chc nng ca b iu khin ny hon ton tun theo thut

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iu khin PI vi tn hiu qu trnh l tn hiu tng t v tn hiu ra ca b iu khin l tn hiu s. Mt phn trong cc chc nng ca module mm ny l ng vai tr ca mt b iu khin PI c cc gi tr v tn hiu u ra s t bng tay. Lm vic ch ny b iu khin bc khng cn n tn hiu hi tip.

Hnh 3.3: S cu trc nguyn l ca module mm FB42 CONT_S Tn hiu ch o: c biu din kiu s thc du phy ng v c thit lp t cng vo SP_INT. Tn hiu ra ca i tng: Tn hiu ra ca i tng c a thng t cng vo tng t theo kiu s nguyn hoc c truyn sau khi bin i sang kiu s thc du phy ng. Hm CRP_IN c chc nng bin i gi

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tr truyn t cng vo tng t sang kiu s thc du phy ng trong khong t -100.0% n 100.0% theo cng thc: Tn hiu ra ca CRP_IN= PV_PER*
100.0 27648.0

Chun ha: Chc nng ca hm PV_NORm l chun ha tn hiu ly t u ra ca hm CRP_IN theo cng thc: Tn hiu ra ca PV_NORM=(Tn hiu ra ca CRP_IN)*PV+PV_OFF Mc nh PV_FAC c gi tr bng 1 v PV_OF c gi tr bng 0. Lc nhiu c tc ng trong ln cn im lm vic: Tn hiu sai lch l hiu gia tn hiu ch o v tn hiu ra ca i tn. Ging nh FB41, trong FB42 cng c khi DEADBAND c thit k ngay sau tn hiu sai lch v trc phn iu khin theo lut lc nhng dao ng nh quanh gi tr xc lp bng cch to ra mt vn km nhy. Nu gi tr DEADB_W=0 th vng km nhy khng tn ti. 3.3.2. Thut iu khin PI bc Khi hm FB42 ca module mm PID lm vic khng cn phi c tn hiu hi tip. Chc nng ca lut I trong thut iu khin PI v tn hiu sai lch c tnh trong mt b tch phn INT, sau so snh vi tn hiu ra ca b iu khin theo lut t l nh mt gi tr hi tip. Hiu ca php so snh ny c a vo mt role ba v tr c tr Three_ST v u ra ca role ny iu khin b pht xung ra PULSEOUT iu khin c cu chp hnh. C th gim tn s ng ct ca b iu khin bng cch to ra vng tr khi chuyn v tr role. S thut ton biu din trong hnh 6.4?? Ngoi ra, gim nh hng ca nhiu trong trng hp iu khin khng hi tip, c th lc nhiu cho h bng cch a tn hiu vo u vo DISV ca b lc nhiu. 3.3.3. Khi ng v thong bo li H thng c khi to li hon ton khi cng vo COM_RST c gi tr logic bng 1. Tt c cc cng ra nhn gi tr mc nh. 73

Khi hm FB42 ny khng c kh nng t kim tra li bn trong. N khng s dng cng ra bo kiu li RET_VAL. 3.3.4. Tham bin hnh thc u vo Tt c cc tham s hnh thc u vo ca FB42 CON_S gm: Phm Kiu Mc Tham s vi lm M t d liu nh vic COM_RST BOOL FALSE COMPLETE RESTART Modle mm c khi to li hon ton khi cng vo complete restart c gi tr logic bng 1. LMNR_HS BOOL FALSE HIGH LIMT OF POSITION FEEDBACK SIGNAL Tn hiu actuator at upper limit stop c ni n cng vo high limit position feedback Cng ra c cu chp hnh s b cm khi LMNR_HS =TRUE LMNR_LS BOOL FALSE LOW LIMT OF POSITION FEEDBACK SIGNAL Tn hiu actuator at upper limit stop c ni n cng vo low limit of position feedback Cng ra c cu chp hnh s b cm khi LMNR_LS =TRUE LMNR_O N BOOL FALSE MANUAL ACTUATING SIGNALS ON X l tn hiu chp hnh c chuyn sang ch bng tay qua cng vo manual actuating signal on

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LMNUP

BOOL

FALSE ACTUATING SIGNALS UP Tn hiu ra QLMNUP c thit lp qua cng vo actuating signal up vi cc tn hiu chp hnh bng tay.

LMNDN

BOOL

FALSE ACTUATING SIGNALS DOWN Tn hiu ra QLMNDN c thit lp qua cng vo actuating signal up vi cc tn hiu chp hnh bng tay.

PVPER_O BOOL N

FALSE PROCESS VARIABLE PERIPHERAL ON Mun c cc tn hiu qu trnh t cc cng vo process variable on phi c gi tr logic1(cho php c)

CYCLE

TIME

>= 1ms

SAMPLING TIME Khong thi gian gi cc ln gi khi phi c nh. Thi gian trch mu (sampling time) c thit lp qua cng vo sampling time

3.4. khi hm to xung fb43 pulsegen Khi hm FB43 PULSEGEN c tc dng h tr vic thit k mt b iu khin PID hai hoc ba v tr vi b to xung theo nguyn tc iu bin

hnh 3.4: Nguyn l iu bin ca FB43 PULSEGEN

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N c bin i tn hiu u vo IVN dng s thc ( thng l u ra LMN ca module mm PID) thnh mt dy xung c chu k c nh v rng tng ng vi ln ca tn hiu u vo. Khi hm FB43 PULSEGEN thng c s dng cng vi FB41 CONT_C c c mt b iu khin PID vi tn hiu dng xung

Hnh3.5: b iu khin PID vi u ra dng xung

3.5. khi to module mm PID trn s7-300 Khi to New Project kch p vo vo biu tng SIMATIC S7-300 ta c mn hnh chnh ca Step7. Ta chn Flie=> New Xy dng cu hnh phn cng cho trm PLC

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Trc ht ta khai bo cu hnh cng cho trm PLC vi S7-300 bng cch vo insert=> Station => Simatic 300 station.

Project chuyn sang dng khng rng vi th mc con trong n c tn mc nh l Simatic 300(1). Ta c th thay i c tn ny. Th mc Simatic 300(1) cha tp tin v cu hnh cng ca trm.

77

 to mn hnh khai bo phn cng, ta nhy chut vo biu tng Hardware trong hp thoi hin ra ta khai bo thanh ray( rack) v cc module c trn thanh rack .

Sau khi khai bo xong cu hnh phn cng cho mt trm PLC v quay tr v ca s chnh ca Step7 ta thy trong th mc Simatic 300(1) by gi c thm th mc con CPU314

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Trong th mc CPU314 ta c cc th mc con nh sau: Source files, Blocks, Symbols

Xy dng chng trnh FB41 v FB42 trn khi OB1 Kch vo Blocks => OB1 ta c mn hnh nh sau:

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Khi OB1 c vi khi to Libraries=> Standard Library => PID Control Blocks=> FB41 CONT_C ta c mn hnh nh sau:

Sau khi xy dng c khi FB41 di dng LAD ta vo View=> STL hay dung t hp phm nng Ctrl+2, chng trnh s t ng chuyn t dng LAD sang STL

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Khi xy dng xong hai khi FB41 v FB42 ta quay tr v mn hnh chnh ca Step7-300 ta c cc khi c xy dng nh sau:

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KT LUN
Sau 12 tun i su nghin cu tm ti n tt nghip, di s phn cng ca cc thy c trong b in t ng khoa in in t, c s ch bo nhit tnh ca thy Ths. ng Hng Hi cng vi s c gng, n lc ht sc ca bn thn em, bn n tt nghip hon chnh. n t c kt qu nh sau: - Nghin cu thnh cng b PID trn PLC S7 300. - S dng c phn mm S7-300 thnh tho Tuy nhin do thi gian gp rt nn n khng trnh khi nhng hn ch: Nghin cu phn mm cn thiu st, tuy nhin cng l s thnh cng ca bn thn em. Em xin chn thnh cm n! Hi Phng, ngy 11 thng 7 nm 2010 Sinh vin

Nguyn Trng Ngc

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TI LIU THAM KHO

[1] SIEMENS, SIMATIC (2006), S7 300/400 and M7 300/400 Programmable controller hardware and Intallation. [2] SIEMENS, SIMATIC (2006), Control [3] SIEMENS, SIMATIC (2006), Ladder Logic (LAD) for S7-300 and S7400 Programming [3] Nguyn Don Phc, Phan Xun Minh, V Vn H (2002), T ng ha vi Simatic S7 300, NXB Khoa hc v K thut. [4] Nguyn Vn Ha (2001), c s l thuyt iu khin t ng, NXB Khoa hc v k thut Softwarefor S7-300 and S7-400 PID

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