LAB 5: Read Only Memory (ROM) and Random Access Memory (RAM) Objective: 1) To learn and understand the

procedure of designing and modeling RAM and ROM in VHDL 2) Design a simple system using RAM and ROM

a) Design of ROM Figure 1 is the block diagram of entity ROM. This module has 2 bits address and 8 bits data. Write VHDL code in Figure 2 and simulate the result. You should get the simulation result similar in Figure 3.

Figure 1: Block diagram of Entity ROMLab4

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity RomLab4 is port(Clock : in std_logic; Read : in std_logic; Address : in std_logic_vector(1 downto 0); Data_out: out std_logic_vector(7 downto 0)); end RomLab4; architecture BehavRomLab4 of RomLab4 is type ROM_Array is array (0 to 3)of std_logic_vector(7 downto 0); constant Content: ROM_Array := ( 0 => "10000001", -- value in ROM at location 0H 1 => "10000010", -- value in ROM at location 1H 2 => "10000011", -- value in ROM at location 2H 3 => "10000100", -- value in ROM at location 3H OTHERS => "11111111"); begin process(Clock)--, Read, Address) begin if( Clock'event and Clock = '0' ) then if( Read = '1' ) then Data_out <= Content(conv_integer(Address)); else Data_out <= "ZZZZZZZZ"; end if; end if; end process; end BehavRomLab4;

Figure 2: VHDL code for ROMLab4 module

Figure 3: Simulation result of ROMLab4 module

b) Design of RAM

Figure 4 is an entity module of RAMLab4. This module has 2 bits address, 8 bit data input and 8 bits data outputs. VHDL code for this module is shown in Figure 5. Write this code and simulate the result. The result should be similar to Figure 6. The first process involves reading data from Data_In and store in the RAM. Then the data is read out again from this module.

Figure 4: Block diagram of RAMLab4 module

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity RamLab4 is generic(width: integer:=8; depth: integer:=4; addr: integer:=2); port( Clock,Write,Read :in std_logic; Addrs : in std_logic_vector(addr-1 downto 0); Data_Out: out std_logic_vector(width-1 downto 0); Data_In: in std_logic_vector(width-1 downto 0)); end RamLab4; architecture behavRamLab4 of RamLab4 is type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; begin process(Clock) begin if (Clock'event and Clock='1') then if Write='1' then tmp_ram(conv_integer(Addrs)) <= Data_In; --write Data_Out <= "ZZZZZZZZ"; elsif Read = '1' then Data_Out <= tmp_ram(conv_integer(Addrs)); else Data_Out <= "ZZZZZZZZ"; end if; end if; end process; end behavRamLab4;

Figure 5: VHDL code for RAMLab4 module

Figure 6: Simulation result of RAMLab4 modul

Exercise: 1. Write a VHDL code to perform the following function. Data from ROM1 and ROM2 is added and the result is stored in RAM. You must design each module first and integrate all modules by using port map design techniques. Show in detail the flowchart of control unit.

Block diagram of overall system 2. Design a system that has the following structure.

The output of each value of X is pre-calculated and stored in ROM. Write VHDL code and show the simulation result.