FPGA/PLD IP

INVENTRA
T H E I N T E L L I G E N T A P P R O A C H T O

TM

I N T E L L E C T U A L

P R O P E R T Y

Inventra IPX

LeonardoSpectrum Altera Release (PC / UNIX edition)

v1.100

Release Note

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12/01 RN-69501.011-FC 2001 Mentor Graphics Corporation All Rights Reserved

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Confidential. May be photocopied by licensed customers of Mentor Graphics for internal business purposes only. The product(s) described in this document are trade secret and proprietary products of Mentor Graphics Corporation or its licensors and are subject to license terms. No part of this document may be photocopied, reproduced or translated, disclosed or otherwise provided to third parties, without the prior written consent of Mentor Graphics. The document is for informational and instructional purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in the written contracts between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in the subdivision (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. A complete list of trademark names appears in a separate Trademark Information document. Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070. This is an unpublished work of Mentor Graphics Corporation.

For Customer Support on this product:

Call up the Inventra Customer Inquiry Service at http://www.mentor.com/supportnet Email support_net@mentor.com Phone 1-877-763-8470 (toll-free in US, Mexico and Canada) (Customers in other parts of the world can access this service via the AT&T USA Direct service in their country.) Full details are given in the Customer Support Handbook, provided in Adobe Acrobat format as custhb.pdf in the /databook directory on the Inventra Soft Cores CD. Please note the checklists of actions to take and information to have to hand when contacting Inventra Customer Support that are given in the Customer Support Handbook.

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TABLE OF CONTENTS
1. 2.

RELEASE NOTE

INTRODUCTION ............................................................................................4 THE INVENTRA IPX PACKAGE ..............................................................4 2.1. System Requirements...............................................................................4 2.2. Package Contents......................................................................................4 2.3. User Guide.................................................................................................6 2.4. Core Specifications...................................................................................6 2.5. Core Datasheets........................................................................................6 2.6. Adobe Acrobat Reader Software (CD Only).......................................6

3.

THE CORES OFFERED IN THE CURRENT RELEASE....................7 3.1. Core List.....................................................................................................7 3.2. Core Information......................................................................................7 3.2.1. 3.2.2. 3.2.3. 3.2.4. 3.2.5. 3.2.6. 3.2.7. 3.2.8. 3.2.9. M1284H ......................................................................................7 M16550A ....................................................................................8 M16x50........................................................................................8 M8051..........................................................................................8 M82365SL...................................................................................9 M8237A.......................................................................................9 M8255........................................................................................10 M8490........................................................................................10 MI2C..........................................................................................10

3.2.10. MPCMCIA1 .............................................................................11 4. REVISION HISTORY....................................................................................12 4.1. Issue 1.100 ...............................................................................................12

CONTENTS

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1. INTRODUCTION
This is the Release Note for Version 1.100 of Inventra IPX. This version of Inventra IPX comprises cores for implementation using the Mentor Graphics LeonardoSpectrum synthesis tool and the Altera Quartus II place & route tool in the Altera encrypted IP flow on either a PC or a UNIX-based workstation. (Full details of the system requirements are given in Section 2.1 below.) This document gives detailed information about the cores and the other supporting materials delivered in Version 1.100 of the Inventra IPX package. PLEASE READ THE CORE INFORMATION SECTION IN THIS RELEASE NOTE. THIS CONTAINS INFORMATION WHICH COULD BE RELEVANT TO YOUR INTENDED USE OF THESE DESIGNS.

2. THE INVENTRA IPX PACKAGE

2.1. SYSTEM REQUIREMENTS

To use the cores from this Inventra IPX collection in the Altera flow, you need: Mentor Graphics Exemplars LeonardoSpectrum Synthesis tool (Version 2001.1b (any level) or higher) Mentor Graphics Model Technologys ModelSim Simulator from (Version 5.5c or higher) Alteras Quartus II Place & Route software (Version 1.1 or higher) All running on either a PC running Windows 98, Windows 2000 or Windows NT or on a UNIX workstation running Solaris 2.6/7/8 or HP 10.2/11.0

2.2. PACKAGE CONTENTS

Inventra IPX is delivered either on a CD or by download from the Web. The CD contains: A copy of the License Agreement as a simple text file. It is important to read this License Agreement before you start to use Inventra IPX. Three executables: one for Windows, one for Solaris, and one for HP. A top-level readme which explains how to install Inventra IPX. This Release Note. A copy of Adobe Acrobat to ensure that you can read the documents associated with the Inventra IPX cores which are all supplied either as simple text files or as Adobe Acrobat PDF files. When Inventra IPX is downloaded from the Web, you download a copy of the executable appropriate to the system on which you wish to install and use Inventra IPX.

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RELEASE NOTE

When the selected executable is run, a set of files is placed on your disk with the outline directory structure shown below:
ipx_v x_ xxx

m1284h

m16550a

m16x50

. . .

m8490

mi2c

mpcmcia1

docs

verilog

vhdl

docs

Within the top level Inventra IPX directory will be a set of core directories, one for each core in the Inventra IPX collection, plus a docs directory. The docs directory contains general documents concerning Inventra IPX including the Inventra IPX User Guide and this Release Note. The files for each IPX core are provided in a directory named after the core, and are principally divided into a Verilog set and a VHDL set as shown in the diagram below.
IPX_core

verilog

vhdl

docs

rtl_encrypted

rtl_sim

synth

gate_sim

template

rtl_encrypted

rtl_sim

synth

gate_sim

template

work

quartus

work

work

quartus

work

The rtl_encrypted directories contain the encrypted source code. The rtl_sim directories each contain a ModelSim compiled library of the testbench and the core, compiled into a work library. The rtl_sim directories also contain scripts and associated files for simulating the IPX core using ModelSim. The gate_sim directories each contain a ModelSim compiled library of the testbench, compiled into a work library. The gate_sim directories also contain scripts and associated files for simulating the gate-level netlist using ModelSim. The synth directories contain scripts for synthesizing the core using LeonardoSpectrum, initially set up with the Altera APEX EP20K400EFC672 as the target device. The synth/quartus directories contain scripts for running place and route using Quartus II (again, initially set up with same APEX device as the target device). The template directories contain template and symbol files for the IPX core. The docs directory contains documentation specific to the core including its Product Specification.

Version-specific information about the core and details of the files supplied are given in the <IPX_core>.readme file in the top-level <IPX_core> directory and in other readmes located at different points in the directory structure.

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2.3. USER GUIDE

The Inventra IPX User Guide is aimed at helping you to evaluate the cores in the Inventra IPX package, verify that they function as required, synthesize and test them with the aid of the various supporting files provided alongside each design. It explains how to license Inventra IPX. It also outlines the actions involved in incorporating one or more of the IPX cores in a FPGA/PLD design and provides answers to a range of frequently asked questions. The current release includes Issue 2 of the Inventra IPX User Guide. The guide is supplied in the top-level docs directory as the Adobe Acrobat (.pdf) file ipx_v1_100_pu.pdf i.e. in the same form as this Release Note. It can therefore be viewed using Adobe Acrobat Reader (see below).

2.4. CORE SPECIFICATIONS

Provided with each IPX core is a Product Specification detailing the functionality of the design. The information given includes lists of signals, register information, timing diagrams and details of the structure of the RTL design. The Product Specification is provided in the <IPX_core>/docs directory as the Adobe Acrobat file <design>_ ps.pdf i.e. in the same form as this Release Note. It can therefore be viewed using Adobe Acrobat Reader (see below).

2 . 5 . C O R E D ATA S H E E T S

Included in each <IPX_core>/docs directory is a two-page Product Datasheet giving an overview of the core. This Product Datasheet is provided as the Adobe Acrobat (PDF) file <IPX_core>_ pd.pdf Release Note. It can therefore be viewed using Adobe Acrobat Reader (see below). i.e. in the same form as this

2.6. ADOBE ACROBAT READER SOFTWARE (CD ONLY)

Where provided on CD, this release includes a copy of the Adobe Acrobat Reader software for use in reading and printing the documents supplied in the Inventra IPX package as Adobe Acrobat Portable Document Format (.pdf) files. The Reader software is located in the /acrobat directory. Windows, Solaris and HP-UX versions are supplied. Installation instructions and instructions for its use are given in the instguid.txt file in the /acrobat directory. Please install and use this software in accordance with the Adobe Acrobat installation and license instructions, and contact Adobe Technical Support if you have any technical queries.

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RELEASE NOTE

3. THE CORES OFFERED IN THE CURRENT RELEASE

3.1. CORE LIST

The cores included in the V1.100 release of the Inventra IX collection are: Design M1284H M16550A M16x50 M8051 M82365SL M8237A M8255 M8490 MI2C Description IEEE 1284 Host Parallel Port UART with FIFOs Enhanced UART with FIFOs and IrDA support 8-Bit Microcontroller PC Host Interface 4-Channel DMA Controller Parallel Peripheral Interface 5380-compatible SCSI Interface I2C Bus Interface Fileset name m1284h m16550a m16x50 m8051 m82365sl m8237a m8255 m8490 mi2c mpcmcia1 Core Version v01.3p1 v08.800 v01.500 v06.700 v01.100 v06.000 v05.001 v02.100 v05.3p1 v01.003 Core Specification m1284h_ps.pdf m16550a_ps.pdf m16x50_ps.pdf m8051_ps.pdf m82365sl_ps.pdf m8237a_ps.pdf m8255_ps.pdf m8490_ps.pdf mi2c_ps.pdf mpcmcia1_ps.pdf Core Datasheet m1284h_pd.pdf m16550a_pd.pdf m16x50_pd.pdf m8051_pd.pdf m82365sl_pd.pdf m8237a_pd.pdf m8255_pd.pdf m8490_pd.pdf mi2c_pd.pdf mpcmcia1_pd.pdf

MPCMCIA1 PC Card Interface

3.2. CORE INFORMATION

The following sections give detailed information about the cores included in the current release of Inventra IPX.

3.2.1. M1284H

The M1284H is a host-based multi-function parallel port that may be used to transfer data between a host PC and a peripheral such as a printer. It is designed to attach to the PCs ISA bus on one side and to the parallel port connector on the other and it can be software-configured to operate in five modes, corresponding to the IEEE Standard 1284 parallel interface protocol standards. The version of the core included in this release of the Inventra IPX collection is v01.3p1. Please Note: 1. 2. 3. There are four testbenches for the M1284H, which are run one after another by the m1284h_tb.bat/.scr scripts. The testbenches for the M1284H are self-checking. No reference listing is therefore provided. Depending on the timing constraints used, it is possible that the output PINTR1 will produce the correct output after it is sampled in the testbench. This will result in testbench errors. As this signal is used to raise an interrupt on the cpu, its exact timing is not critical.

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3.2.2.

M16550A

The M16550A is a high-performance universal asynchronous receiver/transmitter (UART) with two 16-bit FIFOs one for transmit and one for receive. It also includes a 16-bit programmable baud rate generator and an 8-bit scratch register, eight modem control lines and two DMA handshake lines which are used to indicate when the FIFOs are ready to transfer data to the CPU. The M16550A is fully programmable through its 8-bit CPU interface. It supports word lengths from five to eight bits, an optional parity bit and one or two stop bits. If enabled, the parity can be odd, even or forced to a defined state. Interrupts can be generated for a range of TX Buffer/FIFO, RX Buffer/FIFO, Modem Status and Line Status conditions. The version of the core included in this release of the Inventra IPX collection is v08.800. Please Note: 1. 2. Bits 3, 6 and 7 of the FIFO Control Register cannot be written unless bit 0 is being written to 1. Differences may be found between the listing files generated when the core is simulated and the supplied reference listing, especially near the beginning of a gate-level simulation. Further details are given in the m16550a/.../gate_sim.readme file.

3.2.3.

M16X50

The M16x50 is an extension of the M16550A, with enhancements that emulate features found in similar discrete devices with a range of part numbers. These enhancements include: PVCI-compatible CPU interface; Hardware Flow Control; Software Flow Control; IrDA Modulation/Demodulation; Transmit FIFO Threshold; CTS Interrupt; RTS Interrupt. The RTL version of the design can also be configured for different FIFO depths. (In the IPX version, the FIFOs are fixed at 16 bytes). The version of the core included in this release of the Inventra IPX collection is v01.500. Please Note: 1. 2. The THRE bit is set to 1 whenever the TXFIFO is empty and it is cleared when at least one byte is written to the TXFIFO not as described in the Product Specification. Differences may be found between the listing files generated when the core is simulated and the supplied reference listing, especially near the beginning of a gate-level simulation. Further details are given in the m16x50/.../gate_sim.readme file.

3.2.4.

M8051

The M8051 is a high performance 8-bit microcontroller. This microcode-free design is software compatible (including instruction execution times) with industry standard discrete devices, having all their core features, and the additional features corresponding to the Intel 8051/8031/ 80C51BH/80C31BH/87C51 parts except that ONCE mode and Program Lock are not supported. The version of the core included in this release of the Inventra IPX collection is v06.700. Please Note: 1. The Timer 0 and Timer 1 INT0 & INT1 inputs are not sampled by S_EN. This can cause a discrepancy in behavior between the M8051 and the real part when these inputs are used as enables to the counters.

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2. 3.

RELEASE NOTE

RAM models need to be initialized before any simulations requiring RAM reads/writes are conducted, otherwise X values may be input on the AI bus causing RTL and gate-level simulations to fail. Differences may be found between the listing files generated when the core is simulated and the supplied reference listing, especially near the beginning of a gate-level simulation. Further details are given in the m8051/.../gate_sim.readme file.

3.2.5.

M82365SL

The M82365SL provides an industry standard solution to the problem of interfacing one or more PC Card sockets to a Notebook PC that uses an external ISA bus (8 or 16-bit). Each M82365SL supports two PCMCIA 2.0/2.1/ JEIDA 4.1 68-pin standard PC Card sockets, but up to eight PC Card sockets can be supported by using a cascade of up to four M82356SLs. Each socket can be independently configured to support either memory or I/O cards. Memory and I/O windowing facilities are provided between the ISA bus and the PC Cards. The support for the two sockets is clearly divided into two areas in the design, allowing the M82365SL to be readily adapted to a single socket system if required. The M82365SL is software compatible with the Intel 82365SL. The version of the core included in this release of the Inventra IPX collection is v01.100. Please Note: 1. The description of Interrupt Steering in the Product Specification (Sections 2.4 and 2.7.4) does not fully reflect the functionality of the core. The core does not support NIREQ (the RDY/NBSY pin in I/O card mode) via the NINTR output. NINTR only handles interrupts from Card Status Change sources, which include NGPI input, Card Detect inputs CD1 and CD2. In Memory Card Mode, Battery status inputs and the RDY/NBSY input can also interrupt via NINTR. In I/O card mode, the RDY/NBSY input is steered to one of the IRQxx System Interrupt outputs, and the interrupt acknowledge is sent to the PC Card, not to the core. When the design is synthesized, messages such as Info, DLATCH ### implemented using combinational logic and Warning : Design contains combinatorial loop through net ### may appear. These are due to the target technology not having latches and hence the latches having to be implemented in logic. The messages can be ignored. The synthesis has been directed to ensure that the latch is implemented in a single LUT to avoid any timing problems. Differences may be found between the listing files generated when the core is simulated and the supplied reference listing, especially near the beginning of a gate-level simulation. Further details are given in the m82365sl/.../gate_sim.readme file.

2.

3.

3.2.6.

M8237A

The M8237A is a fully-programmable four-channel Direct Memory Access controller. Each channel has a 64K address range which can be incremented or decremented and can handle word counts up to 64K. The channels can be individually programmed to autoinitialize at the end of each transfer, and a priority resolver can be programmed to provide fixed or rotating priority as required. The inclusion of a temporary register allows memory to memory transfers to be made automatically. Multiple M8237As can be cascaded if more than four channels are required. The version of the core included in this release of the Inventra IPX collection is v06.000. Please Note: 1. When the design is synthesized, messages such as Info, DLATCH ### implemented using combinational logic and Warning : Design contains combinatorial loop through net ### may appear. These are due to the target technology not having latches and hence the latches having to be implemented in logic. The messages can be ignored. The synthesis has been directed to ensure that the latch is implemented in a single LUT to avoid any timing problems.

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3.2.7.

M8255

The M8255 is a programmable peripheral interface. It has three 8-bit ports which can be programmed as inputs or outputs through its 8-bit CPU interface. The inputs and outputs can be read or written directly, or they can be strobed by external signals providing handshaking and interrupt signals. The version of the core included in this release of the Inventra IPX collection is v05.001. Please Note: 1. When the design is synthesized, messages such as Info, DLATCH ### implemented using combinational logic and Warning : Design contains combinatorial loop through net ### may appear. These are due to the target technology not having latches and hence the latches having to be implemented in logic. The messages can be ignored. The synthesis has been directed to ensure that the latch is implemented in a single LUT to avoid any timing problems.

3.2.8.

M8490

The M8490 is a Small Computer Systems Interface (SCSI) controller, able to control 8-bit asynchronous communication over an ANSI SCSI-II bus. It has an 8-bit CPU interface through which the local processor can program it to act as initiator or target on the SCSI bus, and can control all phases of data transfer by writing to command registers within the M8490. Data can be transferred to and from the M8490 either through the CPU interface or by DMA, with the M8490 itself driving the arbitration phase of the transfer. Applications currently using an NSC DP8490, an NCR 5380 or an NCR 5380-compatible controller should be able to use the M8490 without software change. The version of the core included in this release of the Inventra IPX collection is v02.100. Please Note: 1. The testbench for the M8490 is self-checking. No reference listing is therefore provided.

3.2.9.

MI2C

The MI2C provides an interface between a microprocessor and an I2C bus. It can be programmed to operate as either a master or a slave device and performs arbitration in master mode to allow it to operate in multi-master systems. In slave mode, it can interrupt the processor when it recognizes its own 7-bit or 10-bit address or the general call address. The MI2C can be used in any applications which use I2C bus devices. These are primarily in the consumer and telecoms market segments. The I2C bus is also used as a board level communications protocol. The version of the core included in this release of the Inventra IPX collection is v05.3p1. Please Note: 1. The testbench for the MI2C is self-checking. No reference listing is therefore provided.

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3.2.10. MPCMCIA1

RELEASE NOTE

The MPCMCIA1 is a general purpose 16-bit PC Card Interface block for use in PCMCIA card designs. It provides 16-bit PCMCIA card, memory and I/O interfaces with user configurable I/O address decoding, level or edge triggered interrupts and power-down control. The MPCMCIA1 supports accesses to attribute memory, common memory and I/O. DMA accesses, however, are not supported. The version of the core included in this release of the Inventra IPX collection is v01.003. Please Note: 1. 2. 3. The I/O addr limit fails for a non-zero base address in the Verilog version of the design. (The VHDL version is not affected). The range of output DO should be [15:0], not [7:0] as shown in the diagram on page 8 of the Product Specification. When the design is synthesized, messages such as Info, DLATCH ### implemented using combinational logic and Warning : Design contains combinatorial loop through net ### may appear. These are due to the target technology not having latches and hence the latches having to be implemented in logic. The messages can be ignored. The synthesis has been directed to ensure that the latch is implemented in a single LUT to avoid any timing problems.

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4. REVISION HISTORY
4.1. ISSUE 1.100

4th December 2001. Describes Version 1.100 of the Inventra IPX collection.

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RELEASE NOTE

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2001 Mentor Graphics Corporation, All Rights Reserved. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation. Altera and Quartus are registered trademarks of Altera Corporation. Inventra, Inventra IPX and LeonardoSpectrum are trademarks of Mentor Graphics Corporation. APEX and FLEX are trademarks of Altera Corporation. All other trademarks are the property of their respective owners.

http://www.mentor.com/inventra
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