You are on page 1of 61

n chuyn ngnh

GVHD : Nguyn Trng Khanh

TRNG CAO NG K THUT CAO THNG


KHOA: IN T _ TIN HC
LP: CT06

Lun v n

GVHD: NGUYN TRNG KHANH


SVTH: L NGUYN H

Trang 1

n chuyn ngnh

GVHD : Nguyn Trng Khanh

LI CM N
Trc tin em xin chn thnh cm n ton th thy c trng Cao ng K
Thut Cao Thng , nhng ngi to iu kin cho em c c hi nghin cu v tm
hiu su rng v lnh vc in t, c bit l thy Nguyn Trng Khanh tn tnh hng
dn v gip chng em trong thi gian thc hin ti. ng thi chng em cng gi li
cm n ti gia nh v bn b gip em trong thi gian qua. C c s gip nhit
tnh cng vi s c gng ca bn thn nn em hn thnh c ti ng thi hn.
Vi s hiu bit cn hn ch v thi gian thc hin ti khng nhiu nn ti khng
trnh khi nhng sai st. Rt cm n s hng dn v gp ca qu thy c v bn b cho
ti c hon chnh hn.
Em xin chn thnh cm n!

Sinh vin thc hin


L Nguyn H

Trang 2

n chuyn ngnh

GVHD : Nguyn Trng Khanh

NHN XT CA GIO VIN

.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................

Tp H Ch Minh, ngy thng nm 2009


Gio vin hng dn
K tn

Thy Gio Nguyn Trng Khanh

Trang 3

n chuyn ngnh

GVHD : Nguyn Trng Khanh

NHN XT CA GIO VIN PHN BIN

.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................
.............................................................................................................................................................................

Tp HCM, ngy thng nm 2009


Gio vin phn bin

Trang 4

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Trang 5

n chuyn ngnh

GVHD : Nguyn Trng Khanh

I. GII THIU V VI IU KHIN PIC 16F877A


1.1. Gii thiu chung
1.1.1 Tng quan v h Vi iu khin PIC
PIC l mt h vi iu khin RISC c sn xut bi cng ty Microchip
Technology. Dng PIC u tin l PIC1650 c pht trin bi Microelectronics Division
thuc General_Instrument. PIC bt ngun t ch vit tt ca Programmable Intelligent
Computer (My tnh kh trnh thng minh) l mt sn phm ca hng General Instruments
t cho dng sn phm u tin ca h l PIC1650. Lc ny, PIC 1650 c dng giao
tip vi cc thit b ngoi vi cho my ch 16 bit CP1600, v vy, ngi ta cng gi PIC
vi tn Peripheral Interface Controller (B iu khin giao tip ngoi vi). CP1600 l
mt CPU tt, nhng li km v cc hot ng xut nhp, v v vy PIC 8-bit c pht
trin vo khong nm 1975 h tr hot ng xut nhp cho CP1600. PIC s dng
microcode n gin t trong ROM, v mc d, cm t RISC cha c s dng thi
by gi, nhng PIC thc s l mt vi iu khin vi kin trc RISC, chy mt lnh mt
chu k my (4 chu k ca b dao ng). Nm 1985 General Instruments bn b phn vi
in t ca h, v ch s hu mi hy b hu ht cc d n lc qu li thi. Tuy
nhin, PIC c b sung EPROM to thnh 1 b iu khin vo ra kh trnh. Ngy nay
rt nhiu dng PIC c xut xng vi hng lot cc module ngoi vi tch hp sn (nh
USART, PWM, ADC), vi b nh chng trnh t 512 Word n 32K Word.
1.1.2. Mt s c tnh ca Vi iu khin PIC
Hin nay c kh nhiu dng PIC v c rt nhiu khc bit v phn cng, nhng chng ta
c th im qua mt vi nt nh sau :
8/16 bit CPU, xy dng theo kin truc Harvard c sa i
Flash v ROM c th tu chn t 256 byte n 256 Kbyte
Cc cng Xut/ Nhp (I/ O ports) (mc logic thng t 0V n 5.5V, ng vi
logic 0 v logic 1)
8/16 bit Timer
Cc chun giao tip ni tip ng b/ khung ng b USART
B chuyn i ADC Analog-to-digital converters, 10/12 bit
B so snh in p (Voltage Comparator)
Cc module Capture/ Compare/ PWM
LCD
MSSP Peripheral dng cho cc giao tip I2 C, SPI, I2 S
B nh ni EPROM c th ghi/ x ln ti 1 triu ln
Module iu khin ng c, c encoder
H tr giao tip USB
Trang 6

n chuyn ngnh

GVHD : Nguyn Trng Khanh

H tr giao tip CAN


H tr giao tip LIN
H tr giao tip IrDA
Mt s dng c tch hp b RF (PIC16f639, v rfPIC)
KEELOQ m h v gii m
DSP nhng tnh nng x l tn hiu s (dsPIC)
c im thc thi tc cao ca RISC CPU ca h vi diu khin PIC16F87XA :
Ch gm 35 lnh n.
Tt c cc lnh l 1chu k ngoi tr chng trnh con l 2 chu k.
Tc hot ng :
*DC- 20MHz ng vo xung clock.
*DC- 200ns chu k lnh.
rng ca b nh chng trnh Flash l 8K x 14word, ca b nh d liu (RAM)
l 368 x 8bytes, ca b nh d liu l EPROM (RAM) l 256 x 8bytes.
1.1.3. Nhng c tnh ngoi vi
- Timer0 : 8- bit nh thi/ m vi 8- bit prescaler
- Timer1 : 16- bit nh thi/ m vi prescaler, c th c tng ln trong sut ch
Sleep qua thch anh/ xung clock bn ngi.
- Timer2 : 8- bit nh thi/m vi 8- bit, prescaler v postscaler
- Hai module Capture, Compare, PWM
* Capture c rng 16 bit, phn gii 12.5ns
* Compare c rng 16 bit, phn gii 200ns
* phn gii ln nht ca PWM l 10bit.
- C 13 ng I/O c th iu khin trc tip
- Dng vo v dng ra ln :
* 25mA dng vo cho mi chn
* 20mA dng ra cho mi chn
1.1.4. c im v tng t
- 10 bit, vi 8 knh ca b chuyn i tng t sang s (A/D).
- Brown out Reset (BOR).
- Module so snh v tng t.
* Hai b so snh tng t.
* Module in p chun VREF c th lp trnh trn PIC.
- C th lp trnh ng ra vo n t nhng ng vo ca PIC v trn in p bn trong.
- Nhng ng ra ca b so snh c th s dng cho bn ngi.
1.1.5. Cc c im c bit :
- C th ghi/ xo 100.000 ln vi kiu b nh chng trnh Enhanced Flash.
Trang 7

n chuyn ngnh

GVHD : Nguyn Trng Khanh

- 1.000.000 ghi/ x vi kiu b nh EPROM.


- EPROM c th lu tr d liu hn 40 nm.
- C th t lp trnh li di s iu khin ca phn mm.
- Mch lp trnh ni tip qua 2 chn.
- Ngun n 5V cp cho mch lp trnh ni tip.
- Watchdog Timer (WDT) vi b dao ng RC tch hp sn trn Chip cho hot
ng ng tin cy.
- C th lp trnh m bo v.
- Tit kim nng lng vi ch Sleep.
- C th la chn b dao ng.
- Mch d sai (ICD : In- Circuit Debug) qua 2 chn
1.1.6. Cng ngh CMOS
Nng lng thp, tc cao Flash/ cng ngh EPROM
Vic thit k hn tn tnh
Khong in p hot ng t 2V n 5.5V
Tiu tn nng lng thp.

1.2. Gii thiu v PIC16F8XX v PIC16F877A


PIC16F8X l nhm PIC trong h PIC16XX ca h Vi iu khin 8-bit, tiu hao
nng lng thp, p ng nhanh, ch to theo cng ngh CMOS, chng tnh in tuyt
i. Nhm bao gm cc thit b sau:
PIC16F83
PIC16CR83
PIC16F84
PIC16CR84
- Tt c cc PIC16/17 u c cu trc RISC. PIC16CXX cc c tnh ni bc, 8
mc ngn xp Stack, nhiu ngun ngt tch hp bn trong ln ngoi. C cu trc
Havard vi cc bus d liu v bus thc thi chng trnh ring bit nhau cho php
di 1 lnh l 14-bit v bus d liu 8-bit cch bit nhau. Tt c cc lnh u mt 1
chu k lnh ngoi tr cc lnh r nhnh chng trnh mt 2 chu k lnh. Ch c 35
lnh v 1 lng ln cc thanh ghi cho php p ng cao trong ng dng.
- H PIC16F8X c nhiu tnh nng c bit lm gim thiu cc thit b ngoi vi, v
vy kinh t cao, c h thng ni bt ng tin cy v s tiu th nng lng thp.
y c 4 s la chn b dao dng v ch c 1 chn kt ni b dao ng RC nn c
gii php tit kim cao. Ch SLEEP tit kim ngun v c th c nh thc
bi cc ngun reset. V cn nhiu phn khc c gii thiu bn trn s c
ni r cc phn k tip.
- PIC16F877A c 40/44 chn vi s phn chia cu trc nh sau :
+ C 5 port xut/nhp
+ C 8 knh chuyn i A/D 10-bit
+ C b nh gp i so vi PIC16F873A v PIC16F874A2.2.1. T chc thanh ghi

Trang 8

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Bng 1.1: Tm tt c im ca PIC16F877A


Tn s hot ng
Reset v Delay
B nh chng trnh Flash
(14-bit word)
B nh d liu (byte)
B nh d liu EEPROM (byte)
Cc ngt
Cc Port xut/nhp

DC-20MHz
POR, BOR (PWRT, OST)
8K

Timer

Module Capture/Compare/PWM
Giao tip ni tip
Giao tip song song
Module A/D 10-bit
B so snh tng t
Tp lnh

2
MSSP, USART
PSP
8 knh ng vo
2
35 lnh

S chn

40 chn PDIP
44 chn PLCC
44 chn TQFP
44 chn QFN

368
256
15
Port A, B, C, D, E

1.3. S chn ,cu trc v chc nng PIC 16F877A loi 40 chn PDIP

Hnh 1.1: S chn Pic 16F877A loi 40 chn PDIP


Chc nng cc chn :
* Chn OSC1/CLKI (13) : ng vo dao ng thch anh hoc xung clock bn ngi.
- OSC1 : ng vo dao ng thch anh hoc xung clock bn ngoi. Ng vo Schmit
trigger khi c cu to ch RC ; mt cch khc ca CMOS.

Trang 9

n chuyn ngnh

GVHD : Nguyn Trng Khanh

- CLKI : ng vo ngun xung bn ngi. Lun c kt hp vi chc nng OSC1.


* Chn OSC2/CLKO (13) : ng vo dao ng thch anh hoc xung clock
- OSC2 : Ng ra dao ng thch anh. Kt ni n thch anh hoc b cng
hng.
- CLKO : ch RC, ng ra ca OSC2, bng tn s ca OSC1 v ch ra tc
ca chu k lnh.
* Chn

/VPP (1) :

- MCLR : Hot ng Reset mc thp


- VPP : ng vo p lp trnh
* Chn RA0/AN0 (2) :
- RA0 : xut/nhp s
- AN0 : ng vo tng t 0
* Chn RA1/NA1 (3) :
- RA1 : xut/nhp s
- AN1 : ng vo tng t 1
* Chn RA2/NA2/VREF-/CVREF (4) :
- RA2 : xut/nhp s
- AN2 : ng vo tng t 2
- VREF -: ng vo in p chun (thp) ca b A/D
- CVREF: in p tham chiu VREF ng ra b so snh
* Chn RA3/NA3/VREF+ (5) :
- RA3 : xut/nhp s
- AN3 : ng vo tng t 3
- VREF+ : ng vo in p chun (cao) ca b A/D
* Chn RA4/TOCKI/C1OUT (6) :
- RA4 : xut/nhp s - m khi c cu to nh ng ra
- TOCKI : ng vo xung clock bn ngi cho Timer 0
- C1 OUT : Ng ra b so snh 1
* Chn RA5/AN4/

/C2OUT (7) :

- RA5 : xut/nhp s
- AN4 : ng vo tng t 4
- SS : ng vo chn la SPI ph
- C2 OUT : ng ra b so snh 2
* RB0/INT (33) :
- RB0 : xut/nhp s
Trang 10

n chuyn ngnh

GVHD : Nguyn Trng Khanh

- INT : ngt ngi


* RB1 (34) : xut/nhp s
* RB2 (35) : xut/nhp s
* RB3/PGC :
- RB3 : xut/nhp s
- Chn cho php lp trnh in p thp ICPS
* RB4 (37), RB5 (38) : xut/nhp s
* RB6/PGC (39) :
- RB6 : xut/nhp s
- PGC : mch d sai v xung clock lp trnh ICSP
* RB7/PGD (40) :
- RB7 : xut/nhp s
- PGD : mch d sai v d liu lp trnh ICSP
* Chn RC0/T1 OCO/T1CKI (15) :
- RC0 : xut/nhp s
- T1 OCO : ng vo b dao ng Timer 1
- T1 CKI : ng vo xung clock bn ngi Timer 1
* Chn RC1/T1 OSI/CCP2 (16) :
- RC1 : xut/nhp s
- T1 OSI : ng vo b dao ng Timer 1
- CCP2 : ng vo Capture 2, ng ra compare 2, ng ra PWM2
* Chn RC2/CCP1 (17) :
- RC2 : xut/nhp s
- CCP1 : ng vo Capture 1, ng ra compare 1, ng ra PWM1
* Chn RC3/SCK/SCL (18):
- RC3 : xut/nhp s
- SCK : ng vo xung clock ni tip ng b/ng ra ca ch SPI
- SCL : ng vo xung clock ni tip ng b/ ng ra ca ch I2C
* Chn RC4/SDI/SDA (23) :
- RC4 : xut/nhp s
- SDI : d liu vo SPI
- SDA : xut/nhp d liu vo I2C
* Chn RC5/SDO (24) :
- RC5 : xut/nhp s
- SDO : d liu ra SPI
Trang 11

n chuyn ngnh

GVHD : Nguyn Trng Khanh

* Chn RC6/TX/CK (25) :


- RC6 : xut/nhp s
- TX : truyn bt ng b USART
- CK : xung ng b USART
* Chn RC7/RX/DT (26) :
- RC7 : xut/nhp s
- RX : nhn bt ng USART
- DT : d liu ng b USART
* Chn RD0/PSP0 (19) :
- RD0 : xut/nhp s
- PSP0 : d liu port nhnh song song
* Chn RD1/PSP1 (20) :
- RD1 : xut/nhp s
- PSP1 : d liu port nhnh song song
* Cc chn RD2/PSP2 (21), RD3/PSP3 (22), RD4/PSP (27), RD5/PSP5 (28),
RD6/PSP6 (29), RD7/PSP7 (30) tng t chn 19,20.
* Chn RE0/

/AN6 (8) :

- RE0 : xut nhp s


- RD : iu khin vic c port nhnh song song
- AN5 : ng vo tng t 5
* Chn RE1/

/AN6 (9) :

- RE1 : xut/nhp s
- WR : iu khin vic ghi port nhnh song song
- AN6 : ng vo tng t 6
* Chn RE2/

/AN7 (10) :

- RE2 : xut/nhp s
- CS : Chip la chn s iu khin port nhnh song song
- AN7 : ng vo tng t 7
* Chn VDD(11,32), v VSS(12,31) : l cc chn ngun ca PIC.

Cu trc bn trong pic 16f877a:

Trang 12

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Trang 13

n chuyn ngnh

GVHD : Nguyn Trng Khanh

2 MT VI THNG S V VI IU KHIN PIC16F877A


y l vi iu khin thuc h PIC16Fxxx vi tp lnh gm 35 lnh c di
14 bit. Mi lnh u c thc thi trong mt chu k xung clock. Tc hot ng ti a cho
php l 20 MHz vi mt chu k lnh l 200ns. B nh chng trnh 8Kx14 bit, b nh d liu
368x8
byte RAM v b nh d liu EEPROM vi dung lng 256x8 byte. S PORT I/O l 5 vi 33
pin I/O.
Cc c tnh ngoi vi bao gmcc khi chc nng sau:
Trang 14

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Timer0: b m 8 bit vi b chia tn s 8 bit.


Timer1: b m 16 bit vi b chia tn s, c th thc hin chc nng m da vo
xung clock ngoi vi ngay khi vi iu khin hot ng ch sleep.
Timer2: b m 8 bit vi b chia tn s, b postcaler.
Hai b Capture/so snh/iu ch rng xung.
Cc chun giao tip ni tip SSP (Synchronous Serial Port), SPI v I2C.
Chun giao tip ni tip USART vi 9 bit a ch.
Cng giao tip song song PSP (Parallel Slave Port) vi cc chn iu khin RD,
WR,
CS bn ngoi.
Cc c tnh Analog:
8 knh chuyn i ADC 10 bit.
Hai b so snh.
Bn cnh l mt vi c tnh khc ca vi iu khin nh:
B nh flash vi kh nng ghi xa c 100.000 ln.
B nh EEPROM vi kh nng ghi xa c 1.000.000 ln.
D liu b nh EEPROM c th lu tr trn 40 nm.
Kh nng t np chng trnh vi s iu khin ca phn mm. Np c chng
trnh ngay trn mch in ICSP (In Circuit Serial Programming) thng qua 2 chn.
Watchdog Timer vi b dao ng trong.
Chc nng bo mt m chng trnh.
Ch Sleep.
C th hot ng vi nhiu dng Oscillator khc nhau.
3 S KHI VI IU KHIN PIC16F877A

Trang 15

n chuyn ngnh

GVHD : Nguyn Trng Khanh

4 T CHC B NH
Cu trc b nh ca vi iu khin PIC16F877A bao gm b nh chng trnh (Program
memory) v b nh d liu (Data Memory).
5 B NH CHNG TRNH
B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b
nh 8K word (1 word = 14 bit) v c phn thnh nhiu trang (t page0 n page 3) .
Nh vy b nh chng trnh c kh nng cha c 8*1024 = 8192 lnh (v mt lnh
sau khi m ha s c dung lng 1 word (14 bit).
m ha c a ch ca 8K word b nh chng trnh, b m chng trnh c dung
lng 13 bit (PC<12:0>).
1. Khi vi iu khin c reset,
b m chng trnh s ch n a ch 0000h (Reset vector). Khi c ngt xy ra,
b m chng trnh s ch n a ch 0004h (Interrupt vector).

Trang 16

n chuyn ngnh

GVHD : Nguyn Trng Khanh

B nh chng trnh khng bao gm:


B nh stack v khng c a ch ha bi b m chng trnh. B nh stack s
c cp c th trong phn sau.
6 B NH D LIU
B nh d liu ca PIC l b nh EEPROM c chia ra lm nhiu bank. i
vi PIC16F877A b nh d liu c chia ra lm 4 bank. Mi bank c dung lng 128 byte,
bao gm cc thanh ghi c chc nng c bit SFG (Special Function Register) nm cc
vng a ch thp v cc thanh ghi mc ch chung GPR (General Purpose Register) nm
vng a ch cn li trong bank. Cc thanh ghi SFR thng xuyn c s dng (v d nh
thanh ghi STATUS) s c t tt c cc bank ca b nh d liu gip thun tin trong
qu trnh truy xut v lm gim bt lnh ca chng trnh. S c th ca b nh d liu
PIC16F877A nh sau:

Trang 17

n chuyn ngnh

GVHD : Nguyn Trng Khanh

6.1 THANH GHI CHC NNG C BIT SFR


y l cc thanh ghi c s dng bi CPU hoc c dng thit lp v iu khin
cc khi chc nng c tch hp bn trong vi iu khin. C th phn thanh ghi SFR lm hai
lai: thanh ghi SFR lin quan n cc chc nng bn trong (CPU) v thanh ghi SRF dng
Trang 18

n chuyn ngnh

GVHD : Nguyn Trng Khanh

thit lp v iu khin cc khi chc nng bn ngoi (v d nh ADC, PWM, ). Phn ny


s cp n cc thanh ghi lin quan n cc chc nng bn trong. Cc thanh ghi dng
thit lp v iu khin cc khi chc nng s c nhc n khi ta cp n cc khi chc
nng .
Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha kt qu thc hin php ton
ca khi ALU, trng thi reset v cc bit chn bank cn truy xut trong b nh d liu. Thanh
ghi OPTION_REG (81h, 181h): thanh ghi ny cho php c v ghi, cho php iu khin chc
nng pull-up ca cc chn trong PORTB, xc lp cc tham s v xung tc ng, cnh tc
ng ca ngt ngoi vi v b m Timer0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho php c v ghi, cha cc
bit iu khin v cc bit c hiu khi timer0 b trn, ngt ngoi vi RB0/INT v ngt interrputon-change ti cc chn ca PORTB.

Thanh ghi PIE1 (8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi chc nng
ngoi vi.

Thanh ghi PIR1 (0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt ny
c cho php bi cc bit iu khin cha trong thanh ghi PIE1.

Thanh ghi PIE2 (8Dh): cha cc bit iu khin cc ngt ca cc khi chc nng
CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM.

Trang 19

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Thanh ghi PIR2 (0Dh): cha cc c ngt ca cc khi chc nng ngoi vi, cc ngt
ny c cho php bi cc bit iu khin cha trong thanh ghi PIE2.

Thanh ghi PCON (8Eh): cha cc c hiu cho bit trng thi cc ch reset ca vi
iu khin.

6.2 THANH GHI MC CH CHUNG GPR


Cc thanh ghi ny c th c truy xut trc tip hoc gin tip thng qua thanh ghi
FSG (File Select Register). y l cc thanh ghi d liu thng thng, ngi s dng c th
ty theo mc ch chng trnh m c th dng cc thanh ghi ny cha cc bin s, hng
s, kt qu hoc cc tham s phc v cho chng trnh.
7 STACK
Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng nh
c bit khng cho php c hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xy ra
lm chng trnh b r nhnh, gi tr ca b m chng trnh PC t ng c vi iu khin
ct vo trong stack. Khi mt trong cc lnh RETURN, RETLW hat RETFIE c thc thi,
gi tr PC s t ng c ly ra t trong stack, vi iu khin s thc hin tip chng trnh
theo ng qui trnh nh trc.
B nh Stack trong vi iu khin PIC h 16F87xA c kh nng cha c 8 a ch v hot
ng theo c ch xoay vng. Ngha l gi tr ct vo b nh Stack ln th 9 s ghi ln gi
tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th 10 s ghi ln gi tri6
ct vo Stack ln th 2.
Cn ch l khng c c hiu no cho bit trng thi stack, do ta khng bit c
khi no stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng c lnh POP
hay PUSH, cc thao tc vi b nh stack s hon ton c iu khin bi CPU.
8 CC CNG XUT NHP CA PIC16F877A

Trang 20

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Cng xut nhp (I/O port) chnh l phng tin m vi iu khin dng tng tc
vi th gii bn ngoi. S tng tc ny rt a dng v thng qua qu trnh tng tc ,
chc nng ca vi iu khin c th hin mt cch r rng.
Mt cng xut nhp ca vi iu khin bao gm nhiu chn (I/O pin), ty theo cch b
tr v chc nng ca vi iu khin m s lng cng xut nhp v s lng chn trong mi
cng c th khc nhau. Bn cnh , do vi iu khin c tch hp sn bn trong cc c
tnh giao tip ngoi vi nn bn cnh chc nng l cng xut nhp thng thng, mt s chn
xut nhp cn c thm cc chc nng khc th hin s tc ng ca cc c tnh ngoi vi
nu trn i vi th gii bn ngoi. Chc nng ca tng chn xut nhp trong mi cng hon
ton c th c xc lp v iu khin c thng qua cc thanh ghi SFR lin quan n chn
xut nhp .
Vi iu khin PIC16F877A c 5 cng xut nhp, bao gm PORTA, PORTB,
PORTC, PORTD v PORTE. Cu trc v chc nng ca tng cng xut nhp s c cp
c th trong phn sau.
8.1 PORTA
PORTA (RPA) bao gm 6 I/O pin. y l cc chn hai chiu (bidirectional pin),
ngha l c th xut v nhp c. Chc nng I/O ny c iu khin bi thanh ghi TRISA
(a ch 85h). Mun xc lp chc nng ca mt chn trong PORTA l input, ta set bit iu
khin tng ng vi chn trong thanh ghi TRISA v ngc li, mun xc lp chc nng
ca mt chn trong PORTA l output, ta clear bit iu khin tng ng vi chn trong
thanh ghi TRISA. Thao tc ny hon ton tng t i vi cc PORT v cc thanh ghi iu
khin tng ng TRIS (i vi PORTA l TRISA, i vi PORTB l TRISB, i vi
PORTC l TRISC, i vi PORTD l TRISD vi vi PORTE l TRISE). Bn cnh
PORTA cn l ng ra ca b ADC, b so snh, ng vo analog ng vo xung clock ca
Timer0 v ng vo ca b giao tip MSSP (Master Synchronous Serial Port). c tnh ny s
c trnh by c th trong phn sau.
Cu trc bn trong v chc nng c th ca tng chn trong PORTA s c trnh
by c th trong Ph lc 1.
Cc thanh ghi SFR lin quan n PORTA bao gm:
PORTA (a ch 05h) : cha gi tr cc pin trong PORTA.
TRISA (a ch 85h)

: iu khin xut nhp.

CMCON (a ch 9Ch) : thanh ghi iu khin b so snh.


CVRCON (a ch 9Dh) : thanh ghi iu khin b so snh in p. ADCON1 (a ch 9Fh)
: thanh ghi iu khin b ADC.
Trang 21

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.


8.2 PORTB
PORTB (RPB) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISB.
Bn cnh mt s chn ca PORTB cn c s dng trong qu trnh np chng trnh cho
vi iu khin vi cc ch np khc nhau. PORTB cn lin quan n ngt ngoi vi v b
Timer0. PORTB cn c tch hp chc nng in tr ko ln c iu khin bi chng
trnh.
Cu trc bn trong v chc nng c th ca tng chn trong PORTB s c trnh
by c th trong Ph lc 1.
Cc thanh ghi SFR lin quan n PORTB bao gm:
PORTB (a ch 06h,106h)
TRISB (a ch 86h,186h)

: cha gi tr cc pin trong PORTB


: iu khin xut nhp

OPTION_REG (a ch 81h,181h) : iu khin ngt ngoi vi v b Timer0.


Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.

Trang 22

n chuyn ngnh

GVHD : Nguyn Trng Khanh

8.3 PORTC
PORTC (RPC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISC.
Bn cnh PORTC cn cha cc chn chc nng ca b so snh, b Timer1, b PWM v
cc chun giao tip ni tip I2C, SPI, SSP, USART.
Cu trc bn trong v chc nng c th ca tng chn trong PORTC s c trnh by
c th trong Ph lc 1.
Cc thanh ghi iu khin lin quan n PORTC:
PORTC (a ch 07h) : cha gi tr cc pin trong PORTC
TRISC (a ch 87h)

: iu khin xut nhp.

Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.


8.4 PORTD
PORTD (RPD) gm 8 chn I/O, thanh ghi iu khin xut nhp tng ng l TRISD.
PORTD cn l cng xut d liu ca chun giao tip PSP (Parallel Slave Port). Cu trc bn
trong v chc nng c th ca tng chn trong PORTD s c trnh by c th trong Ph lc
1.
Cc thanh ghi lin quan n PORTD bao gm:
Thanh ghi PORTD : cha gi tr cc pin trong PORTD.
Thanh ghi TRISD : iu khin xut nhp.
Thanh ghi TRISE : iu khin xut nhp PORTE v chun giao tip PSP.
Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.
8.5 PORTE
PORTE (RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng l TRISE.
Cc chn ca PORTE c ng vo analog. Bn cnh PORTE cn l cc chn iu khin ca
chun giao tip PSP.
Cu trc bn trong v chc nng c th ca tng chn trong PORTE s c trnh
by c th trong Ph lc 1.
Cc thanh ghi lin quan n PORTE bao gm:
PORTE

: cha gi tr cc chn trong PORTE.

TRISE

: iu khin xut nhp v xc lp cc thng s cho chun giao tip PSP.

ADCON1 : thanh ghi iu khin khi ADC.


Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.
9 TIMER_0

Trang 23

n chuyn ngnh

GVHD : Nguyn Trng Khanh

y l mt trong ba b m hoc b nh thi ca vi iu khin PIC16F877A.


Timer0 l b m 8 bit c kt ni vi b chia tn s (prescaler) 8 bit. Cu trc ca Timer0
cho php ta la chn xung clock tc ng v cnh tch cc ca xung clock. Ngt Timer0 s
xut hin khi Timer0 b trn. Bit TMR0IE (INTCON<5>) l bit iu khin ca Timer0.
TMR0IE=1 cho php ngt Timer0 tc ng, TMR0IF= 0 khng cho php ngt Timer0 tc
ng.
Mun Timer0 hot ng ch Timer ta clear bit TOSC (OPTION_REG<5>), khi gi
tr thanh ghi TMR0 s tng theo tng chu k xung ng h (tn s vo Timer0 bng tn s
oscillator). Khi gi tr thanh ghi TMR0 t FFh tr v 00h, ngt Timer0 s xut hin. Thanh
ghi TMR0 cho php ghi v xa c gip ta n nh thi im ngt Timer0 xut hin mt
cch linh ng.
Mun Timer0 hot ng ch counter ta set bit TOSC (OPTION_REG<5>). Khi
xung tc ng ln b m c ly t chn RA4/TOCK1. Bit TOSE (OPTION_REG<4>)
cho php la chn cnh tc ng vo bt m. Cnh tc ng s l cnh ln nu TOSE=0 v
cnh tc ng s l cnh xung nu TOSE=1.
Khi thanh ghi TMR0 b trn, bit TMR0IF (INTCON<2>) s c set. y chnh l c
ngt ca Timer0. C ngt ny phi c xa bng chng trnh trc khi b m bt u thc
hin li qu trnh m. Ngt Timer0 khng th nh thc vi iu khin t ch sleep.
B chia tn s (prescaler) c chia s gia Timer0 v WDT (Watchdog
Timer). iu c ngha l nu prescaler c s dng cho Timer0 th WDT s khng c
c h tr ca prescaler v ngc li. Prescaler c iu khin bi thanh ghi
OPTION_REG. Bit PSA (OPTION_REG<3>) xc nh i tng tc ng ca prescaler.
Trang 24

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Cc bit PS2:PS0 (OPTION_REG<2:0>) xc nh t s chia tn s ca prescaler. Xem li


thanh ghi OPTION_REG xc nh li mt cch chi tit v cc bit iu khin trn. Cc lnh
tc ng ln gi tr thanh ghi TMR0 s xa ch hot ng ca prescaler. Khi i tng tc
ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa prescaler nhng khng lm thay
i i tng tc ng ca prescaler. Khi i tng tc ng l WDT, lnh CLRWDT s xa
prescaler, ng thi prescaler s ngng tc v h tr cho WDT.
Cc thanh ghi iu khin lin quan n Timer0 bao gm:
TMR0 (a ch 01h, 101h) : cha gi tr m ca Timer0.
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE).
OPTION_REG (a ch 81h, 181h): iu khin prescaler.
Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.
10 TIMER_1
Timer1 l b nh thi 16 bit, gi tr ca Timer1 s c lu trong hai thanh
ghi (TMR1H:TMR1L). C ngt ca Timer1 l bit TMR1IF (PIR1<0>). Bit iu khin ca
Timer1 s l TMR1IE (PIE<0>). Tng t nh Timer0, Timer1 cng c hai ch hot
ng: ch nh thi (timer) vi xung kch l xung clock ca oscillator (tn s ca timer
bng tn s ca oscillator) v ch m (counter) vi xung kch l xung phn nh cc s
kin cn m ly t bn ngoi thng qua chn RC0/T1OSO/T1CKI (cnh tc ng l cnh
ln). Vic la chn xung tc ng (tng ng vi vic la chn ch hot ng l timer hay
counter) c iu khin bi bit TMR1CS (T1CON<1>). Sau y l s khi ca Timer1:

Ngoi ra Timer1 cn c chc nng reset input bn trong c iu khin bi mt


trong hai khi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c set,
Trang 25

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Timer1 s ly xung clock t hai chn RC1/T1OSI/CCP2 v RC0/T1OSO/T1CKI lm xung


m. Timer1 s bt u m sau cnh xung u tin ca xung ng vo. Khi PORTC s
b qua s tc ng ca hai bit TRISC<1:0> v PORTC<2:1> c gn gi tr 0. Khi clear bit
T1OSCEN Timer1 s ly xung m t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1
c hai ch m l ng b (Synchronous) v bt ng b (Asynchronous). Ch m
c quyt nh bi bit iu khin

(T1CON<2>). Khi =1 xung m ly t bn ngoi s

khng c ng b ha vi xung clock bn trong, Timer1 s tip tc qu trnh m khi vi


iu khin ang ch sleep v ngt do Timer1 to ra khi b trn c kh nng nh thc
vi iu khin. ch m bt ng b, Timer1 khng th c s dng lm ngun xung
clock cho khi CCP (Capture/Compare/Pulse width modulation). Khi =0 xung m vo
Timer1 s c ng b ha vi xung clock bn trong. ch ny Timer1 s khng hot
ng khi vi iu khin ang ch sleep.
Cc thanh ghi lin quan n Timer1 bao gm:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE).
PIR1 (a ch 0Ch): cha c ngt Timer1 (TMR1IF).
PIE1( a ch 8Ch): cho php ngt Timer1 (TMR1IE).
TMR1L (a ch 0Eh): cha gi tr 8 bit thp ca b m Timer1.
TMR1H (a ch 0Eh): cha gi tr 8 bit cao ca b m Timer1.
T1CON (a ch 10h): xc lp cc thng s cho Timer1.
11.TIMER_2

Timer2 l b nh thi 8 bit v c h tr bi hai b chia tn s prescaler va


postscaler. Thanh ghi cha gi tr m ca Timer2 l TMR2. Bit cho php ngt Timer2 tc
Trang 26

n chuyn ngnh

GVHD : Nguyn Trng Khanh

ng l TMR2ON (T2CON<2>). C ngt ca Timer2 l bit TMR2IF (PIR1<1>). Xung ng


vo (tn s bng tn s oscillator) c a qua b chia tn s prescaler 4 bit (vi cc t
s chia tn s l 1:1, 1:4 hoc 1:16 v c iu khin bi cc bit T2CKPS1:T2CKPS0
(T2CON<1:0>)).
Timer2 cn c h tr bi thanh ghi PR2. Gi tr m trong thanh ghi
TMR2 s tng t 00h n gi tr cha trong thanh ghi PR2, sau c reset v 00h. Kh I
reset thanh ghi PR2 c nhn gi tr mc nh FFh. Ng ra ca Timer2 c a qua b
chia tn s postscaler vi cc mc chia t 1:1 n 1:16. Postscaler c iu khin bi 4 bit
T2OUTPS3:T2OUTPS0. Ng ra ca postscaler ng vai tr quyt nh trong vic iu
khin c ngt.
Ngoi ra ng ra ca Timer2 cn c kt ni vi khi SSP, do Timer2 cn
ng vai tr to ra xung clock ng b cho khi giao tip SSP.
Cc thanh ghi lin quan n Timer2 bao gm:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ton b cc ngt (GIE v PEIE).
PIR1 (a ch 0Ch): cha c ngt Timer2 (TMR2IF).
PIE1 (a ch 8Ch): cha bit iu khin Timer2 (TMR2IE).
TMR2 (a ch 11h): cha gi tr m ca Timer2.
T2CON (a ch 12h): xc lp cc thng s cho Timer2. PR2 (a ch 92h): thanh ghi h
tr cho Timer2.
Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.
Ta c mt vi nhn xt v Timer0, Timer1 v Timer2 nh sau:
Timer0 v Timer2 l b m 8 bit (gi tr m ti a l FFh), trong khi Timer1
l b m 16 bit (gi tr m ti a l FFFFh). Timer0, Timer1 v Timer2 u c hai ch
hot ng l timer v counter. Xung clock c tn s bng tn s ca oscillator. Xung tc
ng ln Timer0 c h tr bi prescaler v c th c thit lp nhiu ch khc
nhau (tn s tc ng, cnh tc ng) trong khi cc thng s ca xung tc ng ln Timer1
l c nh. Timer2 c h tr bi hai b chia tn s prescaler v postcaler c lp, tuy
nhin cnh tc ng vn c c nh l cnh ln. Timer1 c quan h vi khi CCP, trong
khi Timer2 c kt ni vi khi SSP. Mt vi so snh s gip ta d dng la chn c
Timer thch hp cho ng dng.
12 ADC
ADC (Analog to Digital Converter) l b chuyn i tn hiu gia hai dng tng t
v s. PIC16F877A c 8 ng vo analog (RA4:RA0 v RE2:RE0). Hiu in th chun
VREF c th c la chn l VDD, VSS hay hiu in th chun c xc lp trn hai chn
Trang 27

n chuyn ngnh

GVHD : Nguyn Trng Khanh

RA2 v RA3. Kt qu chuyn i t tn tiu tng t sang tn hiu s l 10 bit s tng ng


v c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s dng b chuyn i ADC,
cc thanh ghi ny c th c s dng nh cc thanh ghi thng thng khc. Khi qu trnh
chuyn i hon tt, kt qu s c lu vo

hai thanh ghi ADRESH:ADRESL, bit

(ADCON0<2>) c xa v 0 v c ngt ADIF c set.


Qui trnh chuyn i t tng t sang s bao gm cc bc sau:
1. Thit lp cc thng s cho b chuyn i ADC:
Chn ng vo analog, chn in p mu (da trn cc thng s ca thanh ghi ADCON1)
Chnh knh chuyn i AD (thanh ghi ADCON0).
Chnh xung clock cho knh chuyn i AD (thanh ghi ADCON0).
Cho php b chuyn i AD hot ng (thanh ghi ADCON0).
2. Thit lp cc c ngt cho b AD
Clear bit ADIF.
Set bit ADIE.
Set bit PEIE.
Set bit GIE.
3. i cho ti khi qu trnh ly mu hon tt.
4. Bt u qu trnh chuyn i (set bit ).
5. i cho ti khi qu trnh chuyn i hon tt bng cch:
Kim tra bit . Nu =0, qu trnh chuyn i hon tt.
Kim tra c ngt.
6. c kt qu chuyn i v xa c ngt, set bit (nu cn tip tc chuyn i).

7. Tip tc thc hin cc bc 1 & 2 cho qu trnh chuyn i tip theo

Trang 28

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Cn ch l c hai cch lu kt qu chuyn i AD, vic la chn cch lu


c iu khin bi bit ADFM v c minh ha c th trong hnh sau:

Cc thanh ghi lin quan n b chuyn i ADC bao gm:


INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ngt (cc bit GIE, PEIE).
PIR1 (a ch 0Ch): cha c ngt AD (bit ADIF).
PIE1 (a ch 8Ch): cha bit iu khin AD (ADIE).

Trang 29

n chuyn ngnh

GVHD : Nguyn Trng Khanh

ADRESH (a ch 1Eh) v ADRESL (a ch 9Eh): cc thanh ghi cha kt qu chuyn i


AD.
ADCON0 (a ch 1Fh) v ADCON1 (a ch 9Fh): xc lp cc thng s cho b chuyn i
AD.
PORTA (a ch 05h) v TRISA (a ch 85h): lin quan n cc ng vo analog PORTA.
PORTE (a ch 09h) v TRISE (a ch 89h): lin quan n cc ng vo analog PORTE.
13 COMPARATOR
B so snh bao gm hai b so so snh tn hiu analog v c t PORTA.
g vo b so snh l cc chn RA3:RA0, ng ra l hai chn RA4 v RA5. Thanh ghi iu
khin b so snh l CMCON. Cc bit CM2:CM0 trong thanh ghi CMCON ng vai tr chn
la cc ch hot ng cho b Comparator (hnh 2.10).
C ch hot ng ca b Comparator nh sau:
Tn hiu analog chn
VIN + s c s snh vi in p chun
chn VIN- v tn hiu ng ra b so
snh s thay i tng ng nh hnh v.
Khi in p chn VIN+ ln hn in p
chn VIN+ ng ra s mc 1 v ngc
li.
Da vo hnh v ta thy
p ng ti ng ra khng phi l tc thi
so vi thay i ti ng vo m cn c mt
khong thi gian nht nh ng ra thay
i trng thi (ti a l 10us). Cn ch
n khong thi gian p ng ny khi s
dng b so snh.
Cc tnh ca cc b so snh c th thay i da vo cc gi tr t vo cc bit
C2INV v C1INV (CMCON<4:5>).

Trang 30

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Cc ch hot ng ca b comparator.

Cc bit C2OUT v C1OUT (CMCON<7:6>) ng vai tr ghi nhn s thay i tn hiu analog
so vi in p t trc. Cc bit ny cn c x l thch hp bng chng trnh ghi nhn
s thay i ca tn hiu ng vo. C ngt ca b so snh l bit CMIF (thanh ghi PIR1). C
ngt ny phi c reset v 0. Bit iu khin b so snh l bit CMIE (Tranh ghi PIE).
Cc thanh ghi lin quan n b so snh bao gm:
CMCON (a ch 9Ch) v CVRCON (a ch 9Dh): xc lp cc thng s cho b so snh.
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php cc ngt
(GIE v PEIE).
Thanh ghi PIR2 (a ch 0Dh): cha c ngt ca b so snh (CMIF).
Thanh ghi PIE2 (a ch 8Dh): cha bit cho php b so snh (CNIE).
Thanh ghi PORTA (a ch 05h) v TRISA (a ch 85h): cc thanh ghi iu khin PORTA.
Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2.
Trang 31

n chuyn ngnh

GVHD : Nguyn Trng Khanh

14 B TO IN P SO SNH
B so snh ny ch hot ng khi b Comparator c nh dng hot ng ch
110. Khi cc pin RA0/AN0 v RA1/AN1 (khi CIS = 0) hoc pin RA3/AN3 v RA2/AN2
(khi CIS = 1) s l ng vo analog ca in p cn so snh a vo ng VIN- ca 2 b so
snh C1 v C2 (xem chi tit hnh 2.10). Trong khi in p a vo ng VIN+ s c
ly t mt b to in p so snh.
S khi ca b to in p so snh c trnh by trong hnh v sau:

B to in p so snh ny bao gm mt thang in tr 16 mc ng vai tr l


cu phn p chia nh in p VDD thnh nhiu mc khc nhau (16 mc). Mi mc c gi tr
in p khc nhau ty thuc vo bit iu khin CVRR (CVRCON<5>). Nu CVRR mc
logic 1, in tr 8R s khng c tc dng nh mt thnh phn ca cu phn p (BJT dn
mnh v dng in khng i qua in tr 8R), khi 1 mc in p c gi tr VDD/24.
Ngc li khi CVRR mc logic 0, dng in s qua in tr 8R v1 mc in p c gi tr
VDD/32. Cc mc in p ny c a qua b MUX cho php ta chn c in p a ra
pin RA2/AN2/VREF-/CVREF a vo ng VIN+ ca b so snh bng cch a cc gi tr
thch hp vo cc bit CVR3:CVR0.
B to in p so snh ny c th xem nh mt b chuyn i D/A n gin.
Gi tr in p cn so snh ng vo Analog s c so snh vi cc mc in p do b to

Trang 32

n chuyn ngnh

GVHD : Nguyn Trng Khanh

in p to ra cho ti khi hai in p ny t c gi tr xp x bng nhau. Khi kt qu


chuyn i xem nh c cha trong cc bit CVR3:CVR0.
Cc thanh ghi lin quan n b to in p so snh ny bao gm:
Thanh ghi CVRCON (a ch 9Dh): thanh ghi trc tip iu khin b so snh in p.
Thanh ghi CMCON (a ch 9Ch): thanh ghi iu khin b Comparator.

II. CP NHIT IN
iu u tin trong iu khin nhit l chng ta phi c c mt thit b (cm
bin) cho php o c nhit hin ti. C rt nhiu loi khc nhau, phn trnh by
y s cp mt s loi, c bit ch trng n Thermocouple.

Trang 33

n chuyn ngnh

GVHD : Nguyn Trng Khanh

2.1. Bui ban u ca thit b o nhit :


Galileo c cho l ngi u tin pht minh ra thit b o nhit , vo khong
nm 1592. ng ta lm th nghim nh sau : trn mt bn h cha y cn, ng cho treo
mt ng thy tinh di c c hp, u trn ca n c bu hnh cu cha y khng kh.
Khi gia tng nhit, khng kh trong bu n ra v si sng sc trong cn. Cn khi lnh th
khng kh co li v cn dng ln trong lng ng thy tinh. Do , s thay i ca nhit trong
bu c th bit c bng cch quan st v tr ca cn trong lng ng thy tinh. Tuy
nhin, ngi ta ch bit s thay i ca nhit ch khng bit n l bao nhiu v cha
c mt tm o cho nhit .
u nhng nm 1700, Gabriel Fahrenheit, nh ch to thit b o ngi H Lan,
to ra mt thit b o chnh xc v cho php lp li nhiu ln. u di ca thit b c
gn l 0 , nh du v tr nhit ca nc trn vi mui (hay ammonium chloride) v
y l nhit thp nht thi . u trn ca thit b c gn l 96 , nh du nhit
ca mu ngi. Ti sao l 96 m khng phi l 100 ?. Cu tr li l bi v ngi
ta chia t l theo 12 phn nh cc t l khc thi .
Khong nm 1742, Anders Celsius xut kin ly im tan ca nc gn 0
v im si ca nc gn 100 , chia lm 100 phn.
u nhng nm 1800, William Thomson (Lord Kelvin) pht trin mt tm o ph
qut da trn h s gin n ca kh l tng. Kelvin thit lp khi nim v 0 tuyt i
v tm o ny c chn l tiu chun cho o nhit hin i.
Sau y l phng trnh chuyn i ca 4 loi tm o :
C = 5/9(F 32)

F = 9/5C + 32

K = C + 273,15

R = F + 459,67

Tm o Rankine (R) n gin l tng ng ca Fahrenheit theo tm Kelvin, t


tn theo W. J. M Rankine (ngi tin phong trong lnh vc nhit ng).

2.2. Cc loi cm bin hin ti :


Ty theo lnh vc o v iu kin thc t m c th chn mt trong bn loi cm
bin : thermocouple, RTD, thermistor, v IC bn dn. Mi loi c u im v khuyt
im ring ca n.
2.2.1. Thermocouple
u im
L thnh phn tch cc, t cung cp cng sut.
n gin.
R tin.
Tm thay i rng.
Tm o nhit rng.
Khuyt im
Phi tuyn.
in p cung cp thp.
Trang 34

n chuyn ngnh

GVHD : Nguyn Trng Khanh

i hi in p tham chiu.
Km n nh nht.
Km nhy nht.
2.2.2. RTD (resistance temperature detector)
u im
n nh nht.
Chnh xc nht.
Tuyn tnh hn thermocouple.
Khuyt im
Mc tin.
Cn phi cung cp ngun dng.
Lng thay i R nh.
in tr tuyt i thp.
T gia tng nhit.
2.2.3. Thermistor
u im
Ng ra c gi tr ln.
Nhanh.
o hai dy.
Khuyt im
Phi tuyn.
Gii hn tm o nhit.
D v.
Cn phi cung cp ngun dng.
T gia tng nhit.
2.2.4. IC cm bin
u im
Tuyn tnh nht.
Ng ra c gi tr cao nht.
R tin.
Khuyt im
Nhit o di 200C.
Cn cung cp ngun cho cm bin.

Trang 35

n chuyn ngnh

GVHD : Nguyn Trng Khanh

2.3. THERMOCOUPLE
2.3.1. Hiu ng Seebeck
Nm 1821, Thomas Seebeck khm ph ra rng nu ni hai dy kim loi khc nhau
hai u v gia nhit mt u ni th s c dng in chy trong mch .
Nu mch b h mt u th th hiu in th mch h (hiu in th Seebeck) l

Kim loi A

Kim loi A

Kim loi B
mt hm ca nhit mi ni v thnh phn cu thnh nn hai kim loi.

+
eAB
-

Kim loi A
Kim loi B

Khi nhit thay i mt lng nh th hiu in th Seebeck cng thay i tuyn


tnh theo :
eAB = T vi l h s Seebeck
2.3.2. Cch o hiu in th

Cu

J3

Cu

+
v

Khng th o trc tip hiu


in th Seebeck bi v khi ni volt
k vi thermocouple th v tnh
chng ta li to thm mt mch mi.
V d nh ta ni thermocouple loi
T (ng-constantan).

Cu

Volt k

+
v1

J1

Constantan

J2

Khi ta c mch tng ng


nh sau :

Cu
Cu

+ v3

J3

+ v2

Cu

+
v1

Cu
J1

Constantan

Cu

+ v2

+
v1

J1

Constantan

J2

J2

Ci m chng ta mun o l hiu in th v1 nhng khi ni volt k vo thermocouple


th chng ta li to ra hai mi ni kim loi na : J2 v J3. Do J3 l mi ni ca ng vi ng
nn khng pht sinh ra hiu in th, cn J2 l mi ni gia ng vi constantan nn to
ra hiu in th v2. V vy kt qu o c l hiu ca v1 v v2. iu ny ni ln rng
Trang 36

n chuyn ngnh

GVHD : Nguyn Trng Khanh

chng ta khng th bit nhit ti J1 nu chng ta khng bit nhit ti J2, tc l


bit c nhit ti u o th chng ta cng cn phi bit nhit mi trng na.
Mt trong nhng cch xc nh nhit ti J2 l ta to ra mt mi ni vt l ri
nhng n vo nc , tc l p nhit ca n v 0C v thit lp ti J2 nh l mt mi ni
tham chiu.

+
v
-

Cu

Cu
Cu

Cu

+ v2

J2

Volt k

+
v1

Cu

+
v

J1

+ v2

Constantan-

+
v1

Constantan

T
J1

J2
T = 0C

Lc ny c hai mi ni ti volt k u l ng ng nn khng xut hin hiu in


th Seebeck. S c v trn volt k l hiu ca v1 v v2 :
v = (v1 v2) (tJ1 tJ2)
nu ta dng k hiu TJ1 ch nhit theo Celsius th :
TJ1 (C) + 273,15 = tJ1
do v tr thnh :
v = v1 v2 = [(TJ1 + 273,15) (TJ2 + 273,15)]
= (TJ1 TJ2) = (TJ1 0)

v = TJ1

Bng cch thm hiu in th ca mi ni ti 0C, gi tr hiu in th c c lc


ny l so vi mc 0C.
Phng php ny rt chnh xc nn im 0C c xem nh im tham chiu chun
trong rt nhiu bng tra gi tr in p ra ca thermocouple.
V d xt trn l mt trng hp c bit, khi m mt dy kim loi ca
thermocouple trng vi kim loi lm nn volt k (ng). Nhng nu ta dng loi
thermocouple khc khng c ng (nh loi J : st constantan) th sao? n gin l
chng ta thm mt dy kim loi bng st na th khi c hai u volt k u l ng st
nn hiu in th sinh ra trit tiu ln nhau.

+
v
-

Cu
Cu

Volt k

J3

J4

Fe
Fe

+ v2
J2

+
v1

J1

Constantan

Nu hai u ni ca volt k khng cng nhit th hai hiu in th sinh ra khng


trit tiu ln nhau, v do xut hin sai lch. Trong cc php o lng cn chnh xc,
Trang 37

n chuyn ngnh

GVHD : Nguyn Trng Khanh

ngi ta gn chng trn mt khi ng nhit. Khi ny cch in nhng dn nhit rt tt


nn xem nh J3 v J4 c cng nhit (bng bao nhiu th khng quan trng bi v hai
hiu in th sinh ra lun i nhau nn lun trit tiu nhau khng ph thuc gi tr ca
nhit ).
2.3.3. B nhit ca mi trng
Nh trn phn tch, khi dng thermocouple th gi tr hiu in th thu c b nh
hng bi hai loi nhit : nhit cn o v nhit tham chiu. Cch gn 0C cho
nhit tham chiu thng ch lm trong th nghim rt ra cc gi tr ca
thermocouple v a vo bng tra. Thc t s dng th nhit tham chiu thng l
nhit ca mi trng ti ni mch hot ng nn khng th bit nhit ny l bao
nhiu v do vn b tr nhit c t ra sao cho ta thu c hiu in th ch
ph thuc vo nhit cn o m thi.
B tr nhit khng c ngha l ta c lng trc nhit mi trng ri khi
c gi tr hiu in th th tr i gi tr m ta c lng. Cch lm ny hon ton
khng thu c kt qu g bi hai l do :
Nhit mi trng khng phi l i lng c nh m thay i theo thi gian
theo mt qui lut khng bit trc.
Nhit mi trng ti nhng ni khc nhau c gi tr khc nhau.
B nhit mi trng l mt vn thc t v phi xt n mt cch nghim tc. C
nhiu cch khc nhau, v phn cng ln phn mm, nhng nhn chung u phi c mt
thnh phn cho php xc nh nhit mi trng ri t to ra mt gi tr b li gi
tr to ra bi thermocouple.
2.3.4. Cc loi thermocouple
V nguyn tc th ngi ta hon ton c th to ra mt thermocouple cho gi tr ra
bt k bi v c rt nhiu t hp ca hai trong s cc kim loi v hp kim hin c.
Tuy nhin c mt thermocouple dng c cho o lng th ngi ta phi xt n
cc vn nh : tuyn tnh, tm o, nhy, v do ch c mt s loi dng
trong thc t nh sau :
Loi J : kt hp gia st vi constantan, trong st l cc dng v constantan l
cc m. H s Seebeck l 51V/C 20C.
Loi T : kt hp gia ng vi constantan, trong ng l cc dng v
constantan l cc m. H s Seebeck l 40V/C 20C.
Loi K : kt hp gia chromel vi alumel, trong chromel l cc dng v
alumel l cc m. H s Seebeck l 40V/C 20C.
Loi E : kt hp gia chromel vi constantan, trong chromel l cc dng v
constantan l cc m. H s Seebeck l 62V/C 20C.
Loi S, R, B : dng hp kim gia platinum v rhodium, c 3 loi : S) cc dng dng
dy 90% platinum v 10% rhodium, cc m l dy thun platinum.
R) cc dng dng dy 87% platinum v 13% rhodium, cc m
dng dy thun platinum. B) cc dng dng dy 70%

Trang 38

n chuyn ngnh

GVHD : Nguyn Trng Khanh

platinum v 30% rhodium, cc m dng dy 94% platinum v 6% rhodium. H s


Seebeck l 7V/C 20C.
2.3.5. Mt s nhit chun
Sau khi thit k mch xong th ngi ta cn mt s nhit chun dng cho cn
chnh. Bng sau y a ra mt s loi nhit chun :
Loi
im si ca oxygen
im thng hoa ca CO2
im ng
im tan ca nc
im si ca nc
im tan ca axit benzoic
im si ca naphthalene
im ng c ca thic
im si ca benzophenone
im ng c ca cadmium
im ng c ca ch
im ng c ca km
im si ca sulfur
im ng c ca antimony
im ng c ca nhm
im ng c ca bc
im ng c ca vng
im ng c ca ng
im ng c ca palladium
im ng c ca platinum

Nhit
-183,0 C
- 78,5 C
0 C
0,01C
100,0 C
122,4 C
218 C
231,9 C
305,9 C
321,1 C
327,5 C
419,6 C
444,7 C
630,7 C
660,4 C
961,9 C
1064,4 C
1084,5 C
1554 C
1772 C

Trang 39

-297,3F
-109,2F
32 F
32 F
212 F
252,3F
424,4F
449,4F
582,6F
610 F
621,5F
787,2F
832,4F
1167,3F
1220,7F
1763,5F
1948 F
1984,1F
2829 F
3222 F

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Trang 40

n chuyn ngnh

GVHD : Nguyn Trng Khanh

I. CU TRC PHN CNG TNG QUT :


Board mch iu khin c thit k nhm mc ch o v iu khin c th chia ra
lm 6 khi nh sau :
Khi x l trung tm : dng vi iu khin PIC 16F877A.
Khi hin th : Dng LED 7 THANH cho php hin th nhit
Khi cm bin: dng cm bin nhit l LM335
Khi iu khin:dng r le
Khi giao tip:dng bn phm HEX
Khi ngun : ngun chnh cung cp in p +5V cho ton mch,v cung cp in
p 12v dung cho r le
S khi m t mch :

Hin th
trng thi

Mch iu
khin

X l trung
tm
Cm bin

Ngun

Trang 41

n chuyn ngnh

GVHD : Nguyn Trng Khanh

II. CU TRC CHI TIT


2.1. KHI NGUN
Do mch cn ngun 5v dng cho pic v 12v dng cho r le nn mch ngun gm
ng vo 9v AC v 2 ng ra 5v , 12v DC.Dng 2 con IC LM7805 v LM7812
J9
ban phim
HI

HI

IN

RS403L
2
1

C1

1
1000uf /25V

OUT

D2

J5

GND

U1 LM7805
1

C2
10uF/25V

C3
104

R2
1K

nguon 9v
D1
3

U2
IN

GND

VCC 12V
1

OUT

LM7812C/TO3
C1

C1

1000uf /25V

10uf /25V

C4
104

1
2
3
4
5
g
f
vcc
a
b

J8
1
2
3
4
5
6
7
8

e
d
vcc
c
dot
10
9
8
7
6

10
9
8
7
6

e
d
vcc
c
dot

g
f
vcc
a
b

1
2
3
4
5

2.2. KHI HIN TH :

PORT B

led 7 doan

led 7 doan

R1
330

1
2

R2

330

led

Trang 42

n chuyn ngnh

GVHD : Nguyn Trng Khanh

2.3. KHI VI X L TRUNG TM :


U25

1
2

led

Q1

a1015

a1015
Q2

4k7

I H

4k7

23
24
25
26
18
17
16
15
14
13

33pF

RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CLK
RA3
RA2

J11
PORT B
19
20
21
22
27
28
29
30

RD0/PSP0
RD1/PSP1
RC4/SDI/SDA
RD2/PSP2
RC5/SDO
RD3/PSP3
RC6/TX/CK
RD4/PSP4
RC7/RX/DT
RD5/PSP5
RC3/SCK/SCL
RD6/PSP6
RC2/CCP1
RC1/T1OSO/CCP2 RD7/PSP7
RC0/T1SOI/TCLK
OSC2/CLKOUT
OSC1/CLK

11
12

3
2
1

RA1
RA0
MCLR/VPP

VDD
GND

HI

10k

2.4. KHI CM BIN


R7
3
10K
LM335/SO
1

1k

HI

Trang 43

1
2
NGUON 5V

31
32

PIC16F877A VDD
33pF

HI

1
2
3
4
5
6
7
8
PORTD

GND

CRY STAL

HI

1
2
3
4
5
6
7
8

HI

10
9
8
7
6
5
4

40
39
38
37
36
35
34
33

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT

n chuyn ngnh

GVHD : Nguyn Trng Khanh

IC LM335A l loi cm bin nhit bn dn, c nhy l 10mV/K. p to ra


do LM335A cm bin c l :
V2 = K.Ta [K] = K(273 + Ta) [C] = K.273 + K.Ta = C + KTa (C = K.273)
vi K = 10mV/K; C = 2,73V
c th trit tiu nh hng ca Ta, nhng li to ra mt mc in p l 2,73V
0C nn cn phi c mt khi tr 2,73V nhm to in p u ra l 0V 0C.
Bin tr R12 chnh l thnh phn b tr in p 2,73V nh ni trn.
U10 (dng OP07) ng vai tr b cng c khuch i, in p ra cui cng l :
V2
V 3 R 22 + R 23
R 22 + R 23

V1
Vout = 1 +
+

[(R17 + R 24) // R16]


R15
R15
R17 + R 24 R16

K .Ta
S .Td S .Ta
C
R 22 + R 23

+
+

Vout = 1 +

[(R17 + R 24) // R16]


R15

R17 + R 24 R17 + R 24 R16 R16

R 22 + R 23
V1
R15

Khng b nh hng ca nhit mi trng :


K .Ta
S .Ta
10mV
R17 + R 24 K

=0
= =
= 338,893
R17 + R 24 R16
R16
S 29,5V

chn R16 = 100 R17 + R24 = 338,893K chn R17 = 27K v R24 l bin
tr 10K. Khi cn iu chnh R24 trit tiu Ta.

Trang 44

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Trit tiu in p tnh (2,73V) :


C
R 22 + R 23
R 22 + R 23

V1 = 0

[(R17 + R 24) // R16]


1 +
R15
R15

R17 + R 24

vi (R17 + R24)//R16 = (338,893K)//(100) = 99,97


R 22 + R 23
R 22 + R 23
2,73

xV 1
1 +
=
x99,97 x
R15
R15
338893

R 22 + R 23
2,73
2,73
(1)
hay :
V 1
=
R15
3389,947 3389,947

khi , in p ra l :
S .Td
R 22 + R 23

Vout = 1 +
[(R17 + R 24 ) // R16]
R16
R15

in p ny c a trc tip vo ADC 12-bit (ICL7109) nn cn phi c mt s


tng thch v phn gii :
ADC 12-bit c 4096 mc.
in p vo ti a = 4,096V
1LSB = 4,048V/4096 = 1mV
iu khin n 409,6C :
1LSB = 409,6/4096 = 0,1C
tc mi khi tng 0,1C th in p ra tng 1mV :

0,1.S
R 22 + R 23
= 1mV
[(R17 + R 24) // R16]
1 +
R16
R15

( R17 + R 24) // R16 338,893


=
do :
339,893
R16
R 22 + R 23
R 22 + R 23
1+
= 339,893
= 338,893
R15
R15

chn R15 = 100 chn R22 = 27K; R23 l bin tr 10K.


Chnh R23 cho phn gii.
Thay vo (1) :
2,73
2,73

338,893xV 1
V 1 = 8mV
=
3389,947 3389,947

V1 c to ra t cu chia in p R11 = 3M v R12 l bin tr 10K.


cn chnh R5 V1 t 8mV
Cc t C14, C15, C16 chn gi tr 10F chng nhiu.

Trang 45

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Lu :
1. Cc bin tr nn dng loi bin tr tinh chnh (hay bin tr o lng) c cu to
gm nhiu vng dy in tr xon bn trong (chnh nhiu vng mi ht gi tr), trnh dng
bin tr thng thng rt kh chnh v khng n nh (khi va chm nh b thay i gi
tr).
2. Cc OPAMP dng loi OP07 hoc tng ng, c mc offset thp ph hp vi cc
i lng o c gi tr nh, cc chn 1 v 8 dng chnh offset khng dng trong thit k ny.

2.5.KHI MCH IU KHIN

1
2

J12
NGUON12V

J13
5V

J10

LS2
5
D4
DIODE

R9
330

1
2

4
1
2

NGUON 220V

OPTO ISOLATOR-A
RELAY SPDT
3

ISO1
R10

Q4A
TR_2_IS_N_A

2
2

1K2

MACH ROLE:

B ng ngt dng transistor:


ng ngt cc mch in t, ngi ta dng cc kha m in t. Cc kha ny c 2
trng thi phn bit, trng thi ng (cn gi l trng thi dn) khi in tr gia 2 cc ca
kha rt nh; v trng thi ngt (cn gi l trng thi tt) khi in tr ca kha rt ln, coi
nh h ech. Vic chuyn i kha t trng thi ny sang trng thi khc l do tc ng
ca tn hiu iu khin ng vo, ng thi qu trnh chuyn trng thi c thc hin vi
mt vn tc nht nh, gi l tc ng m ca kha.
lm kha in t ta c th dng transistor BJT hoc FET, ty theo in p phn cc
m transitor c th lm vic trng thi tt hoc dn (s dng ch khuch i hay
bo ha). Thng thng ngi ta s dng mch kha dng transistor BJT mc EC (cc
pht chung), bi v n i hi cng sut iu khin thp.

Trang 46

n chuyn ngnh

GVHD : Nguyn Trng Khanh

S mch tiu biu:


VCC
R

Vi

VCC/
Rc Ics

R1
Q

IB

Vces

VC
C

VC
E

Hnh b

VBE
Hnh c

VF: in p m.
Ics: dng Ic bo ha.
VCES : in p bo ha.
Mun cho transistor T1 nm trng thi ngt th in p UBE ca chuyn tip JE
phi nh hn in p ngng VF.
VBE< VF
Do phi tha mn iu kin :
VI +ICBO x R < VF
(IBCO :Dng r ) .
Transistor T1 lm vic trng thi dn khi VI tc ng xung dng, lc ny ty theo
dng ng vo IB m transistor dn c th lm vic vng khuch i hoc vng bo ha.
Trong mch khuch i: chuyn tip JE phn cc thun, chuyn tip Jc phn cc nghch.
Dng IB c gi tr dng v tha mn cc h thc sau.
IC = IB + ICEO
IE = IB + IC
in p cc thu VO = VCE = VCC -ICRC.

(1)

in p ng ra ph thuc vo tn hiu iu khin ng vo. Tuy nhin tng kh nng chng


nhiu ca kha chn transistor lm vic vng bo ha (v d nh im B trn mn hnh
b). Trong vng ny VI ln nn dng IB v dng IC cng ln.
T cng thc(1) do IC ln, suy ra:
VO = VCE rt nh (in p bo ha)
Trang 47

n chuyn ngnh

GVHD : Nguyn Trng Khanh

V CES = 0,1V n 0,2V


iu ny tng ng vi tnh trng c 2 chuyn tip JE v JC u phn cc thun.
Do VCES rt nh nn gi tr IC c xem nh VCC v RC quyt nh.
IC ? ICS = (VCC VCES)/ RC
IC = VCC /RC

T
VCC

Vi

R1
Q

RELAY

VCC =12v
VI 5 5v
VI = IBRB +VBE suy ra: IB = (VI -VBE )/RB
Trans bo ha:
IB ICmax /sat IC sat /sat v sat =20 25
VCC/RB (VCC -VCesat )/(sat Rreley)
sat Rreley RB
Chn = 20
Rreley =400
RB =3,3 K

2.6. KHI MCH GIAO TIP

J3
ban phim

R6 R5 R4
R
R R
enter
9

8
7
6
5
4
3
2
1

PORT D

Trang 48

n chuyn ngnh

GVHD : Nguyn Trng Khanh

...

III.LU GII THUT CHNG TRNH

Trang 49

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Bt u
c chng

trnh

Ly gi tr t
cm bin

Hin thi
nhit

Qut bn phm

Hin th
s phm

Kim tra
phm enter

ng rle

Ci nhit

Trang 50

n chuyn ngnh

GVHD : Nguyn Trng Khanh

IV.THNG S CC LINH KIN S DNG TRONG MCH


IV.1_TRANSISTOR C1815

Trang 51

n chuyn ngnh

GVHD : Nguyn Trng Khanh

Trang 52

n chuyn ngnh

GVHD : Nguyn Trng Khanh

IV.2

Trang 53

n chuyn ngnh

GVHD : Nguyn Trng Khanh

IV.3_RELAY

Trang 54

n chuyn ngnh

GVHD : Nguyn Trng Khanh

IV.4_LM335

LM335 l cm bin o nhit c chnh xc cao, c th iu chnh c. LM335


hot ng l mt diodezener hai cc, LM335 c mt in p nh thng t l tuyn
tnh vi nhit 10mv/*k.vi tr khng ng nh hn 1ohm, thit b hot ng
trong khon 400microampe n 5miliampe nhng trong thc t th khng thay i
trong khon .
Gii hn nhit m LM335 c th o t -40*C n 100*C

Trang 55

n chuyn ngnh

GVHD : Nguyn Trng Khanh

V.CHNG TRNH
#include <16F877A.h>
#device *=16 adc=10
#FUSES NOWDT, HS, NOPUT, NOPROTECT, NODEBUG, NOBROWNOUT, NOLVP,
NOCPD, NOWRT
#use delay(clock=12000000)
#use fast_io(b)
#use fast_io(c)
#use fast_io(d)
#use fast_io(e)
int8 chuc,donvi,x;
int8 b=2;
int8 i;
int d=0,f=0,c=0;
int8 const a[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
float value;
void hienthi();
void doiso()
{
donvi =x%10;
chuc =x/10;
}
void main()
{
set_tris_b(0);
set_tris_c(0);
set_tris_d(0);
set_tris_e(0);
while(true)
{
// Khoi tao che do cho bo ADC
setup_adc_ports(AN0);
setup_adc(ADC_CLOCK_INTERNAL);
set_adc_channel(0);
delay_us(10);
value= read_adc();
x = (value-558.6)/ 2.048;
doiso();
if(x<=99&&x>=0)
{
for(i=0;i<=80;i++)
{
output_b(a[chuc]);
output_c(0b00001000);
delay_ms(1);
output_c(0b11111111);
delay_us(2);
output_b(a[donvi]);
output_c(0b00000100);
delay_ms(1);
Trang 56

n chuyn ngnh

GVHD : Nguyn Trng Khanh

output_c(0b11111111);
delay_us(2);
}
output_d(0b10111111);
delay_ms(10);
if(input(pin_D3)==0)
{
if(b%2==0)
{
d=8;
b++;
output_b(a[8]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
b++;
c=8;
hienthi();
}
}
if(input(pin_D2)==0)
{
if(b%2==0)
{
d=9;
b++;
output_b(a[9]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
b++;
c=9;
hienthi();
}
}
output_d(0b11011111);
delay_ms(10);
if(input(pin_D3)==0)
{
if(b%2==0)
{
d=4;
b++;
output_b(a[4]);
output_c(0b00001000);
delay_ms(1000);
}
else
Trang 57

n chuyn ngnh

GVHD : Nguyn Trng Khanh

{
c=4;
b++;
hienthi();
}
}
if(input(pin_D2)==0)
{
if(b%2==0)
{
d=5;
b++;
output_b(a[5]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
c=5;
b++;
hienthi();
}
}
if(input(pin_D1)==0)
{
if(b%2==0)
{
d=6;
b++;
output_b(a[6]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
c=6;
b++;
hienthi();
}
}
if(input(pin_D0)==0)
{
if(b%2==0)
{
d=7;
b++;
output_b(a[7]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
Trang 58

n chuyn ngnh

GVHD : Nguyn Trng Khanh

c=7;
b++;
hienthi();
}
}
output_d(0b11101111);
delay_ms(10);
if(input(pin_D3)==0)
{
if(b%2==0)
{
d=0;
b++;
output_b(a[0]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
c=0;
b++;
hienthi();
}
}
if(input(pin_D2)==0)
{
if(b%2==0)
{
d=1;
b++;
output_b(a[1]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
c=1;
b++;
hienthi();
}
}
if(input(pin_D1)==0)
{
if(b%2==0)
{
d=2;
b++;
output_b(a[2]);
output_c(0b00001000);
delay_ms(1000);
}
Trang 59

n chuyn ngnh

GVHD : Nguyn Trng Khanh

else
{
c=2;
b++;
hienthi();
}
}
if(input(pin_D0)==0)
{
if(b%2==0)
{
d=3;
b++;
output_b(a[3]);
output_c(0b00001000);
delay_ms(1000);
}
else
{
b++;
c=3;
hienthi();
}
}
if(x>=f)
{
output_e(111);
}
else
{
output_e(000);
}
}
else
{
output_b(0b10111111);
output_c(0b00001000);
delay_ms(500);
output_b(0b10111111);
output_c(0b00000100);
delay_ms(500);
}
}
}
void hienthi()
{
int16 e;
for(e=0;e<=100;e++)
{
Trang 60

n chuyn ngnh

GVHD : Nguyn Trng Khanh

output_b(a[d]);
output_c(0b00001000);
delay_ms(10);
output_c(0b11111111);
delay_us(2);
output_b(a[c]);
output_c(0b00000100);
delay_ms(10);
output_c(0b11111111);
delay_us(2);
output_d(0b10111111);
delay_ms(10);
if(input(pin_D1)==0)
{
f=10*d+c;
}
}
}

Trang 61

You might also like