I

D
- V
DS
Characteristics
Physical Layout
Circuit Models
Large
Small signal
CMOS FET Introduction
V
GS
= V
DD
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
V
GS
= V
DD
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
I
D
V
DS
V
DS
1
ID-VD Square law
CMOS FET Introduction
V
GS
= V
DD
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
V
GS
= V
DD
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
I
D
V
DS
V
DS

(1)
L
G
S D
W
2
Small Signal Sq Law gm & gds
CMOS FET Introduction
V
GS
= V
DD
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
V
GS
= V
DD
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
I
D
V
DS
V
DS

(1)

(1)
3
Physical Overview parasitics
Contact Rs
Gate
Drain & Source
Cox
C
surface
Diodes
Cdb, Csb



CMOS FET Models
L
G
S D
W
Cox
4
ID-VD Subthreshold
CMOS FET Models

(1)
where I
DO
is the leakage current at V
G
= 0 and is
expressed as:

(1)
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
V
GS
= V
T
+ AV
1
V
GS
= V
T
+ AV
2
I
D
V
DS
V
DS
I
F
and I
R
are called the forward current and reverse
current respectively and can be expressed as

(1)

(1)
5
ID-VD Subthreshold (Cont)
CMOS FET Models
VGS = VT + AV1
VGS = VT + AV2
VGS = VT + AV1
VGS = VT + AV2
ID
VDS
VDS
I
F
and I
R
are called the forward current and reverse
current respectively and can be expressed as

(1)

(1)

(1)

(1)

(1)
6
ID-VD Subthreshold Slope
CMOS FET Models
VGS = VT + AV1
VGS = VT + AV2
VGS = VT + AV1
VGS = VT + AV2
ID
VDS
VDS

(1)

(1)

(1)
The n term in equations is defined as the sub threshold slope.

(1)
7
ID-VD Subthreshold Slope n
CMOS FET Models

(1)
G
S D
Cox
Cs
For BULK CMOS processes, n ranges from 1.25 to 2.
8
ID-VD Subthreshold Slope regions
Weak Inversion, IC << 1
Moderate Inversion, IC ~ 1
Strong Inversion, IC >> 1
Distinction between these three regions is
done on the basis of inversion coefficient.
CMOS FET Models

(1)
9
Small Signal Subthreshold gm & gds
Taking the partial derivative of I
D
w.r.t G,S,D
CMOS FET Models

(1)
VGS = VT + AV1
VGS = VT + AV2
VGS = VT + AV1
VGS = VT + AV2
ID
VDS
VDS

(1)

(1)
10
Small Signal Subthreshold gm & gds
Taking the partial derivative of I
D
w.r.t G,S,D





gds = I
D
/V
A
CMOS FET Models

(1)
VGS = VT + AV1
VGS = VT + AV2
VGS = VT + AV1
VGS = VT + AV2
ID
VDS
VDS

(1)
11
Small Signal Subthreshold gds
gmds (Triode VDS << 4U
T
)
gmds = gmd gms



gmds is a current controlled resistor






CMOS FET Models

(1)
12
CMOS FET Models
Subthreshold Advantages






13
CMOS FET Models

(1)
Subthreshold Disadvantages






14
Mismatch in CMOS Processes
Transistors
Threshold A
VT
dominant term
TOX , doping
Doping channel profile & Gate work function
Current term A

KPsat = unCox ~ 100s to 10s uA/V
2
Includes AL, AW, ATOX & mobility variations
Components
Rs, Cs, Ls
Diodes
CMOS FET Models
15
Mismatch in CMOS Transistors




Where
A
VT
~ 12.0 mV-um & 7.0 mV-um NMOS and PMOS
respectively node length dependent. (120 to 500nm)
TOX = 4.45nm & 4.6 nm range for 180nm processes
KPsat = unCox ~ 350 uA & 70 uA respectively @ V
T

CMOS FET Models

(1)

(1)

(1)
16
CMOS Components Resistors options




Matching factors Ma, Mw, Ml & Ms

Tolerance factors

CMOS FET Models
Specification N+ S/D
Resistor
(opndres)
P+ S/D
Resistor
(oppdres)
P+
Polysilicon
Resistor
(opppcres)
RR
Polysilicon
Resistor
(oprrpres)
RR_Serp
Resistor
(rr_serp.)
RP
Polysilicon
Resistor
(oprppres)
K1
BEOL
Resistor
(k1res)
Sheet R
(W/sq)
72 105 260 1600 1600 165 61
Temp Co
(ppm/C)
1900 1340 160 -1360
3.33
-1360
3.33
210 -387
0.41
Voltage Co
(%/V)
0.065 0.054 0 0 0 0 0
V Limit (V) <5.5 <5.5 <5.5 <5.5 <5.5 <5.5 <5.5
Current
(mA/um)
1 1 0.5 0.1 0.1 0.5 0.5

(1)

(1)
17
CMOS Components Capacitor options
MIM Metal Insulator Metal
Single, Dual, highK Single and Dual
2.05fF/um
2
,

4.1fF/um
2
,

2.7fF/um
2
,

5.4fF/um
2
,


MOM Metal fringe - Density approximately .
TempCo, VoltageCo,
Tolerance
Matching Ma, Mw, & Ml

CMOS FET Models

(1)
18
CMOS Transistor Model Parameters
hand analysis
Geometry W & L
Specific current
Slope n
Cgg, Cdd, & Css total cap seen at g, d, & s
A
VT
(K
VT
)
Early voltage VA
TempCos
V
T
-

0.5 to 2 mV/C,

KP = uoCox - mobility o 1/T
3/2
From Rm to 275C

CMOS FET Models
19
VT - TempCo

CMOS FET Models
Variation of VT over (27 C to 275 C) for PMOS and NMOS devices
of Peregrine 0.5um SOS process. 1.37mV/C
NMOS High Vt Threshold Variation with
temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
27 100 150 200
Temperarture
T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e
3/0.8
3/1
3/1.3
3/1.6
3/2
PMOS High Vt Threshold Voltage Variation with
temperature
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
27 100 150 200
Temperarture
T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e
3/0.8
3/1
3/1.3
3/1.6
3/2
20
KP - TempCo

CMOS FET Models
Variation of KP over (27 C to 275 C) for PMOS and NMOS W
equals 20@1.4um, and L equals 0.8um, and1.6um respectively.
Measured at V
GS
equal 1V, and V
DS
equal 50mV. Peregrine 0.5um
SOS process.
uo mobility o
1/T
3/2
From Rm to
275C n & p
mobility reduces
by approximately
60%.
21
MOS Switch
CMOS FET Basic Ckts
Square law
R =
L
KPWAV

Subthreshold
g
mds
= g
ds
=

=
I
D
nU
T

22
Current steering OR Differential pair
PLLs, current DACs
CMOS FET Basic Ckts
Tail Currernt
Tail Current
2
2
-

-

-

-
+

+

+

+
1
1
3
3
00 0
Avoid breaking tail current (Remains in Sat.)

Avoid both switches turning OFF simultaneously

Avoid full switch turn off (No inversion charge)
23
Current steering OR Differential pair
PLLs, current DACs
CMOS FET Basic Ckts
Charge injection errors WILL OCCUR
At turn on first currents are channel charge
(unavoidable)
At turn off last currents are injection currents (dummies
can help some, matching is typically poor)
Tail Currernt
Tail Current
2
2
-

-

-

-
+

+

+

+
1
1
3
3 00 0
24
Current steering OR Differential pair
CMOS FET Basic Ckts
Charge injection errors WILL OCCUR
At turn on first currents are channel charge
(unavoidable)
At turn off last currents are injection currents (dummies
can help some, matching is typically poor)
Dummy
Dummy
Tail Currernt
Tail Current
2 2
-

-

-

-
+

+

+

+
1
1
3
3
00 0
3
1
3
Dwn
Dwn
Up
Up
Dwn
3
1
Up
25
Basic Circuits Simple CD, CS, CC
CMOS FET Basic Ckts
vin
vo
V
D
D
vin
vo
V
S
S
vin
vo
Common Drain 0 =

1

=

1

26
Current Mirror Simple
CMOS FET Basic Ckts
M1 & M2
M1 & M2
I
D1 I
D2
I
D1 I
D2
1 1 01 =

1
1 0

1

2 2 02 =

2
2 0

2
2 0

2
=

1
1 0

27
Current Mirror Simple
CMOS FET Basic Ckts
M1 & M2
M1 & M2
I
D1 I
D2
I
D1 I
D2

1
I
D2
=

1
0

1 +
V
DS1
V
A

2
0

1 +
V
DS2
V
A

=

1
1 +
V
GS1
V
A

2
1 +
V
DS2
V
A


OR ideally

1
I
D2
=

1
1 +
V
GS1
V
A

2
1 +
V
DS2
V
A

~
Err Sources

W&L matching - Increase Area
VT matching Area Fix
Beta matching (KP = uo Cox)
VGS1 VDS2 Easy Fix

28
Current Mirror Stacked or Cascode

CMOS FET Basic Ckts
Stacking or cascading the mirrors
VGS1 = VGS2, VDS1 = VDS2
VB3 > VDSsat + VGS3
Sq Law
VB3 > AV1 + VTN + AV3 ~ VTN3 + 2AV for |1 = |3
VD4 > AV2 + AV4 = 2AV for |2 = |4
VTN1 + AV > 2AV OR VTN > AV + 90 C x TempCo ~ 200 to 300 mV

M1 & M2
M1 & M2
I
D1
I
D2
I
D1
I
D2
M3 & M4
V
B3
V
B2
I
D1 I
D2
M3 & M4
29
Current Mirror Stacked or Cascode

CMOS FET Basic Ckts
SubT
VB3 > AV1 + VGS3 ~ VTN3 - AV + 4UT for |1~|3
VD4 > VDS2 + VDS4 = 8-9 UT
VTN - AV > = 8-9 UT; VTN > 8-9 UT + n UT LN ID1/Is VTN > 300mV
+

1
I
D2
=

1
1 +
V
GS1
V
A

2
1 +
V
DS2
V
A

~

2
=

2
=

M1 & M2
M1 & M2
I
D1
I
D2
I
D1
I
D2
M3 & M4
V
B3
V
B2
I
D1 I
D2
M3 & M4
30
Current Mirror Stacked or Cascode

CMOS FET Basic Ckts
Current transfer or mirroring is set by the finger or multiplier ratio
Current transfer error or mismatch is dominated by VT and the geometry if
the smaller device
Current magnitude, BW, and error are controlled to a first order by the lower
devices
M3 & M4 control VDS1 and VDS2 or the effective of Early Voltage VA

1
I
D2
=

1
1 +
V
GS1
V
A

2
1 +
V
DS2
V
A

~

2
=

2
=

M1 & M2
M1 & M2
I
D1
I
D2
I
D1
I
D2
M3 & M4
V
B3
V
B2
I
D1 I
D2
M3 & M4
31
Current Mirror Stacked or Cascode

CMOS FET Basic Ckts
Current transfer or mirroring is set by the finger or multiplier ratio
Current transfer error or mismatch is dominated by VT and the geometry if
the smaller device
Small signal VSB3 = VSB4; k = m/n
gm2 = k gm1; g2 = k g1 ; Cgg2 = k Cgg1
gm4 = k gm3; g4 = k g3 ; Cgg4 = k Cgg3

1
I
D2
=

1
1 +
V
GS1
V
A

2
1 +
V
DS2
V
A

~

2
=

2
=

M1 & M2
I
D1 I
D2
g1 gm1 vg1 Cgg1 Cgg2 gm2 vg1 g2
i
i
n
VB3
g3 gm3 vg3
g4 gm4 vg4
I
o
u
t
32
Current Mirror Stacked or Cascode

CMOS FET Basic Ckts
Note for reliable matching L1 = L2 and M1 and M2 are laid out as fingers or
multiples ID2 = m/n ID1 and that mismatched is based on the smaller of m
or n. i.e. for n = 4, m = 8, L = .5um and W = .25um 3 sigma mismatch
equals approx.

1
I
D2
=

1
1 +
V
GS1
V
A

2
1 +
V
DS2
V
A

~

2
=

2
=

=
12.4
40.24. 5
= 1.4 12.4 = 17.5
M1 & M2
M1 & M2
I
D1
I
D2
I
D1
I
D2
M3 & M4
V
B3
V
B2
I
D1 I
D2
M3 & M4
33
I Proportional to Absolute Temp

CMOS FET Basic Ckts
Note for reliable matching L1 = L2 and M1 and M2 and M3 = M4 are laid
out as fingers or multiples. Select L >= Lmin!.
M1 & M2
M1 & M2
I
D1
I
D2
I
D1
I
D2
M3 & M4
V
B2
I
D1 I
D2
M3 & M4
Bias loop
Ideal 1:1 Mirror
Low voltage constant gm
I1 = I2=I; VGS1 = VGS2 + IR; VT1 =VT2; VS1 = VS2
VG1 VS1 VT1 = VG2 VS2 VT2+ IR

1
1 0

1
=

2
2 0

2
+
2

1 0

1
=

2 0

2
+

1 0

2 0

2
=

=

2
1
=

2
1

=

I (PTAT)
34
I Proportional to Absolute Temp

CMOS FET Basic Ckts
Note for reliable matching L1 = L2 and M1 and M2 and M3 = M4 are laid
out as fingers or multiples. Select L >= Lmin!.
2 0 =

2

1 0 =

1

M1 M2
M3 M4
Subthreshold
1 = 2 = ; 1 = 2 + ~

1
~

2
+

2
1
=

=
=

;
~

I (PTAT)

35
VB3 & VB2

CMOS FET Basic Ckts
Note for reliable matching L1 = L2
= L3 =L4 and M1 and M2 and M3
= M4 are laid out as fingers or
multiples.
a S
S = W/L
I
a S
S = W/L
I
VGS1 VGS2 > 4UT
VG1-nVS1 VT1 (VG2- nVS2 VT2) = > 4UT
VG1-nVS1 VT1 (VG2- nVS2 VT2) = VD > 4UT

1 0

2 0

2
> 4

2
1
> 4

> 4 ; = 2;

=
36
Stacked Devices

CMOS FET Basic Ckts
S
S = W/L
I
8 S
S = W/L
I
W/L
I
(3W(/(3L)
VB3
VB4
VB4
VB3
VB4
Compare the merits/demerits of
all three approaches used to
stack transistors in developing a
mirrored current.
Consider Area, Bandwidth, &
mismatch.
Cgg1 gm1 vg1 g1 C
L
AC
Device small signal model
Cgs = Cgg =WLCox/2,
g = gds = ID/VA,
gm/g = = VA/nUT, gm << g
Cd ~ Cgs/4 & CL << Cgs OR Cdb
37
VB3 & VB2

CMOS FET Basic Ckts
M1
M3 M4
I = I
M2
S
8 S
a S
b I = b I
VT2 =VT3 & VT1 < VT4 Simulation Check

1 0

2 0

2
+

3 0

4 0

4
> 5

2 4
1 3

1
> 5

S1 = S; S2 = 8 S; S3 = a S; b =2

2 4
1 3
> 5

8 4

>
5

= 2.5

8 4

>
5

= 2.5

>= 12.2; >= 12.2


=
+

38
Current Biasing Global & Local

CMOS FET Basic Ckts
M1 & M2
M1 & M2
ID1
ID2
ID1
ID2
M3 & M4
VB3
VB2
ID1 ID2
M3 & M4
Bias loop
M1 & M2
M1 & M2
ID1
ID2
ID1
ID2
M3 & M4
VB3
VB2
ID1 ID2
M3 & M4
Bias loop
1:1 Mirror 1:1 Mirror
IR VGS VGS
I ID ID
+ =
= =
2 1
2 1
Classical constant gm
Low voltage constant gm
Sq. LAW
1 + A1 = 2 +A2 +~ A1 = A2 +
A1
A2
1 =
|
2
A2 =

2

2

A1
A2
1 =
2

1
2
1 = ; 1 =

1
& 2 =

2

=

; = =
Classical VDD >| VTX| + AV1N + AV1P + AV2P where VTX the greater of |VTP|
OR VTN

Low Voltage VDD >| VTN| + AV1N + 2AVP approx. 600 or 700mV.

Typically m = 2 n to keep AV1 near AV2 and V
SB
small. In low voltage version R
and M2 can be interchanged.
39
Current Biasing Subthreshold

CMOS FET Basic Ckts
M1 & M2
M1 & M2
ID1
ID2
ID1
ID2
M3 & M4
VB3
VB2
ID1 ID2
M3 & M4
Bias loop
M1 & M2
M1 & M2
ID1
ID2
ID1
ID2
M3 & M4
VB3
VB2
ID1 ID2
M3 & M4
Bias loop
1:1 Mirror 1:1 Mirror
IR VGS VGS
I ID ID
+ =
= =
2 1
2 1
Classical constant gm
Low voltage constant gm
I Portioned to Absolute Temperature I
PTAP


gm set by R and LN(m/n) ratio Typ m/n = 4 to 8

Use sufficient Area to ensure matching M1 & M2 P & NMOS
Subthreshold
1 = 2 = ; 1 = 2 +

1
=

2
+

2
1
=

=
=

; =

40
Current Biasing Subthreshold

CMOS FET Basic Ckts
Develop a PTAT bias
generator assume a
20nA/Leg current.
Use a MOS resistor in place
of an actual resistor!
Homework values used
Model values Show All Work!
KP
(A/V^2)
IS
(A)
VT
(V)
Avt
(V-um)
VA Ls
(V) 0.25um
VA LL
(V) 0.75um
COX
(fF/um^2)
NMOS 330E-6 4.5-13 .3 12 3/2 5 9
PMOS 110E-6 9.0E-13 .35 8 3 10 9
ID-VD Subthreshold
VB1
+Vin/2 -Vin/2
VCM
=VDD/2
I
a
I
b
M1a M1b
VB1
I
I
a S S a S
S
41
Current Biasing Global to all analog Blks

CMOS FET Basic Ckts
Global Bias Generator

Bias source for all analog blocks i.e. PLL, Amplifiers, Voltage References, ADCs,
DACs, filters etc.
MP1
MP2
MN1 MN1
MP3
MN2
MN3 MN4 MN5 MN6
R1
MP5 MP4
CC1
VB1 MP6 MP7 MP8
MP9
MP10
MP14
MP13 MP12
MP11
MN14
MN15
MN13
MN12
MN11
MN10
MN9
MN8
MN7
I_SOURCE
I_SINK
VDD_REGULATED
VB3
VB4
VB2
Start up
Bias Loop and Tailless
Amplifier Cascode Bias voltages Bias legs
42
Current Biasing Global to all analog Blks

CMOS FET Basic Ckts
MP1
MP2
MN1 MN1
MP3
MN2
MN3 MN4 MN5 MN6
R1
MP5 MP4
CC1
VB1 MP6 MP7 MP8 MP9
MP10
MP14
MP13 MP12
MP11
MN14
MN15
MN13
MN12
MN11
MN10
MN9
MN8
MN7
I_SOURCE
I_SINK
VDD_REGULATED
VB3
VB4
VB2
Start up
Bias Loop and Tailless
Amplifier Cascode Bias voltages Bias legs
Constant
gm Sq. Law
PTAT Subthreshold & bipolar
Constant gain or AV Replace R with MOS R
Sq. Law
R =
1
|
R
AV
DD
=
2
|
2
AV
2

n
m
1; where L1 = L2 = L
|

=
A

; = =
AV2/AV
DD
approx. constant
Blocks
Bias Loop Positive feedback is
possible
Start-up REQUIRED! Start-up matters
Latch up is possible!
Bias Legs
43
M1 & M2
M1 & M2
ID1
ID2
ID1
ID2
M3 & M4
VB2
ID1 ID2
M3 & M4
Bias loop
1:1 Mirror
MP1
MP2
MN1 MN1 MN2
VG1 VG2
IB
Bias Loop & Startup
CMOS FET Basic Ckts
Blocks
Bias Loop Positive feedback is
possible
Start-up REQUIRED! Start-up matters
Latch up is possible!
Constant
gm Sq. Law
PTAT Subthreshold & bipolar
Constant gain or AV Replace R with MOS R
Sq. Law
R =
1
|
R
AV
DD
=
2
|
2
AV
2

n
m
1; where L1 = L2 = L
|

=
A

; = =
AV2/AV
DD
approx. constant
44
Bias Loop & Startup
CMOS FET Basic Ckts
Cascode Bias (optional) VB2 & VB3
VB3 > AV9 + VTN8 + AV8 ~ VTN8 + 2AV for |1 = |3
o SubT
VB3 > AV9 + VGS8 ~ VTN8 - nU
T
LN( + 4UT for |1~|3

3
=
7
=
8
+5 =

8
+5

8
= 5 =

8

5

7
2.5
VB2 is handled in a similar manner.
MP7 MP8
MP11
MN9
MN8
MN7
VB3
VB4
VB2
Cascode Bias voltages
VDD
VSS
Mirroring matching and therefor area of
rail side devices is critical
45
Bias Generators
CMOS FET Basic Ckts
Good practices
All rail side devices are long to reduce mismatch, 1/f noise,
improve PSRR. Their ONLY role is to establish stable low noise
bias currents.
All rail side devices have a finger or multiplicity common
denominator for N and PMOS devices
Rail side devices are 2-3X longer than stacked or cascode
devices. The accuracy is necessary.
Global bias sets gm of all analog blocks and as a result they all
track across temperature and process. The gm in bandwidth of
all analog blocks.
46
Amplifiers
CMOS FET Basic Ckts
Small signal parameters & some assumptions
gm I/nUT (SUbT), 2I/AV, (Sq. Law) other forms
gds = gd = g = V
A
/I
D
Cadence simulation
Cgg ~ Cgs ~ Cgg, Cadence simulation
Cgd << Cgs, Cdb, Cgg, AND Cdd ~ 0
47
Common Source
CMOS FET Basic Amplifers
I
D1
Vo
Cgg1 gm1 vg1 g1 C
L
AC

Figure 1.1 Common Source
1 +1 + = 0

=

1 +
=

1 +
=
/

1 +

1 +

=

1 +

48
Common Source
CMOS FET Basic Amplifers
I
D1
Vo
Cgg1 gm1 vg1 g1 C
L
AC



CS Observations
o Self gain independent of ID
o GBP equals gm/CL = gm/mCgg Larger loads require large
devices OR gm!
o VA increases with length increasing but decreases BW
o Increasing I decreases ro increasing f3dB and GBP.
49
Current Mirror
CMOS FET Basic Amplifers
M1 & M2
I
D1 I
D2
g1 gm1 vg1 Cgg1
Cgg2 gm2 vg1 g2
i
i
n
= 1 +1 1 + 2 +1 1
= 2 2 = 2 1; 1 = 2 =
2
1
= /

=
2
1 + 1 + 2 + 1

/
1 +
1 +

1
1

=
/
1 +
11 +

1

m/n should be kept small to maintain BW.
Yin(s) = gm + s(Cgg1 + Cggs
50
Common Drain Large Signal
CMOS FET Basic Amplifers
Vo
Cgg1 gm1 vg1 g1
AC
Vin
V
B1
CL
g2
CL
M1
M2
vo

=
1
+; > 5

=
1
+; > 5 =
1

1
+
51
Common Drain Small Signal Rgen =0
CMOS FET Basic Amplifers
Vo
Cgg1 gm1 vg1 g1
AC
Vin
V
B1
CL
g2
CL
M1
M2
vo
1 = 1 + 1 +2 +
(1 +1 +2 + ) = (1 + 1

1 + 1
1 + + 1
=
1 + 1
1 +( +1) 1
=
1 +
1
1

1 +
(+1) 1
1

52
Common Drain Small Signal Rgen 0

CMOS FET Basic Amplifers
Vo
Cgg1 gm1 vg1 g1
AC
Vin
V
B1
CL
g2
CL
M1
M2
vo
1 = 1 + 1 +2 +
= 1

=
1 + 1
1
2
+ 1(+1 1 2) + 1

1 + 1
1
2
1(21) + 1

Rgen adds second poles severely limits BW!!! --- Use can be quite limited!
53
Common Gate Cascode

CMOS FET Basic Amplifers
Vo
- gm2 vg2 g2 =g
vin
Vin OR VB1
V
B2
CL = nCgg2
g1 = g
Css2 = Cgg2
M1
M2

i
i
n
Ideal current source
Vo
CL = nCgg2
M2

g1
g2
gm1 vin
1 + 2 +1 +2 + 2 2
1 +2 + + 2
2 + 2 2 + 2
=
1 2
1 2

2
2
+ 2 +1
; & 2 < /
54
Common Gate Cascode

CMOS FET Basic Amplifers
Solving for vo/vin and sub n CL = Cgg2
=
1 2
1 2

1 2 2
2
+ 2 1 +1

12
2
2

2

2
+ 2 2 +1

Pole splitting --- dominant pole and non-dominant pole
=
12
+1 +1
=
12

2
+ + +1

12

2
+ +1


edom = 1/(2 r CL) = gm1/(2 1 CL) = gm1/(2 1 n Cgg2) ;
edom = gm1/(2 1 CL); GBP = gm1/CL = gm1/n Cgg2
enon = ad/d = gm2/Cgg2 = eTA2
enon > GBP then n ~> 1
55
Common Gate Cascode

CMOS FET Basic Amplifers
edom = 1/(2 r CL) = gm1/(2 1 CL) = gm1/(2 1 n Cgg2) ;
edom = gm1/(2 1 CL); GBP = gm1/CL = gm1/n Cgg2
enon = ad/d = gm2/Cgg2 = eTA2
enon > GBP then n ~> 1
20 Log A
f3dB
GBP = gm/CL
eT = gm2/Cgg
0dB
40 LOG dB
VA/nUT OR 2 VS/AV
gm = ID/nUT OR |AV
56
Differential Pair Sq. Law

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
aI
b
M1a M1b

2
=
1

1

1

2
;
=

=
1

1
;

+
1

= 2|

2|

2
1 +
|
2

|
2
2

2
1
|
2

|
2
2

=
|
2

|
2
2

2

Taking the derivative w.r.t. Vin = Vindif gmeff =
|

=
|

57
Differential Pair SubT

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
D
1
I
D
2
M1 M2
ID1 + ID2 = I;
VDiff = VG1 VG2;
=

1
1 0

2
2 0

2

Solving for I1-I2
k/n
- 1

I k/n

58
Differential Pair SubT

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
aI
b
M1a M1b

I
D
= I
F
-I
R
= I
DO
exp
V
G
nU
T
exp
-V
S
U
T
-exp
-V
D
U
T
I
DO
exp
V
G
nU
T
exp
-V
S
U
T

(1.1)

V
G
=

I
DO
1 exp
-V
S
U
T
+ n V
S

(1.1)
Substituting for V
GNA1
& V
GN1b

I
DO
1 exp
-V
S
U
T
+ n V
S

I
DO
1 exp
-V
S
U
T
+ n V
S

I
DO

I
DO
=

I
Db

59
Differential Pair SubT

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
aI
b
M1a M1b
Substituting I
Db
= I - I
Da
& solving for I
Da
and likewise for I
Db

=
exp
V
in
nU
T

exp
V
in
nU
T
+1
;

=

exp
V
in
nU
T
+1

=
exp
V
in
nU
T

exp
V
in
nU
T
+1

exp
V
in
nU
T
+1
=
exp
V
in
nU
T
1
exp
V
in
nU
T
+1

=
exp
V
in
nU
T
1
exp
V
in
nU
T
+1

=
exp
V
in
nU
T
1
exp
V
in
nU
T
+1
=

60
Differential Pair SubT

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
aI
b
M1a M1b
Summary
gmeff =I/(2 nUT) -- 1/2 nUT verses
|

=
|

Slew limiting +/- 5 =

OR Vin > 500mV 10

2
No even order harmonics
Taylor series

1
1
3

2
+
2
15

4

61
Differential Amp

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
a
I
b
M1a M1b
Vo
gp gmp vgp Cggp Cggp gm2 vgp gp
gmn vin/2 gn Cdb - gmn vin/2 gn
CL >> Cdbn OR Cdbp
Small signal simplifications
CL >> Cdb & Cgg = Css
gm >> g
Ignore gmbs effect
Cdb ~0

Vgp node:

2
+ + + + 2 2 + +
Vo node:

2
+ + + +

=
( + + 2 2 + 2 + + )
2 ( + + ) ( + + 2 2 + + + )


62
Differential Amp

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
a
I
b
M1a M1b
Vo
gp gmp vgp Cggp Cggp gm2 vgp gp
gmn vin/2 gn Cdb - gmn vin/2 gn
CL >> Cdbn OR Cdbp
Small signal simplifications
CL >> Cdb & Cgg = Css
gm >> g
Ignore gmbs effect
Cdb ~0


( + )
( + ) ( + )

2 ( + + 2 2 + + + )



+
;

63
Differential Amp

CMOS FET Basic Amplifers
VB1
+Vin/2 -Vin/2
VCM =VDD/2
I
a
I
b
M1a M1b
Vo
e3dB =( gn + gp)/CL
GBP = gmn/CL
0dB
20 LOG(
N
||p ) dB
enon = gmp/Cp
ez = 2gmp/Cp


+
;

64
Low gain Amps

CMOS FET Basic Amplifers
Low gain amplifiers with
gm loading
Small signal simplifications
CL >> Cdb & Cgg = Css
gm >> g
Ignore gmbs effect
Cdb ~0

VCMo
VCM
REF
Vo
VB1
M1CMd M1CMa
I
C
M
t
a
i
l
I
C
M
t
a
i
l
/
2
I
C
M
t
a
i
l
/
2

VB3
M2CMb M2CMa
Vo
gmn vo gn/n CL
(VCM
REF
-Vcmo) gmp/2 gp
Vo node:

2
+ +/ + +
=

+

=
|
|

+

Square law adjusting geometry controls gain
65
Low gain Amps

CMOS FET Basic Amplifers
Low gain amplifiers with
gm loading
Small signal simplifications
CL >> Cdb & Cgg = Css
gm >> g
Ignore gmbs effect
Cdb ~0
Subthreshold gain adjust
gmp/gmn = I
CMtail
/Ip = 1/a where a < 1 taking on values of to 1/8.
=

VCMo
VCM
REF
Vo

VB4
VB1
M1CMd M1CMc M1CMb M1CMa
I
C
M
t
a
i
l
a

I
C
M
t
a
i
l
/
2
a

I
C
M
t
a
i
l
/
2
[
1
-
a
]

I
C
M
t
a
i
l
/
2
[
1
-
a
]

I
C
M
t
a
i
l
/
2
VB3
VB4
M2CMb M2CMa
Gain = A = 1/o2
Vo
gmn vo gn/n CL
(VCMREF -Vcmo) gmp/2 gp
66
Low gain using negative feedback


CMOS FET Basic Amplifers
Low gain amplifiers with
gm loading
Small signal simplifications
CL >> Cdb & Cgg = Css
gm >> g
Ignore gmbs effect
Cdb ~0

VCMo
VCM
REF
VB1
M1CMd M1CMa
I
C
M
t
a
i
l

~

4
(
2

+
1
/
n
)

I
S
T
A
B

I
C
M
t
a
i
l
/
2
I
C
M
t
a
i
l
/
2

VB3
M2CMb M2CMa
2(n+1) 2(n+1) 2n 2n
Gain = A = (2n+1)/2
~ n
(4n+2) (4n+2)
2

I
S
T
A
B
4(2n+1)
Vo
Vo
(VCMREF -Vcmo) gmp/2 gp
vo gmna - gmnb vo gn/n CL
Vo node

2
+
+

+ +
~

2
+
+

+

=

A +

A


A =
2 +2 2
4 +2
=
1
2 +1
;
67
DC Voltage Reference


CMOS FET Basic Amplifers
R5
R4 D1
NETB
R1
D2
NETC
VREF
R5
R4

(1)

(1)

(1)
V
REF
=
n V
T
lnK N.R
1
R
1
+
N V
D1
L

68
DC Voltage Reference


CMOS FET Basic Amplifers
R5
R4 D1
NETB
R1
D2
NETC
VREF
R5
R4
L=
V
D1
T
n lnK
V
T
T
=9.41
N=
V
REF
n V
T
ln K +
V
D1
L
=3.28
69
V
REF
=
n V
T
lnK N.R
1
R
1
+
N V
D1
L

DC Voltage Reference


CMOS FET Basic Amplifers
L=
V
D1
T
n lnK
V
T
T
=9.41
N=
V
REF
n V
T
ln K +
V
D1
L
=3.28
MP7
MP8
R5
R4 D1
MP9 MP9
MP10
MP11
MP12
MN7
MN8
MN6
MN5
R1
D2
MP13
MP14
C
C
V
DDA
NETC
NETB
VB
VB2
VB1
VB
c
R6
MP15
MP16
V
REF
CL
R5
R4
70
V
REF
=
n V
T
lnK N.R
1
R
1
+
N V
D1
L

DC Voltage Reference


CMOS FET Basic Amplifers
L=
V
D1
T
n lnK
V
T
T
=9.41
N=
V
REF
n V
T
ln K +
V
D1
L
=3.28
VDD_REGULATED
Start up Bias Loop
PTAT & CTAT Legs
Voltage Reference
c
MP1
MP2
MN1 MN1 MN2
MP3
MP4
MN3
MN4
MP7
MP8
R5
R4 D1
MP5
MP6
MP9 MP9
MP10
MP11
MP12
MN7
MN8
MN6
MN5
R1
D2
R2
R3
R6
MP13
MP14
MP15
MP16
VREF
MP17
MP18
LDO2
LDO1
CC
VDDA
NETC
NETB
VB
CL
VB2
MP19 MP19
MP20
71
V
REF
=
n V
T
lnK N.R
1
R
1
+
N V
D1
L

Gain Boosting


CMOS FET Basic Amplifers
Vo
- gm2 vg2 g2 =g
vin
Vin OR VB1
CL = nCgg2
g1 = g
Css2 = Cgg2
M1
M2

Ideal current source
Vo
CL = nCgg2
M2

g1
gm1 vin
g1
Cd = Cdb + Csb
gmb vs gb
vo node; 2 + ( + ) 2 = 0
vs node; + 2 2 + + 2 1 +
= 0
vg node 2 + + + 2 = 0;
vfb (optional Closed Loop) ( + ) = 0
Low gain amplifiers with
gm loading
Small signal simplifications
CL >> Cdb & Cgg = Css
gm >> g
Ignore gmbs effect
Cdb ~0
72
Gain Boosting


CMOS FET Basic Amplifers
Solving for Av = vo/vin and substituting for b x gmbst = gm1 = gm2 = gm, g1 = g2 = b x gbst = g, =
gm/g and >>1.
@ DC [ = /( ) = /( ^3) =
/ 2 = /( ^2)]
=
( + ) ( )
(
2

3
+
2
+
2
+
2
)

=

; =

=
^2
3
+
2
+
2

2

(
2

3
+
2
+
2
+
2
)

e =

; e =

; ;

;
GBP = gm/CL;
Observations:
Increased gain at no loss in GBP bandwidth
Scale boosting by k =
gm/Cp = eTA >> GBP = gm/CF

73
Noise Basics


Noise
Noise Basics
Noise is just another signal error like CMRR and PSRR
EMI RF coupling supply & ground, crosstalk, rectification
Measurement errors quantization noise
Electronic
Thermal constant value across frequency vn
2
= 4 kTR
Temperature T in Kelvin, k Boltzmanns constant, R in ohms
Shot in
2
= 2 q I
DC
(current flow across a P-N junction (charge impulse white spectrum)
DC current flow, q charge on a carrier
Flicker or 1/f - V
nf
(f) = K
v
/\f i.e. 10 uV/\Hz
Avalanche noise PN junction breakdown
Phase noise alternate form of thermal, shot and1 /f etc.
Input/output referred Cs
74
Noise Basics


Noise
Definitions Noise related

V
nrms
= [1/T} v
n
2
(t) dt]
1/2
I
nrms
= [1/T} i
n
2
(t) dt]
1/2

P
diss
= V
nrms
2
/ 1 O 1 ohm for simplicity
SNR = 10 Log {Signal Pwr/Noise Pwr} even if R = 1 O it cancels
SNR = 10 Log {(Vp
2
/2)/ V
nrms
2
} = SNR = 20 Log {Vp/ (2 V
nrms
)}
dBm - Refencing of signals to 1 mW or 223.6 mV across a 50 O resistor
Types of noise Thermal, 1/f, quantization, distortion, and EMI
We are concerned with only thermal and 1/f in this context.
`
10^
-5
10
-6
10
-7
10
-8
10
2
10
4
10
6
10
8
10
10
10
12
V
/
r
t
(
H
z
)
Hz
75
Noise Basics


Noise
Noise is random with a mean value of zero, hence we use mean square values, which are
measurements of the dissipated noise power levels. The effective noise power of a source is
measured in root mean square of rms values.

2
;

2
;
Noise spectrum density describes the noise power in a 1 Hz bandwidth using units of V
2
/Hz
and plotted as above as V/\Hz.
Total or effective noise is found by integrating the spectral noise density function

2
1
=

2
1

Uncorrelated noise - Noise sources, thermal and 1/f are for the most part considered
uncorrelated
Therefore

V
2
no
= V
2
n1
+ V
2
n2
V
2
n3
+ ... + V
2
nn
and likewise for noise currents.
I
2
no
= I
2
n1
+ I
2
n2
i
2
n3
+ ... + I
2
nn

Square root sum of the squares
76
Noise Basics


Noise
** ** **
**
Vn1(t)
Vn2(t)
In1(t) in2(t)
Vno(t)

Summing uncorrelated noise voltages and currents, i.e. thermal noise.

EX if two noise sources have uncorrelated voltage of 5 and 10 uVs respectively the total
noise generated is
V
no
= \{(5E-6)
2
+ (10E-6)
2
} = 11.2uV This is a Stochastic problem
77
Filtered Noise - Ideal


Noise
Filtered or band limited white or thermal noise, shot noise (P-N unction carrier flow)
V
2
no
= } | A(je)| V
2
ni

where A(s) is the filter function.
EX -- V
2
ni
is white and has a root spectral density of 20 nV/\Hz. Find the total noise from DC to
100kHz. Assuming a Brickwall filter with a gain of 1

2
= |e|

2
1
= 1 20 nV/\Hz
2
10
5
0
= 4x 10
7
(nV)
2

Note input noise terms from multiple sources can be combined before or after filtering.
78
Filtered Noise 1
st
Order


Noise

If | A(je)| were a 1st Order filter the it would be weighted as follows;

f
x
= t/2 f
o
where f
o
= 1/(2t R C)

Repeating the above example for a 1st Order filter

V
2
no
= } | A(je)| V
2
ni
= } t/2 {20}
2
df
i
= 2.0t x 10
7
(nV)
2

79
1/f Noise

Noise
1/f Tangent Principal
Observation - a function proportional to 1/x results in equal power over each decade. For 1/f noise the
noise total noise power doubles ever decade. BW increases by 10 and x.

2
= |e|

2
1
= 1
1

10

= Lnf|

10
= 2.3
LN(10
k
f1)- LN(f) = K LN(10) = k 2.3 for k decades OR v
eq
= \(k 2.3)
Never Open the BW any wider than is essential to achieve the desire task to avoid degrading
performance by added noise. This is a matched filter problem.
80
Device Noise

Noise
Resistors V
2
R
(f) = 4kT R Thermal
1KO ~ 4.0 nV/\Hz @ Rm Temp

Diodes I
2
d
(f) = 2q I
D
Shot
r
d
= V
t
/ nI
D
No noise

BJT I
2
i
(f) = 2q {I
B
+ KI
B
/f + I
C
/||(je)|}
V
2
i
(f) = 4kT {r
b
+ 1/g
m
}

MOS I
2
i
(f) = 4kT { 2/3} g
m
shot
V
2
i
(f) = K/ {WLC
ox
f} 1/f
Active MOS device currents can be converted to a equivalent input voltage by dividing by g
m
2
. k
= Boltzmans Constant, q charge of an electron.
V
2
iT
(f) = K/ {WLC
ox
f} + {4kT (2/3)} /g
m
MOS example equivalent gate input V
2
/Hz
81
Why kT/C?

Noise
EX -- V
2
ni
is white. Find the total noise from DC to f
o
. Assuming a RC filter
v
in
v
out
v
in
v
out

2
= |e|

2
1
= 1/|1 +
jf
fo
|
10
5
0
=

where A(je) = 1/(1 + jf/f
o
), f
eff
= t/2 f
o
and f
o
= 1/(2t R C) and k = Boltzmans Constant

= C kT V
no
/ =
Nice toKnow- For a 1 pFd Cap the noise floor is at ~ 64 uV
As a perspective 1V/2
14
= 61 uV
OBSERVATIONS
In dependent of BW a 1 pFd Cap preserves a 61 uV noise floor. To increase the BW the only
alternative is to decrease Rs, OR inc. g
m
, i.e. Widen MOS switch size. At the penalty of increased charge
injection error and power consumption.
82
Noise Figure/Factor

Noise
The noise factor (F) of a device specifies how much additional noise the device will contribute to the
noise already beyond that contributed by the equivalent source generator.
The total equivalent input noise voltage

2
=
2
+
2
+
2

=

2
+
2
+
2

2
= 1 +

2
+
2

2
= 1 +

2
+
2

4
=

Noise figure (NF) is the Noise factor converted to dB i.e.

NF = 10 log (F)

Signal to Noise Ratio

F vnsveqSNRSNR Thus,

=

.
=

2

=
.

=

2

2

2

2
=

2

2

83
Quantization Noise

Noise
10 bit ADC EX - Find the SNR of a sine wave which spans the full scale range of a 10 bit ADC assuming a
perfect ADC (quantization error only) and all other noise sources have been properly managed. V
FS
=
2.828 V
Quantization SNR = 20 Log (Pwr out)/(Quantization pwr) = 20 Log [{V
FS
/(2\2)}/(V
FS
/2
n
)]
where n is the number of bits or 10
SNR = 20 Log [{V
FS
/(2\2)}/(V
FS
/{2
n
\(12) }] = 20 n Log (2) + 20 Log (\(6)/2)
SNR = 6.02 n +1.76 dB = 61.9 dB
Note All electronics; Buffer amplifiers, Track and Holds, Comprators etc. must preserve this SNR by
being at least 9 to 12 dB down from the quantization noise.
84
Knee frequency f
Knee

Noise
Determine f
Knee
For a MOSFET assuming gate current is 0



V

2
=
4
2
3

Thermal Noise


V
1/
2
=

1/f Noise

Setting both noise terms equal and solving for f

T k 8 Cox L
V KP 3 K

T k Cgs 4
gmK
f
2
f f
Knee
A
= =

Increase L to reduce f
knee
!
85
Noise Summary


Noise

1/
2
= |e|

2
1
= 1
1

10

= Lnf|

10
= 2.3

2
= |e|

2
1
= 1 v

2
10

= v

2
10

f f v

2
10

f
Approx 3X increase/decade
86
OTA Example


Noise
v

2
=
4
2
3

Thermal Noise


v
1/
2
=

1/f Noise
i

2
= 4
2
3
Thermal Noise
i
1/
2
= gm
2

1/f Noise
M5 a & b
M1 a & b
M3 a & b
VCM
VCM
in
1a
in
1b
in
3b
in
3a

in5
b
in
5a
87
OTA Example


Noise
M5 a & b
M1 a & b
M3 a & b
VCM
VCM
in
1a
in
1b
in
3b
in
3a

in5
b
in
5a
Approach Independent of transistor mode of operation,
1. Input or Output referred
a. Noise or Current
2. Short Inputs and Output through metal amp meter
3. Transformation voltages currents or currents to voltage
a. io = gm vin
b. vin = io/gm
4. In5 is common mode
a. ss noise is common mode contribution is operation dependent
i. ss common mode
ii. large signal error contribution
88
OTA Example


Noise
M5 a & b
M1 a & b
M3 a & b
VCM
VCM
in
1a
in
1b
in
3b
in
3a

in5
b
in
5a
Amp meter output noise (Thermal)
i

2
= 2in
1
2
+ 2in
2
2
= 2 4
2
3

1
+2 4
2
3

2

Input refer divide by gm
1
2

v

2
= 2
4
2
3

1
2
+2
4
2
3

1
2
=
16
3
1
1 +

1
without I tail
v

2
=
16
3
1
1 +

1
+

1
with I tail Slewing
v
1/
2
= 2

1
2

1
2
+2

3
2

3

1
2
+2

5
2

3

1
2
=
2

1 +

2
+

2

Observation
1/f increase Area as feasiable.
Increase gm1 as much as practical little option in subthreshold gm1 = gm3 = gm5/2.
v
1/
2
= 2

+2

+2
2

=
2

1 +

3
+4

5

89
OTA Example


Noise
M5 a & b
M1 a & b
M3 a & b
VCM
VCM
in
1a
in
1b
in
3b
in
3a

in5
b
in
5a
When does tail noise matter & how?
90
Cascode Devices


Noise
Cascode (common gate)
ALL Cascode Error currents OR gate voltage are reduced by 1/ !!!
Cascode transistors do not contribute to output or input effective noise!
In fact any noise at the gate of the cascade maybe ignored to a first order!
Decreasing PSRR & CMRR errors!
ierr
2
= (verr g
3
)
2
+ 8/3 kT gm
3
inoise
2
= 8/3 kTg
3
2
/gm
cc
+ 8/3 kT gm
3
inoise
2
= 8/3 kT gm
3
[1 + g
3
/[gm
cc

3
]
inoise
2
~ 8/3 kT gm
3
verr
g3
in
3
verr
2
= 8/3 kT/gm
cc

Mcc
91
Fully Differential Cascode
Noise
Observe that cascading of M3 and M4 implies only M1, M3, and M4
and possible M5 contribute noise.
M5 a & b
M1 a & b
M3 a & b
VCM
VCM
in
1a
in
1b

in5
b
in
5a
in
3a in
3b
V
B4
M4 a & b

in4
b
in
4a
V
B3
V
B2
V
B1
V
B1
92
Fully Differential Cascode
Noise
Observe that
cascading of M3 and
M4 implies only M1,
M3, and M4 and
possible M5
contribute noise.
M5 a & b
M1 a & b
M3 a & b
VCM
VCM
in1a in1b

in5b in5a
in3a in3b
VB4
M4 a & b

in4b in4a
VB3
VB2
VB1
VB1
v

2
= 2
4
2
3

1
2
+2
4
2
3

1
2
+2
4
2
3

1
2
=
16
3
1
1 +

1
+

1

v

2
=
16
3
1
1 +

1
+

1
+

1
with I tail Slewing
v
1/
2
= 2

1
2

1
2
+2

3
2

3

1
2
+2

4
2

3

1
2
=
2

1 +

2
+

2

93
Fully Differential Cascode - Observations
Noise

1. Cascode transistors do not contribute to output or input effective noise!
2. Cascode transistors set or limit BW indirectly dictating L or L
fTA
~ L
1
.
3. Select ALL rail side devices (W/L)
rail
as large as feasible! i.e. 2 to 3X longer
than L
fTA
.
94
Fully Differential Cascode - Observations
Noise
1. Increasing L
rail
to 3 L
fTA
and W
rail
to 3 W
fTA
or rail side area by 9 and gm1 ~gm4
~ 2 gm3.
v
1/
2
<
2

1 +

1
9

2
+
1
9

1 +

1
9

2

2. Vos is an err much very similar to 1/f & by inspection
v

2
=

1
2

1
2
+

3


3
2

1
2
+

4


4
2

1
2
=

1 +

2
+

2

95
Fully Differential Cascode - Observations
Noise
Again observing that rail side device are increased by ~ 9X and assuming gm1
~gm4 ~ 2 gm3.
v

2
<

1 +

2

1
9

2
+
1
9

1 +

2

1
9

2

Note that the fully differential OTA neglects both noise and offset errors created by the Common Mode
Feedback (CMFB) circuit.
96
Fully Differential Cascode with 2
nd
Stage
Opamp Compensation
VB3
VB4
VB1
VB2

VB3
VB4
VB1
VB2
VB1
Vop Vom
VB1
B
VCMo VCMREF
Vip Vim
VB1
Cc Cc
Cc
Cc Rz Rz
Vop Vom
VCMo
A
A B
I
D
P
I
P
I
N

F
r
o
m

G
l
o
b
a
l

B
i
a
s
VB1
VB2
VB3
VB4
VB3
WLP/LLP
WLN/LLN
WLP/LLP
WLN/LLN
WLN/LLN
VB1
M1DAb
M1DAa
I
C
M
t
a
il
WLN/LLN
CM Amplifier
VB3
VB3
Optional split
transistor
Interdigitated
Transistors
Cc
Cc
I
P
WLP/LLP
I
D
P
I
N
M3a M3b
M4a M4b
Stage 1 folded cascode
Avol o
2
or greater when boosting is applied.
GBP = gm
1
/C
L
C
L
= Cin stage 2
Stage 2 common source
Avol o

GBP = gm
2
/C
L
C
L
= effective load with feedback.

Signal swing ~VDD-6U
T

97
Fully Differential Cascode with 2
nd
Stage
Opamp Compensation
VB3
VB4
VB1
VB2

VB3
VB4
VB1
VB2
VB1
Vop Vom
VB1
B
VCMo VCMREF
Vip Vim
VB1
Cc Cc
Cc
Cc Rz Rz
Vop Vom
VCMo
A
A B
I
D
P
I
P
I
N

F
r
o
m

G
l
o
b
a
l

B
i
a
s
VB1
VB2
VB3
VB4
VB3
WLP/LLP
WLN/LLN
WLP/LLP
WLN/LLN
WLN/LLN
VB1
M1DAb
M1DAa
I
C
M
t
a
il
WLN/LLN
CM Amplifier
VB3
VB3
Optional split
transistor
Interdigitated
Transistors
Cc
Cc
I
P
WLP/LLP
I
D
P
I
N
M3a M3b
M4a M4b
Compensation options
Miller
Pole-zero cancelation
Indirect
Split transistor
Differential pair
Rail side current
98
Opamp Compensation
An Introduction to Miller Compensation
g2 CL
Vout
gm1.Vin
g1 C1
CC
gm2.V1
V1
For node V
1
:
gm
1
V
in
+ V
1

1
+V
1
s C
1
+
1

sC
C
=0
(1.1)
For node V
OUT
:
gm
2
V
1
+ V
OUT

2
+ V
2
sC
L
+


1
sC
C
=0
(1.2)
The transfer function
V
OUT
(s)
V
in
(S)
can be expressed as [33]:

V
out
(s)
V
in
(s)
=gm
1
r
1
gm
2
r
2
1-j
f
f
z

1-j
f
f
1
1-j
f
f
2

o
1
2

2
1-j
f
f
z

1-j
f
f
1
1-j
f
f
2

(1.3)

99
Opamp Compensation
An Introduction to Miller Compensation
g2 CL
Vout
gm1.Vin
g1 C1
CC
gm2.V1
V1
PM=180 ATAN

ATAN

ATAN

(1.1)
For f
z
= f
nondom
= 2f
u


PM=180 90 ATAN
1
2
ATAN
2
2
= 47 (1.1)

Table 1.1 Pole Zero locations of a two stage miller OTA
Parameter Value
DC gain
1
2

2

RHP Zero

gm
2
C
C

GBP

gm
1
C
C

Non- dominant pole
gm
2
C
C
C
C
C
g2
+C
C
C
L
+C
g2
C
L

~
gm
2
C
L

Dominant Pole

g1

2
C
C



f1
GBP
f2 fZ
0
-90
-180
f
f
dB
M
a
g
n
i
t
u
d
e
P
h
a
s
e
100
Opamp Compensation
Indirect Compensation some possible options
VDD VDD
VDD
Vout = V2
Vbias4
Vm
M2
2
CC
VP
1
MC1
M1a
M1b
Vbias2
A
MC2
Mi1 Mi2
Mi3
Mi4
VDD VDD
VDD
Vout = V2
Vbias4
Vm
M2
2
CC
VP
1
MC1
M1a
M1b
Vbias2
A
MC2
Mi1 Mi2
Mi3
Mi4
VDD
VB3
VDD
VDD
VB1
VB2
VSS
VDD
vop+
vm
M2a
CC
vP
MC1
M1a M1b
Mi1
Mi2
MC2 CC
M2b
MC3 MC4
Mi3
Mi4
MiT
Mi5
Mi6
vom
vxp
v1a v1b
vxn
VDD
VB3
VDD
VDD
VB1
VB2
VSS
VDD
V2+
Vm
M2a
CC
VP
MC1
M1a M1b
Mi1
Mi2
MC2 CC
M2b
MC3 MC4
Mi3
Mi4
MiT
Mi5
Mi6
V2-
Vxp
V1a V1b
Vxn
101
Cxp
vxp
gi
gmdf.vin
gmpvxp
gcc
v1
Cg2
gmnvxn gcc
vxn
CC
gi
Cxn
gm2v1 g2
CL
vo
vxp
Opamp Compensation
Indirect Compensation
The nodal equations can be written as:
Vo:
v
0
g
2
+ v
0
sC
L
+ gm
2
v
1
+ v
0
-v
xn
sC
C
=0
(1.1)
Vxn:
v
xn
sC
xn
+ v
xn
g
i
+ v
xn
-v
0
sC
C
+ v
xn
-v
1
g
cc
+ gm
n
v
xn
= 0
(1.2)
V1:
v
1
-v
xn
g
cc
- gm
n
v
xn
+ v
1
sC
g2
+ v
1
-v
xp
g
cc
- gm
p
v
xp
= 0
(1.3)
Vxp:
v
xp
s C
xp
+ v
xp
g
i
- gm
df
V
in
+ v
xp
-v
1
g
cc
+ gm
p
v
xp
= 0
(1.4)

102
Opamp Compensation
Indirect Compensation
Solving for the transfer function
V
OUT
(s)
V
in
(S)
, the prominent poles and zeros are summarized below
Table 1.1 Pole and zero locations for current injected at different nodes.
Parameter Value
LHP Zero

gm
C
C
+C
xn

gm
C
C

GBP

C
C

dominant

2gm
C
C

non
near

gm
2
C
C
C
g2
C
C
+C
L

=
e
2
C
C
C
C
+C
L

non
distant C
L
s
2
g
m

TA
+
C
C
+C
L
s
C
C

TA
+1=0

TA

gm
C
xn
K
r



103
Opamp Compensation
Indirect Compensation
Examining

C
L
s
2
g
m

TA
+
C
C
+C
L
s
C
C

TA
+1=0
(1.1)
where eTA = gm/Cxp. Comparing e
non
to the greater of the residual poles there are three cases of
interest.
pole CL<<Cc CL~ Cc CL>> Cc
e
2
C
C
C
C
+C
L

e
2

e
2
2

e
2
C
C
C
L

C
L
s
2
g
m

TA
+
C
C
+C
L
s
C
C

TA
+1=0
C
L
s
2
g
m

TA
+
s

TA
+1=0
C
C
s
2
g
m

TA
+
2 s

TA
+1=0
C
L
s
2
g
m

TA
+
C
L
s
C
C

TA
+1=0
Pole Comment
non
= gm/CL
non
= 2 gm/C
C

non
= gm/C
C


Summarizing
e
1
=

TA2

( + )
; e
2=
( + )
( )

e
2
gm
( + )
2
(CL
2
)
; e
1=
( + )
( )


PM= 180 90 +ATAN

ATAN

; for fz = 2 fu
PM= 180 63.4 ATAN

(1.1)

104
Cxp
vxp
gi
gmpvxp
gcc
v1
Cg2
gmnvxn gcc
vxn
CC
gi
Cxn
gm2v1 g2
CL
vo
gmdp.vin
CC
Opamp Compensation
Indirect Compensation with feedback at same node as ff

Since the main small signal current flows into the node V
XN
, we can ignore node V
XP
in the nodal analysis
by assuming the P side is near idea. Note this removes an e
TAp
pole. The nodal equations for the above
model are written as:
Vo:
v
0
g
2
+ v
0
sC
L
+ gm
2
v
1
+v
0
-v
xn
sC
C
= 0
(1.1)
V
xn
:
v
xn
sC
xn
+ v
xn
g
i
+ v
xn
-v
0
sC
C
+ v
xn
-v
1
g
cc
+ gm
n
v
xn
- gm
df
vin = 0
(1.2)
V
1
:
v
1
-v
xn
g
cc
- gm
n
v
xn
+ v
1
sC
g2
= 0
(1.3)

105
Opamp Compensation
Indirect Compensation with feedback at same node as ff

Cxp
vxp
gi
gmpvxp
gcc
v1
Cg2
gmnvxn gcc
vxn
CC
gi
Cxn
gm2v1 g2
CL
vo
gmdf.vin

Figure 1.1 Small signal model of OTA with compensation current injection at same node as input
transconductance.

Table 1.1 Pole and zero locations for current injected at same nodes
Parameter Value
Zeros

gm.gm
2
C
C
Cg
2

dominant
gm
C
C

2

GBP

C
C

non2
gmC
C
+C
L

C
c
C
L
=

C
C
+C
L

C
L

non1

gm
2
C
C
Cg
2
C
C
+C
L

=
e
2
C
C
C
C
+C
L

106
Opamp Compensation
Indirect Compensation with feedback at opposite nodes

VB3
VB4
VB1
VB2

VB3
VB4
VB1
VB2
VB1
Vop Vom
VB1
B
VCMo VCMREF
Vip Vim
VB1
Cc Cc
Cc
Cc Rz Rz
Vop Vom
VCMo
A
A B
I
D
P
I
P
I
N

F
r
o
m

G
l
o
b
a
l

B
i
a
s
VB1
VB2
VB3
VB4
VB3
WLP/LLP
WLN/LLN
WLP/LLP
WLN/LLN
WLN/LLN
VB1
M1DAb
M1DAa
I
C
M
t
a
il
WLN/LLN
CM Amplifier
VB3
VB3
Optional split
transistor
Interdigitated
Transistors
Cc
Cc
I
P
WLP/LLP
I
D
P
I
N
M3a M3b
M4a M4b
Pole-zero
Indirect
Split indirect PMOS I
Split indirect differential pair

107
Opamp Compensation
Compensation of Fully Differential

Cxp
vxp
gi
gmpvxp
gcc
v1
Cg2
gmnvxn gcc
vxn
CC
gi
Cxn
gm2v1 g2
CL
vo
gmdp.vin
CC
The nodal equations for the above p-z model can be written as:
vo:
gm2vo1 + vo(g2 + sCL + sCc) - vxsCc
(1.1)
vpz:
(vx - vo)sCc + (vx - vo1)Gz (1.2)
v1:
(vo1 - vs)g - gmvs + (vo1 - vx)Gz + vo1sCg2 (1.3)
vxn:
- gmdpvgi + vs(2g + gm) + vssCg - vo1g
(1.4)
Note the vxp will be assume to be ideal. Solving for the transfer function
V
OUT
(s)
V
in
(S)
,
Parameter Value
LHP Zero
Gz gm
( 2)

GBP

gmdp
C
C

dominant

2gm
C
C

non
near

gm
2
C
L

non1
distant

gm
C
xn
=
TA

TA2
distant

gm2
C
g2
=
TA
2

108
Opamp Compensation
Compensation of Fully Differential

Cxp
vxp
gi
gmpvxp
gcc
v1
Cg2
gmnvxn gcc
vxn
CC
gi
Cxn
gm2v1 g2
CL
vo
gmdp.vin
CC
Parameter Value
LHP Zero
GBP
dominant

non
near

non1
distant

TA2
distant

The drawback to p-z compensation is the
added power associated with bias circuit
for the MOS Rz that must track gm2.


109